ninja: Entering directory `out/gn'
[0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix)
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
-- Testing: 27910 tests, 64 workers --
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (1 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564e0754eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564e0751e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564e075562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6477e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6477ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6477e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6477e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564e06eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564e06eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564e06cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564e037ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564e037eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6477e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6477e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6477e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564e037ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (2 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056275b20eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056275b20be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056275b20f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2df2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2df22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2df2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2df2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056275b1a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056275b1a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056275b1898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056275ae38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056275ae38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2df2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2df22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2df22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056275ae38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (3 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571c5dd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571c5dd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571c5dd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63f3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63f3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63f3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63f3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571c5d6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571c5d6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571c5d508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571c59ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571c59ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63f3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63f3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63f3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571c59ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (4 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610365e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610365dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610365e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92a9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92a9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92a9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92a9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561036577bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561036577a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056103655c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056103620be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056103620bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92a9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92a9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92a9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056103620ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/thinlto_backend.ll (5 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# |  #0 0x000055a186feaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a186fe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a186feb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20d3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20d38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20d3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20d3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a186f80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a186f80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a186f658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a186c14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a186c14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20d3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20d38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20d38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a186c14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (6 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale
# | ...
# `---data was truncated (10240/70021) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ebf339eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ebf336e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ebf33a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5aa5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5aa518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5aa5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5aa511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ebf2cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ebf2cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ebf2b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ebef63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ebef63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5aa511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5aa511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5aa511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ebef63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (7 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e16df01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e16defee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e16df0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2dfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2dfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2dfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2dfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e16de97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e16de97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e16de7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e16db2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e16db2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2dfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2dfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2dfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e16db2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (8 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d56367eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d56364e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d5636862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9334a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9334aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9334a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9334a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d562fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d562fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d562e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d55f91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d55f91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9334a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9334a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9334a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d55f91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (9 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa8106beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa81068e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa8106c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafdcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafdcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafdcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafdcc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa81001bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa81001a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa80fe68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa80c95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa80c95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafdcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafdcc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafdcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa80c95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (10 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055850e6bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055850e6b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055850e6bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa67d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa67d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa67d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa67d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055850e651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055850e651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055850e6368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055850e2e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055850e2e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa67d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa67d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa67d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055850e2e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (11 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aec6cd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aec6ccee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aec6cd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6f7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6f7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6f7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6f7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aec6c67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aec6c67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aec6c4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aec68fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aec68fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6f7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6f7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6f7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aec68fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (12 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba168ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba168fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba1690062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa007705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa00775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa007705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0076ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba16895bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba16895a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba1687a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba16529e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba16529b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0076eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0076ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0076ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba16529a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (13 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fae64e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fae64e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fae64e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f117a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f117a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f117a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f117a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fae647bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fae647ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fae64608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fae610fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fae610fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f117a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f117a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f117a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fae610fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (14 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acb212feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055acb212ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055acb213062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe31e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe31e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe31e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe31e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acb20c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055acb20c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055acb20aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055acb1d59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055acb1d59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe31e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe31e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe31e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acb1d59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (15 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e26a871eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e26a86ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e26a87262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8561333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f856138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8561333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f856131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e26a807bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e26a807a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e26a7ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e26a49be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e26a49bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f856131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f856131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f856131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e26a49ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (16 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b38f6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b38f68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b38f6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff849733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff84978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff849733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff84971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b38f01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b38f01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b38ee68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b38b95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b38b95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff84971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff84971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff84971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b38b95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (17 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.
# | ...
# `---data was truncated (10240/17879) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056020b63deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056020b63ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056020b63e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa841d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa841d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa841d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa841d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056020b5d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056020b5d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056020b5b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056020b267e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056020b267b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa841d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa841d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa841d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056020b267a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (18 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6523e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6523e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6523e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99c1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99c1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99c1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99c1c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b65237cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b65237ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6523618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b652010e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b652010b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99c1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99c1c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99c1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b652010a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (19 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/100960) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ba30c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ba30c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ba30ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0910d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0910d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0910d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0910d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ba305fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ba305fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ba30448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ba2cf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ba2cf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0910d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0910d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0910d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ba2cf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (20 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055739bc9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055739bc9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055739bca062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6833d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6833d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6833d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6833d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055739bc35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055739bc35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055739bc1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055739b8c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055739b8c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6833d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6833d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6833d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055739b8c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (21 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055809cb5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055809cb5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055809cb5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0934733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f093478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0934733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f093471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055809caf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055809caf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055809cad98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055809c788e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055809c788b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f093471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f093471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f093471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055809c788a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (22 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/12433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056145e9cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056145e9c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056145e9cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97a671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056145e961bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056145e961a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056145e9468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056145e5f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056145e5f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97a671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056145e5f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (23 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %
# | ...
# `---data was truncated (10240/21774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da53f90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da53f8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da53f9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f216de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f216dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f216de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f216de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da53f26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da53f26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da53f0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da53bbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da53bbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f216de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f216de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f216de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da53bbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (24 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7e3e5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7e3e5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7e3e5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f719e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f719e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f719e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f719e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7e3df4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7e3df4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7e3dd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7e3a88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7e3a88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f719e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f719e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f719e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7e3a88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (25 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2bb416eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2bb413e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2bb41762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf37049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf37049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf37031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2bb3acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2bb3aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2bb3918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2bb040e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2bb040b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf37032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2bb040a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (26 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4
# | ...
# `---data was truncated (10240/25575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d47c5aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d47c5a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d47c5ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdeba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdebaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdeba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdeba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d47c540bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d47c540a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d47c5258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d47c1d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d47c1d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdeba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdeba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdeba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d47c1d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (27 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d7a66feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d7a66ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d7a67062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4b8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4b878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4b8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4b871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d7a605bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d7a605a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d7a5ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d7a299e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d7a299b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4b871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4b871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4b871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d7a299a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (28 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c78b60deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c78b60ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c78b60e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c49c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c49ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c49c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c49c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c78b5a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c78b5a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c78b5888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c78b237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c78b237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c49c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c49c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c49c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c78b237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (29 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |  
# | ...
# `---data was truncated (10240/29535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e474b61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e474b5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e474b6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d42533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d4258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d42533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d4251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e474af7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e474af7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e474adc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e47478be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e47478bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d4251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d4251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d4251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e47478ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (30 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b93b051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b93b04ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b93b05262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc96c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc96c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc96c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc96c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b93afe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b93afe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b93afcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b93ac7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b93ac7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc96c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc96c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc96c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b93ac7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (31 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0c6e03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0c6e00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0c6e0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0c6d99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0c6d99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0c6d7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0c6a2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0c6a2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7aa131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0c6a2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (32 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx
# | ...
# `---data was truncated (10240/78682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567480c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567480c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567480ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff268f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff268f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff268f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff268f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055674805fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055674805fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567480448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556747cf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556747cf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff268f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff268f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff268f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556747cf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (33 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f364a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f364a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f364a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a3c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a3c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a3c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a3c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f3643bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f3643ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f364208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f360cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f360cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a3c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a3c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a3c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f360cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (34 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c  -check-prefix=RV32ZKSH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a17e3a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a17e3a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a17e3a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0187a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0187aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0187a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0187a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a17e33cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a17e33ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a17e3218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a17dfd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a17dfd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0187a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0187a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0187a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a17dfd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (35 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/210435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621209fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621209fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621209fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45abc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45abca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45abc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45abc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562120993bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562120993a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621209788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562120627e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562120627b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45abc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45abc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45abc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562120627a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (36 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577b0b9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577b0b97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577b0b9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f490d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f490d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f490d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f490d6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577b0b30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577b0b30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577b0b158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577b07c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577b07c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f490d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f490d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f490d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577b07c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (37 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb1397beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb13978e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb1397c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd57849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd57849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd57831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb13911bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb13911a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb138f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb135a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb135a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd57832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd578330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb135a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (38 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e845216eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e845213e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e84521762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f875f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f875f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f875f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f875f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8451acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8451aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8451918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e844e40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e844e40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f875f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f875f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f875f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e844e40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (39 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %.splat, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e4f044ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4f0449e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4f044d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdc1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdc1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdc1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdc1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4f03e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4f03e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4f03c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4f0076e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4f0076b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdc1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdc1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdc1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4f0076a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (40 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615c2fa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615c2f9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615c2fa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4de8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4de818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4de8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4de811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615c2f36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615c2f36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615c2f1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615c2bcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615c2bcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4de811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4de811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4de811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615c2bcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (41 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bf1d90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bf1d8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bf1d9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4be249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4be2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4be249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4be231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bf1d26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bf1d26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bf1d0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bf19bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bf19bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4be232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4be2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4be2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bf19baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (42 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056004b2a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056004b2a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056004b2a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd61df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd61df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd61df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd61df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056004b23ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056004b23ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056004b2238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056004aed2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056004aed2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd61df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd61df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd61df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056004aed2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (43 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000557bf953beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bf9538e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bf953c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc4e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc4e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc4e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc4e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bf94d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bf94d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bf94b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bf9165e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bf9165b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc4e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc4e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc4e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bf9165a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (44 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b801a5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b801a5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b801a5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f741cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f741cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f741cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f741cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8019f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8019f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8019d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b801688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b801688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f741cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f741cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f741cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b801688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (45 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba9edd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba9edd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba9edd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2205e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2205ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2205e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2205e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba9ed6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba9ed6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba9ed528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba9ea01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba9ea01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2205e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2205e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2205e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba9ea01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (46 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055581a841eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055581a83ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055581a84262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a73a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a73aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a73a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a73a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055581a7d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055581a7d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055581a7bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055581a46be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055581a46bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a73a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a73a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a73a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055581a46ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (47 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bfe336eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bfe333e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bfe33762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49b891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bfe2ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bfe2cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bfe2b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bfdf60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bfdf60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49b891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bfdf60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (48 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bdd54beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bdd548e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bdd54c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd08505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd0855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd08505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd084ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bdd4e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bdd4e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bdd4c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bdd175e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bdd175b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd084eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd084ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd084ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bdd175a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (49 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e1cef6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e1cef3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e1cef762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc47b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc47b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc47b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc47b8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e1ce8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e1ce8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e1ce718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e1cb20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e1cb20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc47b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc47b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc47b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e1cb20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (50 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eea2c76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eea2c73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eea2c7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb235f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb235f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb235f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb235f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eea2c0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eea2c0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eea2bf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eea28a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eea28a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb235f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb235f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb235f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eea28a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (51 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, a
# | ...
# `---data was truncated (10240/98437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558df27d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558df27d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558df27d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb64333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb6438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb64333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb6431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558df276bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558df276ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558df27508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558df23ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558df23ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb6431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb6431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb6431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558df23ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (52 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ac02d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ac02d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ac02d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0827649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08276a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0827649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0827631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ac026dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ac026da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ac02528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555abff01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555abff01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0827632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08276330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08276330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555abff01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (53 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642e2f27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642e2f24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642e2f2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26a671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642e2ebdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642e2ebda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642e2ea28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642e2b51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642e2b51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26a671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642e2b51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (54 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu
# | ...
# `---data was truncated (10240/156765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e4aaedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e4aaeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e4aaee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb99f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb99f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb99f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb99f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e4aa83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e4aa83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e4aa688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e4a717e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e4a717b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb99f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb99f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb99f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e4a717a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (55 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563918c0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563918c07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563918c0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d01d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d01d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d01d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d01d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563918ba0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563918ba0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563918b858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563918834e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563918834b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d01d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d01d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d01d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563918834a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (56 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a646b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a646b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a646b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba2e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba2e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba2e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba2e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a6464ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a6464ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a646338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a642e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a642e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba2e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba2e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba2e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a642e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (57 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1q_gather_u64base_offset_f64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1q_gather_u64base_offset_f32(<vscale x 16 x i1> %pg, <vscale x 2 x
# | ...
# `---data was truncated (10240/58824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e8ee61ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8ee619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8ee61d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ef1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ef195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ef1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ef18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8ee5b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8ee5b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8ee5978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8ee246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8ee246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ef18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ef18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ef18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8ee246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (58 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ba7dabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ba7da8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ba7dac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7788733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f778878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7788733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f778871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ba7d41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ba7d41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ba7d268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ba79d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ba79d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f778871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f778871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f778871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ba79d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (59 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595c6dc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595c6dc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595c6dca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7345a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7345aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7345a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7345a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595c6d5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595c6d5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595c6d448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595c69f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595c69f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7345a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7345a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7345a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595c69f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (60 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e917c23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e917c20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e917c2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e5c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e5c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e5c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e5c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e917bb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e917bb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e917b9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e91784de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e91784db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e5c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e5c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e5c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e91784da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (61 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000563281f3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563281f37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563281f3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff32a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff32aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff32a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff32a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563281ed0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563281ed0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563281eb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563281b64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563281b64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff32a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff32a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff32a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563281b64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (62 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x
# | ...
# `---data was truncated (10240/93466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d69de4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d69de1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d69de562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff79401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7940725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff79401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff794003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d69d7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d69d7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d69d5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d69a0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d69a0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff794004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7940050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7940050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d69a0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (63 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564beca0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564beca0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564beca0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1fa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1fa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1fa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1fa71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bec9a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bec9a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bec9888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bec637e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bec637b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1fa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1fa71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1fa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bec637a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (64 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560da04f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560da04efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560da04f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bab649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bab6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bab649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bab631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560da0488bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560da0488a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560da046d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560da011ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560da011cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bab632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bab6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bab6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560da011ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (65 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccfa4c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccfa4bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccfa4c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2be0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2be098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2be0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2be091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccfa458bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccfa458a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccfa43d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccfa0ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccfa0ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2be091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2be091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2be091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccfa0eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (66 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub
# | ...
# `---data was truncated (10240/84979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623f7ed7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623f7ed4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623f7ed862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b35449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b354a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b35449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b35431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623f7e6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623f7e6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623f7e528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623f7b01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623f7b01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b35432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b354330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b354330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623f7b01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (67 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586ec25eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586ec25be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586ec25f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f700cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f700cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f700cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f700cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586ec1f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586ec1f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586ec1d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586ebe88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586ebe88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f700cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f700cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f700cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586ebe88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (68 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d5360feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d5360ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d5361062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a28649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a286a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a28649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a28631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d535a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d535a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d5358a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d53239e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d53239b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a28632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a286330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a286330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d53239a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (69 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/68065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055994d240eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055994d23de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055994d24162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86ed849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86ed8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86ed849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86ed831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055994d1d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055994d1d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055994d1bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055994ce6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055994ce6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86ed832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86ed8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86ed8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055994ce6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (70 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5
# | ...
# `---data was truncated (10240/15508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055923d4f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055923d4f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055923d4fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2d7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2d7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2d7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2d7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055923d48fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055923d48fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055923d4748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055923d123e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055923d123b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2d7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2d7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2d7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055923d123a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (71 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615cbb8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615cbb87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615cbb8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0f4d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0f4d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0f4d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0f4ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615cbb20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615cbb20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615cbb058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615cb7b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615cb7b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0f4ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0f4cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0f4cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615cb7b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (72 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056304798aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563047987e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056304798b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4cea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4cea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4cea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4cea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563047920bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563047920a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630479058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630475b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630475b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4cea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4cea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4cea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630475b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (73 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565228c55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565228c52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565228c5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0bf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0bf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0bf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0bf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565228bebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565228beba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565228bd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056522887fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056522887fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0bf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0bf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0bf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056522887fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (74 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |  
# | ...
# `---data was truncated (10240/19083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6af6abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6af6a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6af6ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9238305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f923835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9238305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92382ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6af641bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6af641a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6af6268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6af2d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6af2d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92382eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92382ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92382ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6af2d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (75 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebb9095eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebb9092e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebb909662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f84b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f84b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f84b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f84b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebb902bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebb902ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebb90108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebb8cbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebb8cbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f84b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f84b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f84b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebb8cbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (76 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be9e1abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be9e1a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be9e1ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5e5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5e598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5e5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5e591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be9e141bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be9e141a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be9e1268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be9ddd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be9ddd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5e591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5e591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5e591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be9ddd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (77 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrte_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrte_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrte_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000559f994e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f994e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f994e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd006d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd006d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd006d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd006d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f9947abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f9947aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f9945f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f9910ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f9910eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd006d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd006d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd006d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f9910ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (78 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db6d56deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db6d56ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db6d56e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f674a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f674a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f674a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f674a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db6d503bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db6d503a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db6d4e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db6d197e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db6d197b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f674a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f674a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f674a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db6d197a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (79 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/13593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f163257eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f163254e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f16325862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0a5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0a54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0a5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0a5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1631edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1631eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1631d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f162e81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f162e81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0a5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0a54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0a54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f162e81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (80 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557920a02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579209ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557920a0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98af649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98af6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98af649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98af631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557920998bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557920998a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055792097d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055792062ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055792062cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98af632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98af6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98af6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055792062ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (81 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale
# | ...
# `---data was truncated (10240/156471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6d60fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6d60f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6d60fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfabb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfabb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfabb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfabaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6d6092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6d6092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6d60778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6d5d26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6d5d26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfabaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfabaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfabaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6d5d26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (82 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> 
# | ...
# `---data was truncated (10240/63117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055f662747eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f662744e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f66274862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27dee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27dee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27dee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27dee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6626ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6626dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6626c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f662371e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f662371b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27dee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27dee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27dee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f662371a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (83 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056357077beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563570778e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056357077c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc92e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc92e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc92e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc92e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563570711bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563570711a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635706f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635703a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635703a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc92e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc92e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc92e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635703a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (84 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clastb.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005654f5e60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654f5e5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654f5e6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fead1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fead115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fead1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fead10ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654f5df6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654f5df6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654f5ddb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654f5a8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654f5a8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fead10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fead10ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fead10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654f5a8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (85 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056461c914eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056461c911e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056461c91562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb307f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb307f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb307f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb307f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056461c8aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056461c8aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056461c88f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056461c53ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056461c53eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb307f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb307f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb307f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056461c53ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (86 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_f16_f16(
# | ...
# `---data was truncated (10240/27272) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564c833e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c833e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c833e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2776649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27766a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2776649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2776631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c8337ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c8337ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c833638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c83012e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c83012b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2776632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27766330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27766330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c83012a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (87 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde
# | ...
# `---data was truncated (10240/16083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558aded3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aded39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aded3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d5e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d5e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d5e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d5e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558adecd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558adecd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558adecb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ade966e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ade966b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d5e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d5e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d5e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ade966a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (88 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpklo_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560801804eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560801801e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056080180562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4e5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4e5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4e5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4e5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056080179abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056080179aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056080177f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056080142ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056080142eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4e5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4e5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4e5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056080142ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (89 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cbf89c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbf89c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbf89c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f633801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63380725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f633801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6338003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbf895dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbf895da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbf89428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbf85f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbf85f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6338004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63380050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63380050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbf85f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (90 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde
# | ...
# `---data was truncated (10240/31748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cec35e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cec35e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cec35e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff679d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff679d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff679d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff679d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cec357bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cec357ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cec35608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cec320fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cec320fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff679d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff679d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff679d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cec320fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (91 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvtn_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvtn_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_loc
# | ...
# `---data was truncated (10240/17734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560d7b4d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d7b4d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d7b4d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb17e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb17e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb17e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb17e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d7b46cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d7b46ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d7b4518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d7b100e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d7b100b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb17e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb17e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb17e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d7b100a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (92 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558be03edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558be03eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558be03ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7944249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79442a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7944249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7944231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558be0383bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558be0383a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558be03688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558be0017e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558be0017b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7944232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79442330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79442330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558be0017a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (93 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563e734efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e734ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e734f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c92333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c9238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c92333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c9231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e73485bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e73485a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e7346a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e73119e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e73119b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c9231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c9231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c9231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e73119a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (94 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/94149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560936053eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560936050e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056093605462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fdda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fdda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fdda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560935fe9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560935fe9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560935fce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560935c7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560935c7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fdda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fdda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fdda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560935c7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (95 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6df69aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6df697e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6df69b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb97533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb9758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb97533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb9751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6df630bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6df630a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6df6158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6df2c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6df2c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb9751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb9751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb9751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6df2c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (96 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <8 x i16> %2, %3
# |   store <8 x i16> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <4 x i32> %2, %3
# |   store <4 x i32> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   s
# | ...
# `---data was truncated (10240/798827) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d766d29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d766d26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d766d2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd87d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd87d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd87d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd87d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d766cbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d766cbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d766ca48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d766953e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d766953b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd87d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd87d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd87d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d766953a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (97 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555a6aa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555a6aa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555a6aaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d2d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d2d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d2d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d2d6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555a6a3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555a6a3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555a6a248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555a66d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555a66d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d2d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d2d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d2d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555a66d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (98 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555600698eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555600695e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055560069962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdff761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdff76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdff761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdff7603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055560062ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055560062ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556006138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556002c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556002c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdff7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdff76050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdff76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556002c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (99 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfa
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055daf3b01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055daf3afee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055daf3b0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f001b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f001b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f001b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f001b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daf3a97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055daf3a97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055daf3a7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055daf372be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055daf372bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f001b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f001b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f001b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daf372ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (100 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565172d0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565172d0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565172d0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba59333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba5938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba59333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba5931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565172ca3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565172ca3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565172c888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565172937e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565172937b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba5931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba5931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba5931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565172937a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (101 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb9f585eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb9f582e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb9f58662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51e4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51e478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51e4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51e471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb9f51bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb9f51ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb9f5008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb9f1afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb9f1afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51e471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51e471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51e471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb9f1afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (102 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i
# | ...
# `---data was truncated (10240/40929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a03a29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a03a26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a03a2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83fb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83fb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83fb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83fb603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a039bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a039bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a039a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a03653e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a03653b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83fb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83fb6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83fb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a03653a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (103 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.ad
# | ...
# `---data was truncated (10240/16274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056473a60aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056473a607e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056473a60b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb105a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb105aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb105a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb105a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056473a5a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056473a5a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056473a5858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056473a234e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056473a234b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb105a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb105a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb105a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056473a234a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (104 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3fa89deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3fa89ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3fa89e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e53e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e53ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e53e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e53e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3fa833bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3fa833a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3fa8188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3fa4c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3fa4c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e53e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e53e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e53e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3fa4c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (105 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005598b2726eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598b2723e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598b272762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cd301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cd30725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cd301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cd3003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598b26bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598b26bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598b26a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598b2350e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598b2350b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cd3004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cd30050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cd30050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598b2350a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (106 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d32c862eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d32c85fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d32c86362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f818e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f818e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f818e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f818e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d32c7f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d32c7f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d32c7dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d32c48ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d32c48cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f818e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f818e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f818e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d32c48ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (107 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bf9652eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bf964fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bf965362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe780933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe78098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe780933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe78091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bf95e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bf95e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bf95cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bf927ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bf927cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe78091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe78091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe78091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bf927ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (108 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_s64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 7)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_u8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_s8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562e10a4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e10a47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e10a4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc51333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc5138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc51333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc5131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e109e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e109e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e109c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e10674e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e10674b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc5131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc5131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc5131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e10674a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (109 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561259d9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561259d97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561259d9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2759305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f275935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2759305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27592ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561259d30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561259d30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561259d158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612599c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612599c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27592eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27592ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27592ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612599c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630e923deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630e923ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630e923e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe672b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe672b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe672b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe672b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630e91d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630e91d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630e91b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630e8e67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630e8e67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe672b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe672b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe672b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630e8e67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, bflo
# | ...
# `---data was truncated (10240/43940) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b81449eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b81446e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b8144a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe230705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe23075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe230705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2306ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b813dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b813dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b813c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b81073e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b81073b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2306eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2306ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2306ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b81073a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bb5a4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bb5a47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bb5a4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab97049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab970a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab97049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab97031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bb59e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bb59e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bb59c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bb5674e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bb5674b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab97032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab970330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab970330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bb5674a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (113 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a55630eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a5562de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a5563162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c49f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c49f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c49f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c49f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a555c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a555c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a555ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a5525ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a5525ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c49f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c49f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c49f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a5525aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (114 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cd63fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cd63f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cd63fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d9b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d9b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d9b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d9b2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cd6392bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cd6392a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cd63778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cd6026e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cd6026b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d9b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d9b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d9b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cd6026a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (115 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560720c9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560720c98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560720c9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa891449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8914a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa891449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa891431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560720c31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560720c31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560720c168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607208c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607208c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa891432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8914330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8914330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607208c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (116 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbc3278eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbc3275e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbc327962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe555f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe555f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe555f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe555f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbc320ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbc320ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbc31f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbc2ea2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbc2ea2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe555f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe555f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe555f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbc2ea2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (117 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4e981beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4e9818e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4e981c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1058f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1058f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1058f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1058f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4e97b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4e97b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4e97968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4e9445e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4e9445b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1058f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1058f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1058f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4e9445a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (118 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <8 x half>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <4 x float>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056037985eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056037985be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056037985f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34c7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34c74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34c7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34c7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603797f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603797f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603797d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560379488e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560379488b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34c7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34c74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34c74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560379488a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (119 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m2_i8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m4_i8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m8_i8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m4_i8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m8_i8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_i8m8_i8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m2_u8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m4_u8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m8_u8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m4_u8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m8_u8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_u8m8_u8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m2_i16m1(<vscale x 8 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m4_i16m1(<vscale x 16 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m8_i16m1(<vscale x 32 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale
# | ...
# `---data was truncated (10240/40902) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055869249feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055869249ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586924a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe28d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe28d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe28d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe28d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558692435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558692435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055869241a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586920c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586920c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe28d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe28d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe28d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586920c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (120 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056375cc9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056375cc98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056375cc9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78ee049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78ee0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78ee049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78ee031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056375cc31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056375cc31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056375cc168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056375c8c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056375c8c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78ee032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78ee0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78ee0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056375c8c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (121 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc9f051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc9f04ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc9f05262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12c8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12c86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12c8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12c8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc9efe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc9efe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc9efcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc9ec7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc9ec7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12c8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12c86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12c86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc9ec7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (122 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559df2dbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559df2db7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559df2dbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f438bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f438bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f438bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f438bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559df2d50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559df2d50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559df2d358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559df29e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559df29e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f438bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f438bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f438bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559df29e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (123 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vsc
# | ...
# `---data was truncated (10240/65701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6ce3a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6ce3a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6ce3a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f906d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f906d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f906d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f906d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6ce33abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6ce33aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6ce31f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6cdfcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6cdfceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f906d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f906d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f906d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6cdfcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (124 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e428680eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e42867de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e42868162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16abb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16abb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16abb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16abb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e428616bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e428616a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4285fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4282aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4282aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16abb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16abb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16abb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4282aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (125 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddd9e06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddd9e03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddd9e0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb54c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb54ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb54c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb54c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddd9d9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddd9d9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddd9d818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddd9a30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddd9a30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb54c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb54c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb54c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddd9a30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (126 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_u8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_s8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a944dcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a944dcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a944dd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc24e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc24e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc24e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc24e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a944d65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a944d65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a944d4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9449f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9449f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc24e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc24e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc24e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9449f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (127 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564590567eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564590564e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056459056862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f274e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f274e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f274e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f274e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645904fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645904fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645904e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564590191e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564590191b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f274e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f274e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f274e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564590191a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (128 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582301f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582301f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582301f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c2b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c2b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c2b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c2b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055823018ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055823018ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582301738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055822fe22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055822fe22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c2b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c2b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c2b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055822fe22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (129 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597a4212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597a420fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597a421362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bad733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bad78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bad733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bad71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597a41a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597a41a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597a418d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597a3e3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597a3e3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bad71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bad71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bad71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597a3e3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568e0b46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568e0b43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568e0b4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00c5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00c578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00c5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00c571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568e0adcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568e0adca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568e0ac18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568e0770e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568e0770b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00c571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00c571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00c571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568e0770a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a28cda7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a28cda4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a28cda862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aec91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a28cd3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a28cd3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a28cd228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a28c9d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a28c9d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0aec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aec91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a28c9d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (132 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x half>, ptr %0, align 2
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x float>, ptr %0, align 4
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i8>, ptr %0, align 1
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i8>, ptr %0, align 1
# |   %2 = sext <4 x i8> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = a
# | ...
# `---data was truncated (10240/50873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a1a15feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a1a15ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a1a16062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e5a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e5a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e5a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e5a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a1a0f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a1a0f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a1a0da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a19d89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a19d89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e5a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e5a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e5a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a19d89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (133 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willre
# | ...
# `---data was truncated (10240/273697) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6a60e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6a60e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6a60e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb01be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb01bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb01be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb01be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6a607bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6a607ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6a60608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6a5d0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6a5d0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb01be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb01be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb01be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6a5d0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (134 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_s16_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, i32 16)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/33461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056351e82aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056351e827e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056351e82b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8287505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f828755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8287505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82874ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056351e7c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056351e7c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056351e7a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056351e454e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056351e454b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82874eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82874ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82874ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056351e454a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (135 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d884a79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d884a76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d884a7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f484a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f484a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f484a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f484a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d884a0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d884a0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8849f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8846a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8846a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f484a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f484a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f484a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8846a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (136 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# | 
# | ...
# `---data was truncated (10240/23662) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563f94f88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f94f85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f94f8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e1f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e1f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e1f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e1f0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f94f1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f94f1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f94f038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f94bb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f94bb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e1f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e1f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e1f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f94bb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (137 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4
# | ...
# `---data was truncated (10240/17583) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055955c780eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055955c77de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055955c78162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6f441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6f44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6f441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6f4403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055955c716bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055955c716a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055955c6fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055955c3aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055955c3aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6f4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6f44050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6f44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055955c3aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (138 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %and = and <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @or_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %or = or <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @xor_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vsca
# | ...
# `---data was truncated (10240/18831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000564aa8f73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564aa8f70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564aa8f7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa427849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4278a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa427849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa427831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aa8f09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aa8f09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aa8eee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aa8b9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aa8b9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa427832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4278330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4278330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aa8b9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639e45e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639e45e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639e45e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1bf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1bf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1bf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1bf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639e457cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639e457ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639e45618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639e4210e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639e4210b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa1bf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1bf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1bf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639e4210a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (140 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpa_f16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpa_f32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svexpa_f64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556fa3ce6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fa3ce3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fa3ce762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32f4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32f4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32f4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32f4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fa3c7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fa3c7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fa3c618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fa3910e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fa3910b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32f4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32f4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32f4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fa3910a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561081244eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561081241e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056108124562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610811dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610811daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610811bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561080e6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561080e6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facc6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561080e6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (142 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 0
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 1
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056494cfe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056494cfe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056494cfe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ab7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ab72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ab7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ab7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056494cf7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056494cf7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056494cf618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056494cc10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056494cc10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ab7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ab72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ab72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056494cc10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/80648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa942b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa942b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa942b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd35d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd35d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd35d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd35d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa9424ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa9424ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa942338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa93ee2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa93ee2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd35d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd35d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd35d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa93ee2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (144 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b7fb3d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7fb3cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7fb3d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1db981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1db98725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1db981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1db9803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7fb367bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7fb367a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7fb34c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7faffbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7faffbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1db9804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1db98050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1db98050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7faffba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (145 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   
# | ...
# `---data was truncated (10240/11488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a0eb7aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0eb7abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0eb7af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b53d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b53d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b53d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b53ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0eb744bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0eb744a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0eb7298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0eb3d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0eb3d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b53ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b53cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b53cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0eb3d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (146 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp ule <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp sle <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp ule <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0cec87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0cec84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0cec8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eb8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eb82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eb8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eb8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0cec1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0cec1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0cec028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0ce8b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0ce8b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2eb8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eb82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eb82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0ce8b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (147 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 3
# |   %14 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 3
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, <vscale x 8 x half> %10, <vscale x 8 x half> %11, <vscale x 8 x half> %12, <vscale x 8 x half> %13, <vscale x 8 x half> %15, <vscale x 8 x half> %16, <vscale x 8 x half> %17, <vscale x 8 x half> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/34400) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563c8780deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c8780ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c8780e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd8bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd8bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd8bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd8bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c877a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c877a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c877888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c87437e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c87437b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd8bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd8bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd8bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c87437a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (148 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604d37f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604d37ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604d37f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdb7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdb7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdb7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdb7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604d3786bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604d3786a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604d376b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604d341ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604d341ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdb7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdb7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdb7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604d341aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (149 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cb8813eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cb8810e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cb881462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6083705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f608375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6083705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60836ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cb87a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cb87a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cb878e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cb843de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cb843db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60836eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60836ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60836ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cb843da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (150 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %
# | ...
# `---data was truncated (10240/93831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055dd1fe06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd1fe03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd1fe0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba7e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba7e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba7e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba7e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd1fd9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd1fd9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd1fd818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd1fa30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd1fa30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba7e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba7e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba7e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd1fa30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (151 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1)
# |   store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.fptosi.sat.i64.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   st
# | ...
# `---data was truncated (10240/53064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614aac1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614aac18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614aac1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faed5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faed54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faed5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faed5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614aabb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614aabb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614aab968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614aa845e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614aa845b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faed5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faed54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faed54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614aa845a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (152 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005605ecfd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605ecfd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605ecfd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f033ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f033ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f033ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f033ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605ecf6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605ecf6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605ecf4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605ecbfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605ecbfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f033ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f033ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f033ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605ecbfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (153 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b6ef78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b6ef75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b6ef7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78af649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78af6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78af649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78af631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b6ef0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b6ef0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b6eef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b6eba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b6eba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78af632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78af6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78af6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b6eba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (154 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005599af75deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599af75ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599af75e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ab5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ab578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ab5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ab571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599af6f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599af6f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599af6d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599af387e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599af387b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ab571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ab571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ab571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599af387a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (155 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056369c6e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056369c6e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056369c6e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ee1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ee14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ee1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ee1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056369c67ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056369c67ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056369c6638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056369c312e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056369c312b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ee1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ee14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ee14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056369c312a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (156 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 1
# |   %6 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | ...
# `---data was truncated (10240/24605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055587a7fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055587a7f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055587a7fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d12105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d1215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d12105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d120ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055587a791bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055587a791a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055587a7768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055587a425e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055587a425b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d120eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d120ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d120ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055587a425a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (157 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1
# | ...
# `---data was truncated (10240/26476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e7950eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e7950be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e7950f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd36ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd36baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd36ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd36ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e794a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e794a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e794898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e79138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e79138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd36ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd36ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd36ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e79138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (158 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c95a87feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c95a87ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c95a88062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd8a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd8a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd8a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd8a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c95a815bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c95a815a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c95a7fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c95a4a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c95a4a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd8a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd8a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd8a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c95a4a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (159 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c55db7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c55db4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c55db862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ab8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ab8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ab8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ab8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c55d4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c55d4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c55d328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c559e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c559e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ab8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ab8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ab8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c559e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (160 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ec7a891eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec7a88ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec7a89262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa9d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa9d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa9d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa9d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec7a827bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec7a827a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec7a80c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec7a4bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec7a4bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa9d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa9d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa9d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec7a4bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/153813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c63bb9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c63bb9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c63bb9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c91849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c918a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c91849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c91831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c63bb33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c63bb33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c63bb188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c63b7c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c63b7c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c91832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c918330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c918330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c63b7c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 64 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, al
# | ...
# `---data was truncated (10240/30013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c46c046eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c46c043e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c46c04762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fa2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fa258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fa2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fa251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c46bfdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c46bfdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c46bfc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c46bc70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c46bc70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fa251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fa251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fa251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c46bc70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (163 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale
# | ...
# `---data was truncated (10240/79489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055def12b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055def12b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055def12b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4490e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4490e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4490e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4490e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055def1249bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055def1249a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055def122e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055def0edde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055def0eddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4490e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4490e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4490e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055def0edda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (164 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593b6b49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593b6b46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593b6b4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c37733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c3778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c37733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c3771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593b6adfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593b6adfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593b6ac48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593b6773e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593b6773b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c3771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c3771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c3771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593b6773a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (165 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
# | ...
# `---data was truncated (10240/37760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f6be68eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6be68be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6be68f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb9c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb9c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb9c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb9c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6be624bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6be624a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6be6098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6be2b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6be2b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb9c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb9c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb9c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6be2b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (166 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/75656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005578ba08beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578ba088e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578ba08c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb063133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb06318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb063133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb06311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578ba021bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578ba021a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578ba0068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578b9cb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578b9cb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb06311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb06311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb06311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578b9cb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (167 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562679b9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562679b98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562679b9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7785849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77858a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7785849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7785831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562679b31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562679b31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562679b168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626797c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626797c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7785832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77858330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77858330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626797c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (168 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056209713aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562097137e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056209713b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecb4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecb4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecb4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecb4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620970d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620970d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620970b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562096d64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562096d64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecb4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecb4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecb4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562096d64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (169 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4b2b43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4b2b40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4b2b4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50e8105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50e815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50e8105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50e80ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4b2ad9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4b2ad9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4b2abe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4b276de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4b276db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50e80eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50e80ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50e80ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4b276da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (170 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmax_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmax_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055739a4a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055739a4a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055739a4a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e8ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e8cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e8ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e8ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055739a43dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055739a43da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055739a4228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055739a0d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055739a0d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e8ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e8ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e8ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055739a0d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (171 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055865f96feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055865f96ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055865f97062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8c6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8c6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8c6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8c6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055865f905bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055865f905a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055865f8ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055865f599e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055865f599b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8c6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8c6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8c6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055865f599a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (172 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd
# | ...
# `---data was truncated (10240/215044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056468824beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564688248e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056468824c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26c5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26c54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26c5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26c5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646881e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646881e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646881c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564687e75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564687e75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26c5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26c54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26c54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564687e75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (173 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svrshl_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svrshl_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> 
# | ...
# `---data was truncated (10240/93119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555b94ddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b94dd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b94ddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06c9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06c918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06c9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06c911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b94d72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b94d72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b94d578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b94a06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b94a06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06c911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06c911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06c911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b94a06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve/minv.c (174 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005651116a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651116a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651116a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f241dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f241dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f241dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f241dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056511163cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056511163ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651116218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651112d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651112d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f241dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f241dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f241dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651112d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (175 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e72c039eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e72c036e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e72c03a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe443533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe44358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe443533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe44351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e72bfcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e72bfcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e72bfb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e72bc63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e72bc63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe44351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe44351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe44351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e72bc63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (176 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v
# | ...
# `---data was truncated (10240/18520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d662126eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d662123e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d66212762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0a8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0a80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0a8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0a8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6620bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6620bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6620a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d661d50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d661d50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0a8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0a80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0a80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d661d50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (177 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e26a3c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e26a3bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e26a3c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8791705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f879175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8791705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87916ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e26a357bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e26a357a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e26a33c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e269febe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e269febb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87916eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87916ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87916ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e269feba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (178 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563839829eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563839826e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056383982a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e7c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e7c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e7c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e7c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638397bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638397bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638397a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563839453e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563839453b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e7c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e7c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e7c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563839453a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (179 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c2646cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2646c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2646cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64cf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64cf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64cf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64cf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c264661bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c264661a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2646468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2642f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2642f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64cf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64cf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64cf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2642f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c545d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c545d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c545d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1127733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f112778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1127733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f112771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c5456ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c5456ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c545538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c54202e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c54202b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f112771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f112771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f112771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c54202a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (181 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cc8eca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc8eca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc8eca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4da1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4da18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4da1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4da1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc8ec3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc8ec3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc8ec208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc8e8cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc8e8cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4da1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4da18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4da18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc8e8cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (182 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_u8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_u16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_u32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_u64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svinsr_n_f16(<vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> %0, half %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half>, half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svinsr_n_f32(<vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> %0, float %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float>, float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svinsr_n_f64(<vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load double, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> %0, double %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double>, double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svinsr_n_bf16(<vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat>, bfloat) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055faebb6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055faebb6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055faebb6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2f2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2f24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2f2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2f2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faebb03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055faebb03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055faebae88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055faeb797e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055faeb797b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2f2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2f24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2f24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faeb797a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (183 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ed2adfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ed2adce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ed2ae062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f1d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f1d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f1d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f1d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ed2a75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ed2a75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ed2a5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ed2709e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ed2709b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f1d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f1d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f1d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ed2709a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (184 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/77120) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fbd2f24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbd2f21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbd2f2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81f6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81f64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81f6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81f6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbd2ebabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbd2ebaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbd2e9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbd2b4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbd2b4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81f6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81f64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81f64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbd2b4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (185 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 7
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x float>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_vnum_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x double>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"
# | ...
# `---data was truncated (10240/10573) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f226657eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f226654e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f22665862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc20da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc20daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc20da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc20da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2265edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2265eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2265d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f226281e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f226281b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc20da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc20da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc20da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f226281a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (186 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555a4a07deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a4a07ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a4a07e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc03d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc03d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc03d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc03d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a4a013bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a4a013a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a49ff88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a49ca7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a49ca7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc03d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc03d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc03d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a49ca7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (187 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056441bd7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056441bd7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056441bd7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe351533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe35158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe351533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe35151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056441bd14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056441bd14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056441bcf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056441b9a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056441b9a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe35151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe35151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe35151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056441b9a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (188 of 27910)
******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @_Z9cond_boolu10__SVBool_tS_(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ult <vscale x 16 x i1> %0, %1
# |   %2 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %vector_select = select <vscale x 16 x i1> %cmp, <vscale x 16 x i1> %2, <vscale x 16 x i1> %3
# |   ret <vscale x 16 x i1> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_i8u10__SVInt8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_u8u11__SVUint8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_i16u11__SVInt16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_u16u12__SVUint16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_i32u11__SVInt32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_u32u12__SVUint32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_i64u11__SVInt64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_u64u12__SVUint64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @_Z8cond_f16u13__SVFloat16_tS_(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x half> %2, <vscale x 8 x half> %3
# |   ret <vscale x 8 x half> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @_Z8cond_f32u13__SVFloat32_tS_(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %3 = load <vs
# | ...
# `---data was truncated (10240/16444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005575d5c33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575d5c30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575d5c3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff472e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff472ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff472e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff472e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575d5bc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575d5bc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575d5bae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575d585de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575d585db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff472e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff472e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff472e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575d585da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (189 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557e851f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e851f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e851f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16a9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16a9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16a9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16a9eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e8518cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e8518ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e851718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e84e20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e84e20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16a9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16a9eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16a9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e84e20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (190 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ede2175eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ede2172e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ede217662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e7f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e7f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e7f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e7f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ede210bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ede210ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ede20f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ede1d9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ede1d9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e7f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e7f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e7f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ede1d9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (191 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/11908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056482513aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564825137e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056482513b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d0af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d0af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d0af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d0af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648250d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648250d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648250b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564824d64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564824d64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d0af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d0af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d0af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564824d64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (192 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 
# | ...
# `---data was truncated (10240/43617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570d6634eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570d6631e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570d663562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91ac733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91ac78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91ac733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91ac71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570d65cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570d65caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570d65af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570d625ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570d625eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91ac71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91ac71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91ac71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570d625ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (193 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d05645feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d05645ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d05646062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e70733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e7078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e70733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e7071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0563f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0563f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0563da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d056089e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d056089b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e7071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e7071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e7071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d056089a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (194 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b8d391eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b8d38ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b8d39262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f876fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f876fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f876fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f876fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b8d327bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b8d327a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b8d30c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b8cfbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b8cfbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f876fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f876fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f876fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b8cfbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm64-lanes.c (195 of 27910)
******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %src, ptr %src.addr, align 8
# |   %0 = load <2 x float>, ptr %src.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vdups_lane = extractelement <2 x float> %1, i32 0
# |   store float %vdups_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <1 x double>, ptr %src.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vdupd_lane = extractelement <1 x double> %1, i32 0
# |   store double %vdupd_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560321368eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560321365e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056032136962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9613533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f961358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9613533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f961351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603212febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603212fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603212e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560320f92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560320f92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f961351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f961351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f961351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560320f92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (196 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056423d3b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056423d3b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056423d3b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30b2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30b235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30b2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30b22ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056423d349bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056423d349a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056423d32e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056423cfdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056423cfddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30b22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30b22ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30b22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056423cfdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (197 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2, <vscale x 16 x i8> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %data.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 0
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 1
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 2
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 3
# |   call void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, <vscale x 16 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2, <vscale x 8 x i16> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %data.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 0
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 1
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 2
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 3
# |   %11 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10, <vscale x 8 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2, <vscale x 4 x i32> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %data.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 0
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 1
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 2
# |   %10 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 3
# |   %11 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10, <vscale x 4 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2, <vscale x 2 x i64> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %da
# | ...
# `---data was truncated (10240/73307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fd333f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd333f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd333f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5959e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5959e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5959e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5959e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd3338ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd3338ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd333738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd33022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd33022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5959e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5959e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5959e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd33022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (198 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597e92a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597e929ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597e92a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bd5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bd54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bd5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bd5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597e9237bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597e9237a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597e921c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597e8ecbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597e8ecbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bd5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bd54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bd54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597e8ecba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (199 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560ddb343eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ddb340e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ddb34462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d8dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d8dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d8dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d8dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ddb2d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ddb2d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ddb2be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ddaf6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ddaf6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d8dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d8dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d8dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ddaf6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (200 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamax_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svamax_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 0
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 1
# |   %10 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %8, <vscale x 4 x float> %9)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svamax_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm.coerce0, <vscale x 2 x double> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %zm.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 1
# |   %7 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 0
# |   %9 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 1
# |   %10 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double> %5, <vscale x 2 x double> %6, <vscale x 2 x double> %8, <vscale x 2 x double> %9)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamin_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8
# | ...
# `---data was truncated (10240/45703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056549a2beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056549a2bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056549a2bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f034f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f034f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f034f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f034f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056549a254bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056549a254a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056549a2398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565499ee8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565499ee8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f034f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f034f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f034f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565499ee8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (201 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x
# | ...
# `---data was truncated (10240/51854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055eb0e4cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb0e4cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb0e4d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4c9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4c9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4c9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4c9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb0e465bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb0e465a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb0e44a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb0e0f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb0e0f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4c9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4c9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4c9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb0e0f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (202 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563b1394eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b1394be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b1394f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d41b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d41b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d41b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d41aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b138e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b138e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b138c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b13578e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b13578b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d41aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d41aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d41aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b13578a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (203 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalb_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef43611eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef4360ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef4361262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe220333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe22038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe220333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe22031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef435a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef435a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef4358c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef4323be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef4323bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe22031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe22031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe22031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef4323ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (204 of 27910)
******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - |     /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | @X = global i32 0, align 4
# | @Y = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @foo() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %i = alloca i32, align 4
# |   store i32 0, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %entry
# |   %0 = load i32, ptr %i, align 4
# |   %cmp = icmp slt i32 %0, 100
# |   br i1 %cmp, label %for.body, label %for.end
# | 
# | for.body:                                         ; preds = %for.cond
# |   br label %for.end
# | 
# | for.inc:                                          ; No predecessors!
# |   %1 = load i32, ptr %i, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.end:                                          ; preds = %for.body, %for.cond
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type]
# |    13 | }
# |       | ^
# | 1 warning generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# |  #0 0x0000557ffec42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ffec3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ffec4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ce7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ce718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ce7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ce711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ffebd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ffebd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ffebbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ffe86ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ffe86cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ce711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ce711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ce711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ffe86ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (205 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintam_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintm_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintn_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn me
# | ...
# `---data was truncated (10240/17932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f77401feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f77401ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f77402062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd13133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd1318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd13133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd1311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f773fb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f773fb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f773f9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f773c49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f773c49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd1311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd1311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd1311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f773c49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (206 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f19ff01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f19fefee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f19ff0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cdad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cdad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cdad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cdad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f19fe97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f19fe97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f19fe7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f19fb2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f19fb2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0cdad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cdad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cdad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f19fb2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (207 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056303c1d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056303c1d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056303c1d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04e3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04e3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04e3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04e3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056303c16bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056303c16ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056303c1508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056303bdffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056303bdffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04e3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04e3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04e3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056303bdffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (208 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_rsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %splat.splat = shufflevector <vscale x 16 x i8> %splat.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %shl = shl <vscale x 16 x i8> %0, %splat.splat
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_lsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %0, i64 0
# |   %splat.splat
# | ...
# `---data was truncated (10240/32491) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000557e5fd01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e5fcfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e5fd0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1579249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15792a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1579249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1579231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e5fc97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e5fc97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e5fc7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e5f92be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e5f92bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1579232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15792330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15792330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e5f92ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (209 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056322aa39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056322aa36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056322aa3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4c4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4c40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4c4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4c4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056322a9cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056322a9cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056322a9b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056322a663e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056322a663b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4c4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4c40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4c40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056322a663a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (210 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svzip_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svzip_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svzip_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557351514eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557351511e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055735151562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2612249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26122a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2612249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2612231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573514aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573514aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055735148f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055735113ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055735113eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2612232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26122330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26122330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055735113ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (211 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6ce6beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6ce6bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6ce6bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7777049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77770a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7777049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7777031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6ce654bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6ce654a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6ce6398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6ce2e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6ce2e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7777032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77770330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77770330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6ce2e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (212 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 {
# | entry:
# |   ret target("aarch64.svcount") zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ac78498eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac78495e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac7849962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc26d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc26d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc26d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc26d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac7842ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac7842ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac784138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac780c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac780c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc26d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc26d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc26d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac780c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (213 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c76d732eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c76d72fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c76d73362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f804261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80426725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f804261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8042603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c76d6c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c76d6c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c76d6ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c76d35ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c76d35cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8042604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80426050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80426050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c76d35ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (214 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056408e751eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056408e74ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056408e75262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e31849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e318a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e31849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e31831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056408e6e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056408e6e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056408e6cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056408e37be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056408e37bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e31832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e318330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e318330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056408e37ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (215 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_u32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056461321ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564613219e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056461321d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ce0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ce0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ce0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ce0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646131b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646131b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646131978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564612e46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564612e46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ce0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ce0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ce0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564612e46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (216 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splat
# | ...
# `---data was truncated (10240/24132) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056227a463eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056227a460e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056227a46462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff137649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff137649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff137631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056227a3f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056227a3f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056227a3de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056227a08de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056227a08db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff137632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1376330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056227a08da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (217 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmsb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563c5368eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c5368be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c5368f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3164d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3164d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3164d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3164d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c53624bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c53624a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c536098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c532b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c532b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3164d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3164d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3164d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c532b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (218 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 2, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 3, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560ee23d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ee23cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ee23d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8257649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82576a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8257649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8257631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ee2367bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ee2367a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ee234c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ee1ffbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ee1ffbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8257632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82576330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82576330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ee1ffba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (219 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d162d47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d162d44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d162d4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19e621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19e62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19e621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19e6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d162cddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d162cdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d162cc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d162971e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d162971b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19e6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19e62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19e62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d162971a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (220 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate2_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %1, 1
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcreate2_f32(<vscale x 4 x float> %x0, <vscale x 4 x float> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x float>, align 16
# |   %x1.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x float> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %1, 1
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svcreate2_f64(<vscale x 2 x double> %x0, <vscale x 2 x double> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x double>, align 16
# |   %x1.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x double> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %1, 1
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_mf8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svcreate2_bf16(<vscale x 8 x bfloat> %x0, <vscale x 8 x bfloat> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %x1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x bfloat> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/10734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563b0a3e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b0a3dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b0a3e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fe4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fe438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fe4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fe431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b0a376bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b0a376a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b0a35b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b0a00ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b0a00ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fe431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fe431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fe431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b0a00aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (221 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c7c0b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c7c0ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c7c0b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4705e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4705ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4705e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4705e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c7c046bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c7c046a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c7c02b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c7bcdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c7bcdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4705e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4705e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4705e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c7bcdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (222 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x2(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svclamp_single_s16_x2(<vscale x 8 x i16> %op1.coerce0, <vscale x 8 x i16> %op1.coerce1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %op1.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svclamp_single_s32_x2(<vscale x 4 x i32> %op1.coerce0, <vscale x 4 x i32> %op1.coerce1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %op1.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svclamp_single_s64_x2(<vscale x 2 x i64> %op1.coerce0, <vscale x 2 x i64> %op1.coerce1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %op1.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x4(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op1.coerce2, <vscale x 16 x i8> %op1.coerce3, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %op1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/62547) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e28b472eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e28b46fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e28b47362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba6901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba690725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba6901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba69003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e28b408bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e28b408a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e28b3ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e28b09ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e28b09cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba69004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba690050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba690050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e28b09ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (223 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %5, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %5, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %5, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %5, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# | ...
# `---data was truncated (10240/34217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562a4962aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a49627e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a4962b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0116b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0116b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0116b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0116b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a495c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a495c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a495a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a49254e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a49254b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0116b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0116b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0116b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a49254a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (224 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005565dd02eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565dd02be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565dd02f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa474c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa474ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa474c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa474c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565dcfc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565dcfc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565dcfa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565dcc58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565dcc58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa474c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa474c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa474c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565dcc58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (225 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f311207eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f311204e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f31120862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f424e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f424e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f424e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f424e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f31119dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f31119da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3111828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f310e31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f310e31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f424e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f424e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f424e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f310e31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (226 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 13, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 29, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562d25592eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d2558fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d2559362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e77133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e7718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e77133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e7711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d25528bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d25528a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d2550d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d251bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d251bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e7711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e7711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e7711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d251bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (227 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> zeroi
# | ...
# `---data was truncated (10240/32102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d8136f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8136f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8136f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65a7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65a738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65a7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65a731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d81368abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d81368aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d81366f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d81331ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d81331eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65a731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65a731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65a731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d81331ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (228 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558df2746eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558df2743e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558df274762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aee51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558df26dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558df26dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558df26c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558df2370e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558df2370b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4aee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aee51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558df2370a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (229 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.ad
# | ...
# `---data was truncated (10240/17434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005628d3602eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628d35ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628d360362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d24c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d24ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d24c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d24c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628d3598bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628d3598a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628d357d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628d322ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628d322cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d24c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d24c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d24c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628d322ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (230 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrts_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrts_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrts_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055a656fbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a656fbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a656fc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59fd21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59fd2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59fd21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59fd203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a656f55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a656f55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a656f3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a656be9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a656be9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59fd204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59fd2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59fd2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a656be9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (231 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557909616eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557909613e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055790961762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7608133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f760818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7608133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f760811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579095acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579095aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579095918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557909240e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557909240b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f760811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f760811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f760811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557909240a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (232 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x ha
# | ...
# `---data was truncated (10240/18235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056041d155eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056041d152e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056041d15662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21a5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21a5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21a5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21a5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056041d0ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056041d0eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056041d0d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056041cd7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056041cd7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21a5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21a5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21a5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056041cd7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (233 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 3)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 7)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f61287deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f61287ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f61287e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff906c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff906ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff906c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff906c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f612813bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f612813a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6127f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6124a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6124a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff906c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff906c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff906c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6124a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (234 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559b91625eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b91622e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b9162662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24e5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24e5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24e5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24e5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b915bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b915bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b915a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b9124fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b9124fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24e5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24e5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24e5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b9124fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (235 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dc310a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc3109de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc310a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7334449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73344a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7334449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7334431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc31036bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc31036a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc3101b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc30ccae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc30ccab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7334432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73344330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73344330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc30ccaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (236 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1ro_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1ro_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1ro_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1ro_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055efbf2deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efbf2dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efbf2df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8039b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8039b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8039b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8039b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efbf274bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efbf274a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efbf2598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efbef08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efbef08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8039b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8039b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8039b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efbef08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (237 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a07cd9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a07cd97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a07cd9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2116333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f211638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2116333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f211631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a07cd30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a07cd30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a07cd158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a07c9c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a07c9c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f211631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f211631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f211631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a07c9c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/orv.c (238 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000560cb05c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cb05c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cb05c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d3db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d3db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d3db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d3db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cb055ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cb055ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cb05438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cb01f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cb01f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d3db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d3db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d3db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cb01f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (239 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 {
# | entry:
# |   %cnt.addr = alloca target("aarch64.svcount"), align 2
# |   store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2
# |   %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1> %0)
# |   ret target("aarch64.svcount") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ebc3d50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebc3d4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebc3d5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcae8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcae82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcae8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcae8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebc3ce6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebc3ce6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebc3ccb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebc397ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebc397ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcae8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcae82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcae82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebc397aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (240 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | 
# | ...
# `---data was truncated (10240/178306) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560892442eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056089243fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056089244362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdedbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdedbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdedbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdedbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608923d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608923d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608923bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056089206ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056089206cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdedbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdedbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdedbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056089206ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (241 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562ba51edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ba51eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ba51ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d3a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d3a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d3a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d3a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ba5183bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ba5183a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ba51688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ba4e17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ba4e17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d3a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d3a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d3a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ba4e17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (242 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmad_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555f4f411eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f4f40ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f4f41262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8dded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8dded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8dded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8dded1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f4f3a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f4f3a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f4f38c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f4f03be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f4f03bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8dded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8dded1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8dded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f4f03ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (243 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_s8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_s16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_s32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_s64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_u8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_u16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_u32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_u64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdupq_lane_f16(<vscale x 8 x half> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdupq_lane_f32(<vscale x 4 x float> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdupq_lane_f64(<vscale x 2 x double> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 {
# | entry:
# |   %x0.addr = alloca i8, align 1
# |   %x1.addr = alloca i8, align 1
# |   %x2.addr = alloca i8, align 1
# |   %x3.addr = alloca i8, align 1
# |   %x4.addr = alloca i8, align 1
# |   %x5.addr = alloca i8, align 1
# |   %x6.addr = alloca i8, align 1
# |   %x7.addr = alloca i8, align 1
# |   %x8.addr = alloca i8, align 1
# |   %x9.addr = alloca i8, align 1
# |   %x10.addr = alloca i8, align 1
# |   %x11.addr = alloca i8, align 1
# |   %x12.addr = alloca i8, align 1
# |   %x13.addr = alloca i8, align 1
# |   %x14.addr = alloca i8, align 1
# |   %x15.addr = alloca i8, align 1
# |   store i8 %x0, ptr %x0.addr, align 1
# |   store i8 %x1, ptr %x1.addr, align 1
# |   store i8 %x2, ptr %x2.addr, align 1
# |   store i8 %x3, ptr %x3.addr, align 1
# |   store i8 %x4, ptr %x4.addr, align 1
# |   store i8 %x5, ptr %x5.addr, align 1
# |   store i8 %x6, ptr %x6.addr, align 1
# |   store i8 %x7, ptr %x7.addr, align 1
# |   store i8 %x8, ptr %x8.addr, align 1
# |   store i8 %x9, ptr %x9.addr, align 1
# |   store i8 %x10, ptr %x10.addr, align 1
# |   store i8 %x11, ptr %x11.addr, align 1
# |   store i8 %x12, ptr %x12.addr, align 1
# |   store i8 %x13, ptr %x13.addr, align 1
# |   store i8 %x14, ptr %x14.addr, align 1
# |   store i8 %x15, ptr %x15.addr, align 1
# |   %0 = load i8, ptr %x0.addr, align 1
# |   %1 = load i8, ptr %x1.addr, align 1
# |   %2 = load i8, ptr %x2.addr, align 1
# |   %3 = load i8, ptr %x3.addr, align 1
# |   %4 = load i8, ptr %x4.addr, align 1
# |   %5 = load i8, ptr %x5.addr, align 1
# |   %6 = load i8, ptr %x6.addr, align 1
# |   %7 = load i8, ptr %x7.addr, align 1
# |   %8 = load i8, ptr %x8.addr, align 1
# |   %9 = load i8, ptr %x9.addr, align 1
# |   %10 = load i8, ptr %x10.addr, align 1
# |   %11 = load i8, ptr %x11.addr, align 1
# |   %12 = load i8, ptr %x12.addr, align 1
# |   %13 = load i8, ptr
# | ...
# `---data was truncated (10240/42600) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056311f2d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056311f2d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056311f2d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61d8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61d838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61d8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61d831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056311f26dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056311f26da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056311f2528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056311ef01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056311ef01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61d831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61d831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61d831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056311ef01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (244 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local half @subscript_float16(<vscale x 8 x half> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 4 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %a.coerce, i64 0)
# |   store <16 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 2 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> %a.coerce, i64 0)
# |   store <8 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055bc258ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc258dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc258de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2374933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f237498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2374933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f237491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc25873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc25873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc258588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc25507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc25507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f237491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f237491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f237491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc25507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (245 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b79a88aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b79a887e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b79a88b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6e6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6e618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6e6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6e611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b79a820bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b79a820a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b79a8058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b79a4b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b79a4b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6e611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6e611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6e611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b79a4b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (246 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055daeafd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055daeafcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055daeafd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f336dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f336dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f336dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f336dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daeaf67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055daeaf67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055daeaf4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055daeabfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055daeabfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f336dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f336dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f336dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daeabfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/perm.c (247 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, 
# | ...
# `---data was truncated (10240/231562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055c23ae89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c23ae86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c23ae8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b03705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b0375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b03705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b036ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c23ae1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c23ae1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c23ae048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c23aab3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c23aab3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b036eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b036ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b036ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c23aab3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (248 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsplice_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/14328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561e119b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e119b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e119ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2b4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2b418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2b4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2b411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e1194fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e1194fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e119348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e115e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e115e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2b411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2b411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2b411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e115e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (249 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmmla_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559f302f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f302eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f302f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f181ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f181ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f181ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f181ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f30287bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f30287a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f3026c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f2ff1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f2ff1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f181ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f181ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f181ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f2ff1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (250 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 0)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 90)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_2(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 180)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_3(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 270)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 0)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 90)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale
# | ...
# `---data was truncated (10240/21122) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055982ee5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055982ee58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055982ee5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc07b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc07b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc07b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc07b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055982edf1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055982edf1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055982edd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055982ea85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055982ea85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc07b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc07b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc07b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055982ea85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (251 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @subscript_float16(<vscale x 8 x half> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @subscript_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @subscript_float64(<vscale x 2 x double> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %1, float 1.000000e+00, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_read_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecext = extractelement <vscale x 4 x float> %1, i64 %0
# |   %add = fadd float %vecext, 1.000000e+00
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %2, float %add, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000562d7c377eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d7c374e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d7c37862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f480c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f480c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f480c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f480c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d7c30dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d7c30da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d7c2f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d7bfa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d7bfa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f480c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f480c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f480c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d7bfa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (252 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate3_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1, <vscale x 8 x half> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   %x2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x half> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vsc
# | ...
# `---data was truncated (10240/15704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d7cfad1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7cfacee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7cfad262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57af533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57af58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57af533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57af51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7cfa67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7cfa67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7cfa4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7cf6fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7cf6fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57af51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57af51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57af51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7cf6fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (253 of 27910)
******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> <i32 3, i32 2, i32 8, i32 11, i32 7, i32 6, i32 12, i32 15>
# |   ret <8 x float> %shufp
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> <i32 1, i32 0>
# |   ret <2 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 1, i32 2, i32 3>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <4 x double> %b, ptr %b.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <4 x double>, ptr %b.addr, align 32
# |   %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
# |   ret <4 x double> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
# |   ret <8 x float> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <4 x i64>, align 32
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <4 x i64> %b, ptr %b.addr, align 32
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <4 x i64>, ptr %b.addr, align 32
# |   %3 = bitcast <4 x i64> %2 to <8 x i32>
# |   %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
# |   %4 = bitcast <8 x i32> %vperm to <4 x i64>
# |   ret <4 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3
# |   store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__d.i = alloca double, align 8
# |   %.compoundliteral.i = alloca <4 x double>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load double, ptr %1, align 1
# |   store double %2, ptr %__d.i, align 8
# |   %3 = load double, ptr %__d.i, align 8
# |   %vecinit.i = insertelement <4 x double> poison, double %3, i32 0
# |   %4 = load double, ptr %__d.i, align 8
# |   %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1
# |   %5 = load double, ptr %__d.i, align 8
# |   %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2
# |   %6 = load double, ptr %__d.i, align 8
# |   %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3
# |   store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32
# |   %7 = load <4 x double>, ptr %.compoundliteral.i, align 32
# |   ret <4 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <8 x float>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <8 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3
# |   %7 = load float, ptr %__f.i, align 4
# |   %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4
# |   %8 = load float, ptr %__f.i, align 4
# |   %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5
# |   %9 = load float, ptr %__f.i, align 4
# |   %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6
# |   %10 = load float, ptr %__f.i, align 4
# |   %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7
# |   store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32
# |   %11 = load <8 x float>, ptr %.compoundliteral.i, align 32
# |   ret <8 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <4 x float>, align 16
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
# |   ret <8 x float> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <2 x double>, align 16
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
# |   ret <4 x double> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <2 x i64>, ptr
# | ...
# `---data was truncated (10240/21933) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618a2cb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618a2cafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618a2cb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb1081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb108725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb1081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb10803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618a2c48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618a2c48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618a2c2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618a28dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618a28dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb10804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb108050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb108050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618a28dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (254 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559a44df5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a44df2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a44df662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8793c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8793ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8793c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8793c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a44d8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a44d8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a44d708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a44a1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a44a1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8793c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8793c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8793c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a44a1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @foo() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @bar() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @baz(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @quux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %call = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %call
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e810dcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e810dcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e810dd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff723133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff72318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff723133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff72311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e810d65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e810d65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e810d4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8109f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8109f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff72311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff72311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff72311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8109f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (256 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i)
# |   store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i)
# |   store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i)
# |   store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i)
# |   store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i)
# |   store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i)
# |   store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i)
# |   store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i)
# |   store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vrndns_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vrndn.i = call float @llvm.roundeven.f32(float %1)
# |   store float %vrndn.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i)
# |   store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndm.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i)
# |   store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i)
# |   store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a
# | ...
# `---data was truncated (10240/29785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560de760beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560de7608e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560de760c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f629b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f629b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f629b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f629b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560de75a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560de75a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560de75868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560de7235e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560de7235b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f629b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f629b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f629b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560de7235a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (257 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svadda_f16(<vscale x 16 x i1> %pg, half noundef %initial, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca half, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store half %initial, ptr %initial.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load half, ptr %initial.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1> %3, half %1, <vscale x 8 x half> %2)
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1>, half, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svadda_f32(<vscale x 16 x i1> %pg, float noundef %initial, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca float, align 4
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store float %initial, ptr %initial.addr, align 4
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load float, ptr %initial.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1> %3, float %1, <vscale x 4 x float> %2)
# |   ret float %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1>, float, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svadda_f64(<vscale x 16 x i1> %pg, double noundef %initial, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca double, align 8
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store double %initial, ptr %initial.addr, align 8
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load double, ptr %initial.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %3, double %1, <vscale x 2 x double> %2)
# |   ret double %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563a8773eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a8773be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a8773f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7749849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77498a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7749849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7749831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a876d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a876d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a876b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a87368e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a87368b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7749832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77498330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77498330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a87368a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (258 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_cvtl_f32_x2(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half> %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558f8a316eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f8a313e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f8a31762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7d1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7d198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7d1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7d191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f8a2acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f8a2aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f8a2918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f89f40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f89f40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7d191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7d191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7d191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f89f40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (259 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %a.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %b.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x bfloat> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564682300eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646822fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056468230162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd46ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd46caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd46ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd46ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564682296bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564682296a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056468227b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564681f2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564681f2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd46ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd46ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd46ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564681f2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (260 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svqdmulh_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svqdmulh_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x4(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zdn.coerce2, <vscale x 16 x i8> %zdn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zdn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x4(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zdn.coerce2, <vscale x 8
# | ...
# `---data was truncated (10240/47111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557a2206eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a2206be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a2206f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb060133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb06018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb060133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb06011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a22004bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a22004a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a21fe98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a21c98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a21c98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb06011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb06011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb06011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a21c98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (261 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f35ebd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f35ebd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f35ebd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb10105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb1015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb10105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb100ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f35eb6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f35eb6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f35eb538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f35e802e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f35e802b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb100eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb100ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb100ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f35e802a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (262 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626629a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626629a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626629a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e24049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e240a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e24049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e24031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056266293abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056266293aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056266291f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626625cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626625ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e24032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e240330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e240330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626625cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (263 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld3_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld3_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svld3_f64(<vscale x
# | ...
# `---data was truncated (10240/26187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a8a5c68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8a5c65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8a5c6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e9f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e9f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e9f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e9f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8a5bfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8a5bfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8a5be38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8a5892e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8a5892b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e9f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e9f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e9f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8a5892a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (264 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrev_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrev_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrev_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b8(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b16(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b32(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b64(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svrev_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fc40c2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc40c29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc40c2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7be333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7be38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7be333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7be31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc40bc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc40bc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc40ba78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc40856e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc40856b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7be31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7be31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7be31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc40856a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (265 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6de350eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6de34de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6de35162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79f7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79f7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79f7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79f7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6de2e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6de2e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6de2cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6ddf7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6ddf7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79f7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79f7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79f7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6ddf7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (266 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1>, ptr, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = getelementptr <vscale x 16 x i8>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_s32offset(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/16554) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b12721ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b127219e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b12721d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dca333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dca38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dca333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dca31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1271b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1271b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1271978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b126e46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b126e46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9dca31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dca31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dca31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b126e46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (267 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld4_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld4_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.fr
# | ...
# `---data was truncated (10240/27970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055767434ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557674349e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055767434d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576742e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576742e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576742c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557673f76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557673f76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facc0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557673f76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (268 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005648f5ac7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648f5ac4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648f5ac862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd90d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd90d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd90d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd90d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648f5a5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648f5a5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648f5a428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648f56f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648f56f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd90d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd90d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd90d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648f56f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (269 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_s32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_u32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svadd_vector_single2_s64(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x
# | ...
# `---data was truncated (10240/34761) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d68fffceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d68fff9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d68fffd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc52725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc5203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d68ff92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d68ff92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d68ff778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d68fc26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d68fc26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facc5204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc52050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc52050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d68fc26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (270 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055913447feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055913447ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055913448062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f329cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f329cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f329cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f329cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559134415bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559134415a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591343fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591340a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591340a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f329cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f329cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f329cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591340a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (271 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlasta_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlasta_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlasta_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cbd8e8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbd8e88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbd8e8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe415f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe415f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe415f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe415f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbd8e21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbd8e21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbd8e068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbd8ab5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbd8ab5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe415f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe415f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe415f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbd8ab5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (272 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0
# | ...
# `---data was truncated (10240/39820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056353b45eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056353b45be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056353b45f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fe1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fe155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fe1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fe14ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056353b3f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056353b3f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056353b3d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056353b088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056353b088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fe14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fe14ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fe14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056353b088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (273 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555b6a277eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b6a274e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b6a27862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7371849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73718a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7371849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7371831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b6a20dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b6a20da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b6a1f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b69ea1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b69ea1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7371832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73718330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73718330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b69ea1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (274 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %4, 0
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %4, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale
# | ...
# `---data was truncated (10240/25462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005648e0683eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648e0680e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648e068462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb416b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb416b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb416b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb416b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648e0619bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648e0619a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648e05fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648e02ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648e02adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb416b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb416b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb416b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648e02ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (275 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcompact_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcompact_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005614b4cd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614b4cd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614b4cd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f033d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f033d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f033d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f033d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614b4c6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614b4c6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614b4c528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614b4901e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614b4901b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f033d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f033d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f033d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614b4901a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (276 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16(<vscale x 8 x half> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d39480feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d39480ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d39481062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc9b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc9b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc9b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc9b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3947a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3947a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d39478a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d394439e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d394439b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc9b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc9b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc9b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d394439a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (277 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005585b274eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585b274be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585b274f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf3df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf3df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf3df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf3df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585b26e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585b26e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585b26c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585b2378e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585b2378b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf3df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf3df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf3df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585b2378a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (278 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005561a55f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561a55f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561a55f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f894cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f894cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f894cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f894cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561a558abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561a558aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561a556f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561a521ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561a521eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f894cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f894cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f894cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561a521ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (279 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 8 x half> %0, %1
# |   ret <vscale x 8 x half> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @add_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 4 x float> %0, %1
# |   ret <vscale x 4 x float> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @add_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 2 x double> %0, %1
# |   ret <vscale x 2 x double> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %add = add <vscale x 4 x i32> %1, %0
# |   store <vscale x 4 x i32> %add, ptr %a.addr, align 16
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_inplace_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %add = add <vscale x 2 x i64> %1, %0
# |   store <vscale x 2 x i64> %add, ptr %a.addr, align 16
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <
# | ...
# `---data was truncated (10240/107144) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055e0949f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0949ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0949f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f0f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f0f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f0f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f0f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e094986bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e094986a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e09496b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e09461ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e09461ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f0f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f0f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f0f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e09461aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (280 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005617e736feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617e736ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617e737062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faad6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faad678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faad6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faad671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617e7305bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617e7305a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617e72ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617e6f99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617e6f99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faad671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faad671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faad671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617e6f99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (281 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsel_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/15264) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b64d8cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b64d8cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b64d8ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1801933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f180198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1801933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f180191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b64d863bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b64d863a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b64d8488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b64d4f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b64d4f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f180191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f180191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f180191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b64d4f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (282 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de473f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de473eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de473f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f03e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f03ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f03e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f03e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de47387bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de47387a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de4736c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de4701be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de4701bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f03e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f03e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f03e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de4701ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (283 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_s8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_s16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_s32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_s64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_u8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_u16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_u32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_u64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbl_f16(<vscale x 8 x half> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbl_f32(<vscale x 4 x float> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtbl_f64(<vscale x 2 x double> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtbl_bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptra
# | ...
# `---data was truncated (10240/10361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b5bdaa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5bda9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5bdaa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4720b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4720b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4720b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4720b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5bda37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5bda37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5bda1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5bd6cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5bd6cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4720b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4720b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4720b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5bd6cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (284 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005583e6d42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583e6d3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583e6d4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f56333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f5638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f56333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f5631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583e6cd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583e6cd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583e6cbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583e696ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583e696cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f5631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f5631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f5631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583e696ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (285 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055606ff42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055606ff3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055606ff4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febc5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febc578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febc5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febc571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055606fed8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055606fed8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055606febd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055606fb6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055606fb6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febc571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febc571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febc571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055606fb6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (286 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b7ab9bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7ab9b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7ab9bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5c7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5c758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5c7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5c751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7ab951bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7ab951a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7ab9368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7ab5e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7ab5e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5c751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5c751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5c751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7ab5e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (287 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000562abdd3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562abdd38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562abdd3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91a181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91a18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91a181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91a1803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562abdcd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562abdcd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562abdcb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562abd965e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562abd965b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91a1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91a18050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91a18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562abd965a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (288 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 3
# |   %14 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 3
# |   call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, <vscale x 8 x i16> %10, <vscale x 8 x i16> %11, <vscale x 8 x i16> %12, <vscale x 8 x i16> %13, <vscale x 8 x i16> %15, <vscale x 8 x i16> %16, <vscale x 8 x i16> %17, <vscale x 8 x i16> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, <vscale x 16 x i8> %zm.coerce2, <vscale x 16 x i8> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align
# | ...
# `---data was truncated (10240/127452) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055850074aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558500747e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055850074b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5ae649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5ae6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5ae649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5ae631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585006e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585006e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585006c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558500374e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558500374b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5ae632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5ae6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5ae6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558500374a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (289 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559324a40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559324a3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559324a4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29ca905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29ca95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29ca905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29ca8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593249d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593249d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593249bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055932466ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055932466ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29ca8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29ca8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29ca8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055932466aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (290 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmmla_f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 4 x float>, align 16
# |   %z.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 4 x float> %y, ptr %y.addr, align 16
# |   store <vscale x 4 x float> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %y.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562ffea2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ffea28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ffea2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29f6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29f6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29f6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29f6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ffe9c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ffe9c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ffe9a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ffe655e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ffe655b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29f6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29f6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29f6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ffe655a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (291 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055594a023eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055594a020e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055594a02462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f0d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f0d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f0d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f0d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555949fb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555949fb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555949f9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555949c4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555949c4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f0d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f0d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f0d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555949c4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/addv.c (292 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svaddv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svaddv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svaddv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | a
# | ...
# `---data was truncated (10240/10826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x0000557b4c519eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b4c516e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b4c51a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ab221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ab22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ab221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ab2203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b4c4afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b4c4afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b4c4948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b4c143e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b4c143b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ab2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ab22050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ab22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b4c143a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (293 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561c49b8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c49b88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c49b8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66da933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66da98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66da933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66da91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c49b21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c49b21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c49b068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c497b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c497b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66da91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66da91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66da91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c497b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (294 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> }
# | ...
# `---data was truncated (10240/45653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557a5d097eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a5d094e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a5d09862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c92c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c92ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c92c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c92c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a5d02dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a5d02da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a5d0128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a5ccc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a5ccc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c92c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c92c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c92c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a5ccc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (295 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a656365eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a656362e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a65636662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9592f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9592f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9592f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9592f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6562fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6562fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6562e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a655f8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a655f8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9592f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9592f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9592f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a655f8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (296 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrun_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056094fd89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056094fd86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056094fd8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ce7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ce7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ce7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ce7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056094fd1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056094fd1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056094fd048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056094f9b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056094f9b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ce7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ce7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ce7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056094f9b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (297 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561a772bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a772b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a772bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f195ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f195ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f195ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f195ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a77252bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a77252a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a772378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a76ee6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a76ee6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f195ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f195ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f195ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a76ee6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (298 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 270)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.ad
# | ...
# `---data was truncated (10240/12234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d78ebbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d78ebbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d78ebc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e58249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e58249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e58231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d78eb55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d78eb55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d78eb3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d78e7e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d78e7e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e58232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e582330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d78e7e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (299 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055d38457ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d384579e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d38457d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffab2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffab22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffab2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffab2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d384512bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d384512a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3844f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3841a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3841a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffab2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffab22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffab22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3841a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (300 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtssel_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtssel_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtssel_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fbd2fb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbd2fade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbd2fb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5a881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5a88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5a881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5a8803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbd2f46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbd2f46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbd2f2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbd2bdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbd2bdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5a8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5a88050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5a88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbd2bdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (301 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpe_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpe_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpe_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005556c0c7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556c0c7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556c0c8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8b3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8b3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8b3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8b3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556c0c15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556c0c15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556c0bfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556c08a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556c08a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8b3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8b3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8b3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556c08a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (302 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_ra
# | ...
# `---data was truncated (10240/35066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000056041dff1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056041dfeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056041dff262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0e0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0e058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0e0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0e051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056041df87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056041df87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056041df6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056041dc1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056041dc1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0e051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0e051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0e051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056041dc1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (303 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056035ca5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056035ca59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056035ca5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6ee933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6ee98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6ee933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6ee91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056035c9f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056035c9f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056035c9d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056035c686e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056035c686b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6ee91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6ee91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6ee91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056035c686a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (304 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563d805eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d805ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d805ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbae461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbae46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbae461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbae4603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d80584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d80584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d805698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d80218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d80218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbae4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbae46050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbae46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d80218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (305 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a387a39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a387a36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a387a3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc85da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc85daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc85da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc85da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3879cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3879cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3879b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a387663e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a387663b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc85da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc85da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc85da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a387663a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (306 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svsel_s16_x2(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   %11 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale 
# | ...
# `---data was truncated (10240/33971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005603bba57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603bba54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603bba5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f461881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46188725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f461881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4618803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603bb9edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603bb9eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603bb9d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603bb681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603bb681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4618804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46188050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46188050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603bb681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (307 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <
# | ...
# `---data was truncated (10240/50499) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564163d83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564163d80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564163d8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb25a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb25a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb25a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb25a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564163d19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564163d19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564163cfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641639ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641639adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb25a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb25a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb25a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641639ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (308 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32f16(<vscale x 4 x float> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005623258c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623258c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623258c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff37ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff37caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff37ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff37ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562325859bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562325859a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056232583e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623254ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623254edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff37ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff37ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff37ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623254eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (309 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000055afc14dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afc14dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afc14e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb20b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb20b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb20b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb20b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afc1475bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afc1475a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afc145a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afc1109e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afc1109b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb20b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb20b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb20b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afc1109a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (310 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = c
# | ...
# `---data was truncated (10240/207083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c053ee2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c053edfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c053ee362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3440333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f344038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3440333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f344031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c053e78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c053e78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c053e5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c053b0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c053b0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f344031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f344031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f344031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c053b0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (311 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559906029eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559906026e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055990602a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f668f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f668f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f668f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f668f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559905fbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559905fbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559905fa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559905c53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559905c53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f668f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f668f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f668f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559905c53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (312 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 2
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 2
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue 
# | ...
# `---data was truncated (10240/21007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056310b4ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056310b4e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056310b4ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6862933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f686298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6862933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f686291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056310b481bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056310b481a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056310b4668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056310b115e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056310b115b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f686291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f686291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f686291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056310b115a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (313 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfirst_b(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556b2c937eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b2c934e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b2c93862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87f1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87f12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87f1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87f1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b2c8cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b2c8cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b2c8b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b2c561e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b2c561b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87f1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87f12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87f12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b2c561a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (314 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i64>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a1716f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1716eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1716f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5919d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5919d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5919d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5919d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a171687bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a171687a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a17166c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a17131be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a17131bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5919d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5919d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5919d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a17131ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (315 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eaf130eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaf130be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaf130f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee2cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee2cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee2cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaf12a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaf12a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaf12898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaf0f38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaf0f38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee2cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee2cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee2cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaf0f38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (316 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fff5ceeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fff5cebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fff5cef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50cb905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50cb95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50cb905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50cb8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fff5c84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fff5c84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fff5c698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fff5918e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fff5918b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50cb8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50cb8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50cb8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fff5918a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (317 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <
# | ...
# `---data was truncated (10240/50724) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bb6b10beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb6b108e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb6b10c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff07c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff07c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff07c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff07c8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb6b0a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb6b0a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb6b0868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb6ad35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb6ad35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff07c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff07c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff07c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb6ad35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (318 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a6ba0a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6ba09ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6ba0a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1eec333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1eec38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1eec333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1eec31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6ba037bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6ba037a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6ba01c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6b9ccbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6b9ccbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1eec31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1eec31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1eec31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6b9ccba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (319 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557f4356deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f4356ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f4356e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f676d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f676d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f676d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f676d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f43503bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f43503a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f434e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f43197e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f43197b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f676d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f676d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f676d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f43197a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (320 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005584f5947eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584f5944e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584f594862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44aaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44aaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44aaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44aaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584f58ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584f58dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584f58c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584f5571e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584f5571b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44aaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44aaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44aaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584f5571a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (321 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 
# | ...
# `---data was truncated (10240/13379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a730bb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a730bb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a730bb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5badaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bada31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a730b4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a730b4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a730b318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7307e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7307e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bada330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7307e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (322 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564767c45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564767c42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564767c4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f47933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f4798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f47933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f4791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564767bdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564767bdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564767bc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056476786fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056476786fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f4791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f4791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f4791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056476786fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (323 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562381ef1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562381eeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562381ef262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe305533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe30558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe305533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe30551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562381e87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562381e87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562381e6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562381b1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562381b1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe30551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe30551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe30551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562381b1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (324 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557868e90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557868e8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557868e9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9f0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9f04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9f0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9f0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557868e26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557868e26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557868e0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557868abae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557868abab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9f0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9f04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9f04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557868abaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (325 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x float
# | ...
# `---data was truncated (10240/338684) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2a99f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2a99f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2a99fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4173933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f417398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4173933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f417391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2a998fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2a998fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2a99748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2a9623e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2a9623b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f417391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f417391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f417391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2a9623a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (326 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557a02a05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a02a02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a02a0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9d7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9d72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9d7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9d7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a0299bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a0299ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a029808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a0262fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a0262fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9d7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9d72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9d72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a0262fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (327 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> noundef %a.coerce, <vscale x 8 x half> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x half>, align 16
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca <32 x half>, align 16
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %b.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store <32 x half> %b, ptr %b.addr, align 16
# |   %0 = load <32 x ha
# | ...
# `---data was truncated (10240/161192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005592f5c65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592f5c62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592f5c6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad3c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad3c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad3c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad3c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592f5bfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592f5bfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592f5be08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592f588fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592f588fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad3c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad3c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad3c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592f588fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (328 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562c4e61deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c4e61ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c4e61e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50e9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50e9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50e9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50e9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c4e5b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c4e5b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c4e5988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c4e247e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c4e247b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50e9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50e9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50e9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c4e247a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (329 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   call void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 2
# |   %9 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 0
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 1
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 2
# |   %9 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, <vscale x 2 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = al
# | ...
# `---data was truncated (10240/58378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055aa6cfa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa6cf9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa6cfa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea14649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea14649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea14631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa6cf36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa6cf36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa6cf1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa6cbcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa6cbcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea14632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea146330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa6cbcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (330 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate2_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %1, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055770e23eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055770e23be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055770e23f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1d4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1d4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1d4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1d4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055770e1d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055770e1d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055770e1b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055770de68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055770de68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa1d4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1d4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1d4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055770de68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (331 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 8)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 1)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 16)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 1)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z_1(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 32)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 1)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z_1(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 64)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i32 1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, 
# | ...
# `---data was truncated (10240/14353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005643c970ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643c9709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643c970d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc01e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc01e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc01e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc01e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643c96a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643c96a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643c96878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643c9336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643c9336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc01e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc01e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc01e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643c9336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (332 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564cb63cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cb63c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cb63cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00cc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00cc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00cc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00cc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cb6362bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cb6362a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cb63478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cb5ff6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cb5ff6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00cc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00cc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00cc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cb5ff6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (333 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %and = and <8 x i8> %2, %3
# |   store <8 x i8> %and, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %and = and <8 x i64> %0, %1
# |   store <8 x i64> %and, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x
# | ...
# `---data was truncated (10240/35910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000560f99cd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f99cd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f99cd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1addd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1addd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1addd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1addced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f99c69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f99c69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f99c4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f998fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f998fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1addceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1addcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1addcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f998fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (334 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vsca
# | ...
# `---data was truncated (10240/53696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eec1353eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eec1350e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eec135462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd401705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd40175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd401705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4016ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eec12e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eec12e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eec12ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eec0f7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eec0f7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4016eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4016ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4016ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eec0f7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (335 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056065e97feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056065e97ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056065e98062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f524a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f524a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f524a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f524a2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056065e915bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056065e915a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056065e8fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056065e5a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056065e5a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f524a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f524a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f524a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056065e5a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (336 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 
# | ...
# `---data was truncated (10240/172384) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b5ad07beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5ad078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5ad07c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc224333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc224333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5ad011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5ad011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5acff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5acca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5acca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc22431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5acca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (337 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_1(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 =
# | ...
# `---data was truncated (10240/15126) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560359181eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056035917ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056035918262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f5181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f518725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f5181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f51803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560359117bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560359117a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603590fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560358dabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560358dabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f51804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f518050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f518050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560358daba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (338 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055feaa80feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055feaa80ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055feaa81062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45fa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45fa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45fa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45fa403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feaa7a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055feaa7a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055feaa78a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055feaa439e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055feaa439b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45fa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45fa4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45fa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055feaa439a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (339 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 
# | ...
# `---data was truncated (10240/22063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557c67d9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c67d99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c67d9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2169e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2169ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2169e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2169e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c67d32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c67d32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c67d178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c679c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c679c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2169e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2169e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2169e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c679c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (340 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmin_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmin_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560bd0d98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bd0d95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bd0d9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c8a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c8a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c8a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c8a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bd0d2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bd0d2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bd0d138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bd09c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bd09c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c8a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c8a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c8a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bd09c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (341 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/11769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e54fac7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e54fac4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e54fac862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa83da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa83daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa83da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa83da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e54fa5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e54fa5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e54fa428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e54f6f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e54f6f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa83da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa83da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa83da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e54f6f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (342 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a707fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a707fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a707fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb4d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb4d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb4d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb4d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a707f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a707f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a707f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a707c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a707c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb4d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb4d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb4d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a707c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/recps.c (343 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecps_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecps_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecps_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000555bb7d19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bb7d16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bb7d1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac38733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac3878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac38733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac3871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bb7cafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bb7cafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bb7c948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bb7943e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bb7943b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac3871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac3871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac3871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bb7943a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (344 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmla_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b0b8fbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0b8fb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0b8fbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafb4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafb48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafb4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafb4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0b8f50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0b8f50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0b8f358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0b8be4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0b8be4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafb4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafb48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafb48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0b8be4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (345 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559f1afcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f1afc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f1afcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd79b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd79b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd79b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd79b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f1af61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f1af61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f1af468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f1abf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f1abf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd79b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd79b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd79b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f1abf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (346 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpa_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559f2d320eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f2d31de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f2d32162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe61da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe61daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe61da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe61da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f2d2b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f2d2b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f2d29b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f2cf4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f2cf4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe61da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe61da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe61da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f2cf4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (347 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005562f664eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562f664be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562f664f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbda7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbda7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbda7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbda7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562f65e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562f65e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562f65c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562f6278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562f6278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbda7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbda7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbda7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562f6278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (348 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559d9145eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d9145be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d9145f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08e6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08e618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08e6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08e611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d913f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d913f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d913d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d91088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d91088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08e611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08e611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08e611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d91088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc3b41beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc3b418e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc3b41c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03f7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03f718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03f7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03f711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc3b3b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc3b3b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc3b3968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc3b045e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc3b045b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03f711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03f711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03f711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc3b045a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (350 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfalse_b() #0 {
# | entry:
# |   ret <vscale x 16 x i1> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005607e95caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607e95c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607e95cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1790049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17900a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1790049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1790031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e9560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607e9560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607e95458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607e91f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607e91f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1790032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17900330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17900330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e91f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (351 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtsmul_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtsmul_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtsmul_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557444306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557444303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055744430762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff60d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff60d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff60d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff60d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055744429cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055744429ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574442818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557443f30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557443f30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff60d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff60d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff60d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557443f30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (352 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vsqaddb_u8() #0 {
# | entry:
# |   %__p0.addr.i = alloca i8, align 1
# |   %__p1.addr.i = alloca i8, align 1
# |   %__ret.i = alloca i8, align 1
# |   %ref.tmp.i = alloca i8, align 1
# |   store i8 1, ptr %__p0.addr.i, align 1
# |   store i8 -1, ptr %__p1.addr.i, align 1
# |   %0 = load i8, ptr %__p0.addr.i, align 1
# |   %1 = load i8, ptr %__p1.addr.i, align 1
# |   %2 = insertelement <8 x i8> poison, i8 %0, i64 0
# |   %3 = insertelement <8 x i8> poison, i8 %1, i64 0
# |   %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3)
# |   %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0
# |   store i8 %4, ptr %ref.tmp.i, align 1
# |   %5 = load i8, ptr %ref.tmp.i, align 1
# |   store i8 %5, ptr %__ret.i, align 1
# |   %6 = load i8, ptr %__ret.i, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vsqaddh_u16() #0 {
# | entry:
# |   %__p0.addr.i = alloca i16, align 2
# |   %__p1.addr.i = alloca i16, align 2
# |   %__ret.i = alloca i16, align 2
# |   %ref.tmp.i = alloca i16, align 2
# |   store i16 1, ptr %__p0.addr.i, align 2
# |   store i16 -1, ptr %__p1.addr.i, align 2
# |   %0 = load i16, ptr %__p0.addr.i, align 2
# |   %1 = load i16, ptr %__p1.addr.i, align 2
# |   %2 = insertelement <4 x i16> poison, i16 %0, i64 0
# |   %3 = insertelement <4 x i16> poison, i16 %1, i64 0
# |   %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3)
# |   %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0
# |   store i16 %4, ptr %ref.tmp.i, align 2
# |   %5 = load i16, ptr %ref.tmp.i, align 2
# |   store i16 %5, ptr %__ret.i, align 2
# |   %6 = load i16, ptr %__ret.i, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vsqadds_u32() #0 {
# | entry:
# |   %__p0.addr.i = alloca i32, align 4
# |   %__p1.addr.i = alloca i32, align 4
# |   %__ret.i = alloca i32, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   store i32 1, ptr %__p0.addr.i, align 4
# |   store i32 -1, ptr %__p1.addr.i, align 4
# |   %0 = load i32, ptr %__p0.addr.i, align 4
# |   %1 = load i32, ptr %__p1.addr.i, align 4
# |   %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1)
# |   store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4
# |   %2 = load i32, ptr %ref.tmp.i, align 4
# |   store i32 %2, ptr %__ret.i, align 4
# |   %3 = load i32, ptr %__ret.i, align 4
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vsqaddd_u64() #0 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i64, align 8
# |   %ref.tmp.i = alloca i64, align 8
# |   store i64 1, ptr %__p0.addr.i, align 8
# |   store i64 -1, ptr %__p1.addr.i, align 8
# |   %0 = load i64, ptr %__p0.addr.i, align 8
# |   %1 = load i64, ptr %__p1.addr.i, align 8
# |   %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1)
# |   store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8
# |   %2 = load i64, ptr %ref.tmp.i, align 8
# |   store i64 %2, ptr %__ret.i, align 8
# |   %3 = load i64, ptr %__ret.i, align 8
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# |  #0 0x0000560555bedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560555beae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560555bee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76af049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76af0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76af049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76af031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560555b83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560555b83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560555b688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560555817e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560555817b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76af032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76af0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76af0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560555817a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (353 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563082685eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563082682e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056308268662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5e1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5e1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5e1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5e1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056308261bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056308261ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630826008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630822afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630822afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5e1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5e1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5e1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630822afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (354 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a0eb623eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0eb620e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0eb62462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4829733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f482978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4829733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f482971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0eb5b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0eb5b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0eb59e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0eb24de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0eb24db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f482971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f482971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f482971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0eb24da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (355 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558511bdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558511bdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558511be062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e53333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e5338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e53333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e5331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558511b75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558511b75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558511b5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558511809e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558511809b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e5331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e5331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e5331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558511809a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (356 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i16>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/18010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b796bd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b796bd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b796bda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61f7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61f74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61f7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61f7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b796b6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b796b6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b796b548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b796803e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b796803b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61f7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61f74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61f74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b796803a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (357 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svldr_zt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svstr_zt(ptr noundef %base) #2 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) }
# | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005590d30b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590d30b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590d30b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f503eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f503eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f503eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f503eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590d304cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590d304ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590d30318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590d2ce0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590d2ce0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f503eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f503eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f503eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590d2ce0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (358 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2  -target-feature +sme  -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u8_1(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s8_2(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u16_3(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s16_1(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u32_2(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s32_3(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u64_0(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s64_1(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f16_2(<vscale x 8 x half> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_bf16_3(<vscale x 8 x bfloat> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f32_0(<vscale x 4 x float> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f64_1(<vscale x 2 x double> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, <vscale x 2 x double> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %
# | ...
# `---data was truncated (10240/13584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f651801eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6517fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f65180262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa90a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa90a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa90a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa90a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f651797bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f651797a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f65177c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f65142be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f65142bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa90a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa90a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa90a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f65142ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (359 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bbc31deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bbc31ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bbc31e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f215da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f215daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f215da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f215da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bbc2b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bbc2b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bbc2988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bbbf47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bbbf47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f215da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f215da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f215da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bbbf47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/orn.c (360 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svorn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000563419ed0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563419ecde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563419ed162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42d421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42d42725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42d421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42d4203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563419e66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563419e66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563419e4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563419afae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563419afab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42d4204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42d42050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42d42050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563419afaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (361 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv
# | ...
# `---data was truncated (10240/255166) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0e0fa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0e0fa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0e0faa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef20049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef200a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef20049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef20031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0e0f3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0e0f3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0e0f248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0e0bd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0e0bd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef20032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef200330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef200330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0e0bd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (362 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055813cad5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055813cad2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055813cad662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6aece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6aecea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6aece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6aece31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055813ca6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055813ca6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055813ca508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055813c6ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055813c6ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6aece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6aece330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6aece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055813c6ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (363 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056092889ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560928899e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056092889d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62dea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62deaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62dea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62dea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560928832bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560928832a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609288178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609284c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609284c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62dea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62dea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62dea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609284c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (364 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %shl = shl <16 x i32> %0, %1
# |   store <16 x i32> %shl, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 imma
# | ...
# `---data was truncated (10240/51475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005603ac5c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603ac5c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603ac5c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61cf305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61cf35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61cf305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61cf2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603ac55dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603ac55da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603ac5428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603ac1f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603ac1f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61cf2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61cf2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61cf2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603ac1f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (365 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac71c4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac71c4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac71c4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bad249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bad2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bad249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bad231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac71be4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac71be4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac71bc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac71878e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac71878b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bad232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bad2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bad2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac71878a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (366 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/69495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad454c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad454c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad454c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcf4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcf498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcf4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcf491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad4545bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad4545ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad454408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad450efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad450efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcf491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcf491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcf491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad450efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (367 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/72501) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561aa2de4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561aa2de1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561aa2de562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ca4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ca42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ca4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ca4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aa2d7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561aa2d7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561aa2d5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561aa2a0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561aa2a0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ca4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ca42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ca42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aa2a0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (368 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e79999eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e79996e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e7999a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b16905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b1695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b16905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b168ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e7992fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e7992fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e799148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e795c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e795c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b168eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b168ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b168ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e795c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (369 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vsc
# | ...
# `---data was truncated (10240/72568) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005592e5322eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592e531fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592e532362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5665b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5665b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5665b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5665b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592e52b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592e52b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592e529d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592e4f4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592e4f4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5665b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5665b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5665b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592e4f4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (370 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree n
# | ...
# `---data was truncated (10240/15237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563582f2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563582f2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563582f3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff450049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4500a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff450049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff450031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563582ec5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563582ec5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563582eaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563582b59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563582b59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff450032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4500330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4500330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563582b59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (371 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri
# | ...
# `---data was truncated (10240/20523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560611847eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560611844e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056061184862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e7861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e786725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e7861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e78603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606117ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606117dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606117c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560611471e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560611471b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e78604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e786050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e786050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560611471a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (372 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c62b438eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c62b435e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c62b43962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb49e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb49e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb49e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb49e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c62b3cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c62b3cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c62b3b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c62b062e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c62b062b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb49e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb49e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb49e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c62b062a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (373 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svclamp_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563d6a9daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d6a9d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d6a9db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c5d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c5d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c5d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c5d0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d6a970bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d6a970a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d6a9558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d6a604e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d6a604b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c5d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c5d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c5d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d6a604a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (374 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #4
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64
# | ...
# `---data was truncated (10240/21923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b431af2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b431aefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b431af362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77bca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77bcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77bca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77bca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b431a88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b431a88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b431a6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b43171ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b43171cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77bca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77bca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77bca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b43171ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (375 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 4)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 5)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 2)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 3)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svextq_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svextq_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 2)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svextq_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svextq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 6)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr,
# | ...
# `---data was truncated (10240/11061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056147c6dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056147c6d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056147c6dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd39de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd39dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd39de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd39de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056147c672bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056147c672a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056147c6578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056147c306e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056147c306b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd39de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd39de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd39de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056147c306a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (376 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556777ed2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556777ecfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556777ed362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8871449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88714a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8871449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8871431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556777e68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556777e68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556777e4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556777afce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556777afcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8871432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88714330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88714330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556777afca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-misc.c (377 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = icmp sge <8 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %2 to <8 x i8>
# |   store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %3 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %3, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %3 = icmp sge <4 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %3 = icmp sge <2 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x i64>
# |   %3 = icmp sge <1 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = icmp sge <16 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <16 x i1> %2 to <16 x i8>
# |   store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %3 = load <16 x i8>, ptr %ref.tmp.i, align 16
# |   store <16 x i8> %3, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x i16>
# |   %3 = icmp sge <8 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x i32>
# |   %3 = icmp sge <4 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x i64>
# |   %3 = icmp sge <2 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x float>
# |   %3 = fcmp oge <2 x float> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x double>
# |   %3 = fcmp oge <1 x double> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fcmp oge <4 x float> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %3 = fcmp oge <2 x double> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, ali
# | ...
# `---data was truncated (10240/217310) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a635502eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6354ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a63550362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcba4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcba438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcba4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcba431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a635498bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a635498a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a63547d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a63512ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a63512cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcba431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcba431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcba431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a63512ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (378 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsetffr() #0 {
# | entry:
# |   call void @llvm.aarch64.sve.setffr()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.setffr() #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005616f09b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616f09b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616f09ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1c8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1c8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1c8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1c8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616f094fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616f094fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616f09348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616f05e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616f05e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1c8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1c8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1c8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616f05e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (379 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpand_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svexpand_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpand_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, al
# | ...
# `---data was truncated (10240/12168) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a7f4924eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7f4921e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7f492562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f789e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f789e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f789e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f789e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7f48babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7f48baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7f489f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7f454ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7f454eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f789e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f789e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f789e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7f454ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (380 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_571 = alloca float, align 4
# |   %__s0_571 = alloca float, align 4
# |   %__s1_571 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_571, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_571, align 8
# |   %2 = load float, ptr %__s0_571, align 4
# |   %3 = load <2 x float>, ptr %__s1_571, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_571, align 4
# |   %8 = load float, ptr %__ret_571, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret_570 = alloca double, align 8
# |   %__s0_570 = alloca double, align 8
# |   %__s1_570 = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_570, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_570, align 8
# |   %2 = load double, ptr %__s0_570, align 8
# |   %3 = load <1 x double>, ptr %__s1_570, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %4, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_570, align 8
# |   %8 = load double, ptr %__ret_570, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_577 = alloca float, align 4
# |   %__s0_577 = alloca float, align 4
# |   %__s1_577 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_577, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_577, align 16
# |   %2 = load float, ptr %__s0_577, align 4
# |   %3 = load <4 x float>, ptr %__s1_577, align 16
# |   store <4 x float> %3, ptr %__s0, align 16
# |   %4 = load <4 x float>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <4 x float> %4, i32 3
# |   store float %vgetq_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_577, align 4
# |   %8 = load float, ptr %__ret_577, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret_575 = alloca double, align 8
# |   %__s0_575 = alloca double, align 8
# |   %__s1_575 = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_575, align 8
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1_575, align 16
# |   %2 = load double, ptr %__s0_575, align 8
# |   %3 = load <2 x double>, ptr %__s1_575, align 16
# |   store <2 x double> %3, ptr %__s0, align 16
# |   %4 = load <2 x double>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <2 x double> %4, i32 1
# |   store double %vgetq_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_575, align 8
# |   %8 = load double, ptr %__ret_575, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca double, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store double %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x double>, ptr %__p0.addr.i, align 8
# |   %3 = load double, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <1 x double> %2 to double
# |   %5 = fmul double %4, %3
# |   store double %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_626 = alloca float, align 4
# |   %__s0_626 = alloca float, align 4
# |   %__s1_626 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_626, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_626, align 8
# |   %2 = load float, ptr %__s0_626, align 4
# |   %3 = load <2 x float>, ptr %__s1_626, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   store float %2, ptr %__p0.addr.i, align 4
# |   store float %7, ptr %__p1.addr.i, align 4
# |   %8 = load float, ptr %__p0.addr.i, align 4
# |   %9 = load float, ptr %__p1.addr.i, align 4
# |   %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9)
# |   store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4
# |   %10 = load float, ptr %ref.tmp.i, align 4
# |   store float %10, ptr %__ret.i, align 4
# |   %11 = load float, ptr %__ret.i, align 4
# |   store float %11, ptr %__ret_626, align 4
# |   %12 = load float, ptr %__ret_626, align 4
# |   store float %12, ptr %tmp1, align 4
# |   %13 = load float, ptr %tmp1, align 4
# |   ret float %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_636 = alloca float, align 4
# |   %__s0_636 = alloca float, align 4
# |   %__s1_636 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_636, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_636, align 16
# |   %2 = load float, ptr %__s0_636, align 4
# |   %3 = load <4 x float>, ptr %__s1_636, align 16
# |   store <4 x float> %3, ptr %
# | ...
# `---data was truncated (10240/74804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005611fbbcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611fbbcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611fbbce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff813533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff81358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff813533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff81351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611fbb63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611fbb63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611fbb488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611fb7f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611fb7f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff81351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff81351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff81351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611fb7f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (381 of 27910)
******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13)
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundlit
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572b9e74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572b9e71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572b9e7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc09681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0968725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc09681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc096803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572b9e0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572b9e0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572b9def8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572b9a9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572b9a9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc096804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0968050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0968050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572b9a9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (382 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641f4d0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641f4d0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641f4d0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7e001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7e00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7e001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7e0003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641f4ca4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641f4ca4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641f4c898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641f4938e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641f4938b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa7e0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7e00050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7e00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641f4938a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (383 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1
# | ...
# `---data was truncated (10240/37926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005602f6db8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602f6db5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602f6db962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a77c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a77c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a77c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a77c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602f6d4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602f6d4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602f6d338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602f69e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602f69e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a77c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a77c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a77c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602f69e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/store.c (384 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   store <4 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <2 x float>
# |   store <2 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   store <1 x double> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %val.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %val, ptr %val.addr, align 8
# |   %0 = load <8 x i8>, ptr %val.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   store <4 x i16> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store <1 x i64> %val, ptr %val.addr, align 8
# |   %0 = load <1 x i64>, ptr %val.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %ptr.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   store <1 x i64> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   store <8 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   %__s1 = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   store <4 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr
# | ...
# `---data was truncated (10240/446007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055790e426eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055790e423e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055790e42762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27d9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27d98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27d9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27d9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055790e3bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055790e3bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055790e3a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055790e050e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055790e050b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27d9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27d98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27d98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055790e050a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (385 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000565402729eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565402726e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056540272a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f703f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f703f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f703f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f703f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654026bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654026bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654026a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565402353e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565402353b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f703f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f703f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f703f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565402353a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (386 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16mf8(<vscale x 8 x half> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ddbbb1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddbbb17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddbbb1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafaac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafaaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafaac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafaac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddbbab0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddbbab0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddbba958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddbb744e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddbb744b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafaac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafaac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafaac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddbb744a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (387 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6d0c61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6d0c5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6d0c6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe90ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe90ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe90ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe90ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6d0bf7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6d0bf7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6d0bdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6d088be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6d088bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe90ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe90ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe90ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6d088ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (388 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x2(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x2(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svscale_single_f64_x2(<vscale x 2 x double> %op1.coerce0, <vscale x 2 x double> %op1.coerce1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %op1.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x4(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x half> %op1.coerce2, <vscale x 8 x half> %op1.coerce3, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %op1.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x4(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x float> %op1.coerce2, <vscale x 4 x float> %op1.coerce3, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %op1.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr 
# | ...
# `---data was truncated (10240/37349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bbe730eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbe730be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbe730f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2793d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2793d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2793d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2793d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbe72a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbe72a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbe72898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbe6f38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbe6f38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2793d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2793d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2793d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbe6f38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (389 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/112825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c0af6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c0af6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c0af6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6e3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6e3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6e3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6e3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c0af04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c0af04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c0aee98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c0ab98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c0ab98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6e3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6e3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6e3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c0ab98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (390 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1)
# |   store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1)
# |   store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca double, align 8
# |   %ref.tmp.i = alloca double, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1)
# |   store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8
# |   %2 = load double, ptr %ref.tmp.i, align 8
# |   store double %2, ptr %__ret.i, align 8
# |   %3 = load double, ptr %__ret.i, align 8
# |   ret double %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16>
# |   %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3)
# |   store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32>
# |   %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9)
# |   store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %2, ptr %__ret, align 8
# |   %3 = load <4 x i16>, p
# | ...
# `---data was truncated (10240/770739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d8a5ae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8a5ae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8a5ae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f8c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f8c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f8c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f8c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8a5a79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8a5a79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8a5a5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8a570de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8a570db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f8c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f8c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f8c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8a570da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (391 of 27910)
******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu  -target-cpu swift   -target-feature +fullfp16 -ffreestanding   -flax-vector-conversions=none   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7s-apple-darwin"
# | 
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p0.addr.i1, align 8
# |   store <8 x i8> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %8, ptr %__ret.i3, align 8
# |   %9 = load <8 x i8>, ptr %__ret.i3, align 8
# |   %add.i = add <8 x i8> %3, %9
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x i16>, align 8
# |   %__p1.addr.i2 = alloca <4 x i16>, align 8
# |   %__ret.i3 = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %5 = load <4 x i16>, ptr %__p2.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p0.addr.i1, align 8
# |   store <4 x i16> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16>
# |   %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %8, ptr %__ret.i3, align 8
# |   %9 = load <4 x i16>, ptr %__ret.i3, align 8
# |   %add.i = add <4 x i16> %3, %9
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %10 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <2 x i32>, align 8
# |   %__p1.addr.i2 = alloca <2 x i32>, align 8
# |   %__ret.i3 = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x i32>, ptr %__p2.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p0.addr.i1, align 8
# |   store <2 x i32> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32>
# |   %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %8, ptr %__ret.i3, align 8
# |   %9 = load <2 x i32>, ptr %__ret.i3, align 8
# |   %add.i = add <2 x i32> %3, %9
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %10 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, pt
# | ...
# `---data was truncated (10240/2159854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b1b9950eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1b994de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1b995162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28f0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28f078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28f0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28f071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1b98e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1b98e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1b98cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1b957ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1b957ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28f071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28f071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28f071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1b957aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (392 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005565bc4f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565bc4f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565bc4f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a26933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a2698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a26933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a2691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565bc48abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565bc48aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565bc46f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565bc11ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565bc11eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a2691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a2691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a2691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565bc11ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (393 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i)
# |   store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i)
# |   store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i)
# |   store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i)
# |   store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i)
# |   store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i)
# |   store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/162735) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560419cf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560419cf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560419cf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ade41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ade4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ade41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ade403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560419c8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560419c8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560419c738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560419922e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560419922b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ade404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ade4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ade4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560419922a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (394 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale 
# | ...
# `---data was truncated (10240/13048) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7b5d78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7b5d75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7b5d7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9333b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9333b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9333b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9333b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7b5d0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7b5d0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7b5cf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7b59a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7b59a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9333b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9333b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9333b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7b59a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (395 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/46416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056329c085eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056329c082e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056329c08662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32e4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32e4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32e4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32e4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056329c01bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056329c01ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056329c0008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056329bcafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056329bcafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32e4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32e4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32e4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056329bcafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (396 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/53158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561c13579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c13576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c1357a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc545533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc54558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc545533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc54551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c1350fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c1350fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c134f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c131a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c131a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc54551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc54551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc54551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c131a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (397 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   st
# | ...
# `---data was truncated (10240/110292) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a279907eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a279904e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a27990862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3709049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37090a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3709049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3709031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a27989dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a27989da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2798828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a279531e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a279531b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3709032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37090330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37090330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a279531a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (398 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8_1(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 0)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16_1(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 0)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32_1(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64_1(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svext_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 127)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svext_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr 
# | ...
# `---data was truncated (10240/12880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560bda28eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bda28be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bda28f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe177d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe177d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe177d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe177d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bda224bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bda224a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bda2098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bd9eb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bd9eb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe177d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe177d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe177d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bd9eb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (399 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557e50478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e50475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e5047962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d8cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d8cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d8cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d8cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e5040ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e5040ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e503f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e500a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e500a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d8cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d8cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d8cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e500a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (400 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055809976deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055809976ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055809976e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3277905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f327795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3277905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32778ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558099703bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558099703a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580996e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558099397e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558099397b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32778eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32778ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32778ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558099397a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (401 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalt_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556ac0ce7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ac0ce4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ac0ce862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae5ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae5ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae5ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae5ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ac0c7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ac0c7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ac0c628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ac0911e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ac0911b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae5ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae5ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae5ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ac0911a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (402 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 3
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 2
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_374 = alloca <4 x bfloat>, align 8
# |   %__s0_374 = alloca <4 x bfloat>, align 8
# |   %__s2_374 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.add
# | ...
# `---data was truncated (10240/18871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bde7528eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bde7525e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bde752962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf5eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf5eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf5eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf5eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bde74bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bde74bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bde74a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bde7152e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bde7152b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf5eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf5eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf5eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bde7152a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (403 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599e7686eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599e7683e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599e768762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47e5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47e5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47e5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47e5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599e761cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599e761ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599e76018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599e72b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599e72b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47e5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47e5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47e5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599e72b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (404 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef4_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef4_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef4_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef4_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563ba41dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ba41dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ba41e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c8de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c8dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c8de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c8de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ba4175bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ba4175a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ba415a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ba3e09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ba3e09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c8de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c8de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c8de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ba3e09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (405 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bc81dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bc81dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bc81e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f534ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f534eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f534ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f534ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bc8175bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bc8175a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bc815a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bc7e09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bc7e09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f534ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f534ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f534ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bc7e09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (406 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 3, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 4, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cc12d7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc12d7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc12d8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a06a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a06aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a06a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a06a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc12d15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc12d15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc12cfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc129a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc129a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a06a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a06a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a06a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc129a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (407 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbo
# | ...
# `---data was truncated (10240/21216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005559b9206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559b9203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559b920762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3bca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3bcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3bca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3bca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559b919cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559b919ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559b91818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559b8e30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559b8e30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3bca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3bca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3bca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559b8e30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (408 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvtn_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt1_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt2_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr
# | ...
# `---data was truncated (10240/17058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055972ce01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055972cdfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055972ce0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f1a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f1a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f1a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f1a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055972cd97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055972cd97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055972cd7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055972ca2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055972ca2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f1a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f1a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f1a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055972ca2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (409 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055619284deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055619284ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055619284e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe611849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6118a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe611849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe611831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561927e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561927e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561927c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556192477e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556192477b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe611832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6118330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6118330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556192477a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (410 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 8, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 9, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bfefcedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfefceae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfefcee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc11e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc11e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc11e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc11e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfefc83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfefc83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfefc688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfef917e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfef917b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc11e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc11e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc11e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfef917a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (411 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563226c3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563226c3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563226c3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe933c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe933ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe933c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe933c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563226bd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563226bd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563226bb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563226868e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563226868b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe933c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe933c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe933c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563226868a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644dd6d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644dd6d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644dd6d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9847c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9847ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9847c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9847c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644dd66bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644dd66ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644dd6508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644dd2ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644dd2ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9847c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9847c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9847c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644dd2ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (413 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_x(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_m(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f2f733deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2f733ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2f733e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb66ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb66eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb66ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb66ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2f72d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2f72d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2f72b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2f6f67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2f6f67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb66ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb66ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb66ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2f6f67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (414 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e33acdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e33acae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e33ace62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f092c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f092c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f092c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f092c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e33a63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e33a63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e33a488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e336f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e336f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f092c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f092c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f092c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e336f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (415 of 27910)
******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %w.addr = alloca float, align 4
# |   store float %w, ptr %w.addr, align 4
# |   %0 = load float, ptr %w.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %1, i32 0
# |   %2 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1
# |   %3 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2
# |   %4 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %5 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   store <4 x float> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 {
# | entry:
# |   %V.addr = alloca <1 x double>, align 8
# |   %__ret_379 = alloca <2 x double>, align 16
# |   %__s0_379 = alloca <1 x double>, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   %tmp1 = alloca <2 x double>, align 16
# |   store <1 x double> %V, ptr %V.addr, align 8
# |   %0 = load <1 x double>, ptr %V.addr, align 8
# |   store <1 x double> %0, ptr %__s0_379, align 8
# |   %1 = load <1 x double>, ptr %__s0_379, align 8
# |   store <1 x double> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer
# |   store <2 x double> %lane, ptr %ref.tmp, align 16
# |   %4 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %4, ptr %__ret, align 16
# |   %5 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %5, ptr %tmp, align 16
# |   %6 = load <2 x double>, ptr %tmp, align 16
# |   store <2 x double> %6, ptr %__ret_379, align 16
# |   %7 = load <2 x double>, ptr %__ret_379, align 16
# |   store <2 x double> %7, ptr %tmp1, align 16
# |   %8 = load <2 x double>, ptr %tmp1, align 16
# |   ret <2 x double> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %6 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %6, ptr %__ret, align 8
# |   %7 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %7, ptr %tmp, align 8
# |   %8 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6
# |   %9 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %10 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %10, ptr %__ret, align 16
# |   %11 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %11, ptr %tmp, align 16
# |   %12 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %12
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562639f5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562639f58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562639f5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4766f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4766f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4766f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4766f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562639ef1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562639ef1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562639ed68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562639b85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562639b85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4766f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4766f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4766f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562639b85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (416 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556256fcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556256fc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556256fcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b9eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b9eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b9eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b9eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556256f60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556256f60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556256f458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556256bf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556256bf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b9eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b9eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b9eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556256bf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (417 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9b9bd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9b9bcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9b9bd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19c7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19c78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19c7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19c7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9b9b68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9b9b68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9b9b4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9b97fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9b97fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19c7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19c78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19c78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9b97fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (418 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/83088) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555669909eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555669906e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055566990a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1745533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f174558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1745533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f174551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055566989fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055566989fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556698848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555669533e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555669533b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f174551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f174551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f174551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555669533a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (419 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560ff9a1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ff9a17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ff9a1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5278649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52786a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5278649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5278631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ff99b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ff99b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ff99958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ff9644e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ff9644b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5278632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52786330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52786330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ff9644a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (420 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d413ef4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d413ef1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d413ef562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fe2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fe2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fe2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fe2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d413e8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d413e8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d413e6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d413b1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d413b1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fe2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fe2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fe2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d413b1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (421 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlastb_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlastb_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlastb_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a73fc59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a73fc56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a73fc5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3624333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f362438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3624333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f362431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a73fbefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a73fbefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a73fbd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a73f883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a73f883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f362431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f362431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f362431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a73f883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (422 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fad430deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fad430ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fad430e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fcfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fcfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fcfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fcfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fad42a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fad42a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fad42888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fad3f37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fad3f37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fcfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fcfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fcfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fad3f37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (423 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/22149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005634e29aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634e29a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634e29ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f171c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f171c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f171c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f171c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634e2942bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634e2942a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634e29278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634e25d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634e25d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f171c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f171c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f171c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634e25d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (424 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 8, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 9, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005641c738beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641c7388e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641c738c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5631b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5631b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5631b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5631b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641c7321bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641c7321a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641c73068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641c6fb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641c6fb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5631b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5631b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5631b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641c6fb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (425 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056189471feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056189471ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056189472062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ff7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ff72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ff7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ff7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618946b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618946b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056189469a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561894349e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561894349b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ff7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ff72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ff72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561894349a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (426 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600e57beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600e57bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600e57bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe33ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe33ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe33ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe33ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600e5754bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600e5754a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600e57398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600e53e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600e53e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe33ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe33ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe33ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600e53e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (427 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625bc482eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625bc47fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625bc48362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52ee249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52ee2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52ee249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52ee231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625bc418bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625bc418a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625bc3fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625bc0ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625bc0acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52ee232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52ee2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52ee2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625bc0aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (428 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_zt0() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_zt0() #1 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_zt0() #2 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_zt0() #3 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_zt0() #4 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_za_zt0() #5 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_za_zt0() #6 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_za_zt0() #7 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_za_zt0() #8 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_za_zt0() #9 {
# | entry:
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565531d6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565531d68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565531d6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe692b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe692b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe692b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe692aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565531d01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565531d01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565531ce68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565531995e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565531995b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe692aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe692aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe692aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565531995a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x0000562e94fb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e94fb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e94fb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab83d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab83d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab83d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab83d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e94f4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e94f4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e94f328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e94be1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e94be1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab83d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab83d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab83d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e94be1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (429 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b98a193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b98a190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b98a19462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d96b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d96b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d96b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d96b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b98a129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b98a129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b98a10e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b989dbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b989dbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d96b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d96b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d96b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b989dbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (430 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e006f3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e006f38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e006f3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa07449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa074a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa07449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa07431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e006ed1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e006ed1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e006eb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e006b65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e006b65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa07432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa074330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa074330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e006b65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (431 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a3203eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3203e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3203eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f841d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f841d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f841d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f841d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a320380bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a320380a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3203658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a320014e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a320014b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f841d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f841d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f841d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a320014a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (432 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef2_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef4_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564a14febeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a14fe8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a14fec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6703533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f670358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6703533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f670351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a14f81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a14f81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a14f668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a14c15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a14c15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f670351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f670351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f670351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a14c15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (433 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x hal
# | ...
# `---data was truncated (10240/514165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b80d3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b80d3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b80d3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ca7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ca798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ca7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ca791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b80cd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b80cd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b80cb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b80967e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b80967b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ca791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ca791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ca791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b80967a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056532f0c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056532f0c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056532f0c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28ca933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28ca98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28ca933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28ca91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056532f05dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056532f05da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056532f0428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056532ecf1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056532ecf1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28ca91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28ca91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28ca91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056532ecf1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (435 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/68141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d2c722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d2c71fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d2c72362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9706333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f970638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9706333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f970631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d2c6b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d2c6b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d2c69d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d2c34ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d2c34cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f970631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f970631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f970631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d2c34ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (436 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560584ab5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560584ab2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560584ab662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd23f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd23f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd23f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd23f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560584a4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560584a4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560584a308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605846dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605846dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd23f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd23f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd23f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605846dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (437 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d352928eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d352925e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d35292962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f721b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f721b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f721b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f721b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3528bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3528bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3528a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d352552e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d352552b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f721b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f721b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f721b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d352552a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (438 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c9a3fdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9a3fdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9a3fdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1235533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f123558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1235533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f123551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9a3f74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9a3f74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9a3f598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9a3c08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9a3c08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f123551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f123551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f123551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9a3c08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0, i64 %2)
# | ...
# `---data was truncated (10240/69831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb452b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb452b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb452b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11d3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11d38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11d3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11d3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb4524abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb4524aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb4522f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb44edee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb44edeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11d3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11d38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11d38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb44edea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (440 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 29, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 30, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005608d295ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608d2959e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608d295d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f223c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f223c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f223c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f223c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608d28f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608d28f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608d28d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608d2586e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608d2586b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f223c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f223c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f223c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608d2586a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (441 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c42428eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c42428be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c42428f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0caf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0caf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0caf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0caf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c424224bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c424224a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4242098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c423eb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c423eb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0caf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0caf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0caf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c423eb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (442 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 1
# | ...
# `---data was truncated (10240/48782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557cc3a45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cc3a42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cc3a4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3c691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cc39dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cc39dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cc39c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cc366fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cc366fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3c691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cc366fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (443 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/135337) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633de49beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633de498e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633de49c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89e3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89e3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89e3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89e3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633de431bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633de431a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633de4168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633de0c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633de0c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89e3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89e3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89e3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633de0c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (444 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/72493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2f4d35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2f4d32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2f4d3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe37661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3766725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe37661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe376603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2f4ccbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2f4ccba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2f4cb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2f495fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2f495fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe376604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3766050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3766050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2f495fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (445 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfs
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055825851aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558258517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055825851b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24b5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24b54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24b5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24b5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582584b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582584b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582584958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558258144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558258144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24b5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24b54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24b54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558258144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (446 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f7ecbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f7ecbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f7ecbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafdf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafdf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafdf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafdf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f7ec54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f7ec54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f7ec398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f7e8e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f7e8e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafdf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafdf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafdf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f7e8e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/andv.c (447 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055a88ceb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a88ceade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a88ceb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1fe249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1fe2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1fe249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1fe231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a88ce46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a88ce46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a88ce2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a88cadae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a88cadab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1fe232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1fe2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1fe2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a88cadaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (448 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %
# | ...
# `---data was truncated (10240/74176) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005584d4afaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584d4af7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584d4afb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe01449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe014a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe01449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe01431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584d4a90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584d4a90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584d4a758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584d4724e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584d4724b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe01432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe014330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe014330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584d4724a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (449 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x
# | ...
# `---data was truncated (10240/101475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab46a34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab46a31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab46a3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66e7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66e7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66e7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66e7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab469cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab469caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab469af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab4665ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab4665eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66e7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66e7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66e7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab4665ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (450 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564e64f1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e64f19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e64f1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3cae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3cae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3cae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3cae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e64eb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e64eb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e64e978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e64b46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e64b46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3cae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3cae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3cae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e64b46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (451 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_72 = alloca <4 x i16>, align 8
# |   %__s0_72 = alloca <4 x i16>, align 8
# |   %__s1_72 = alloca <4 x i16>, align 8
# |   %__s2_72 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_72, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_72, align 8
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_72, align 8
# |   %3 = load <4 x i16>, ptr %__s0_72, align 8
# |   %4 = load <4 x i16>, ptr %__s1_72, align 8
# |   %5 = load <4 x i16>, ptr %__s2_72, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_72, align 8
# |   %11 = load <4 x i16>, ptr %__ret_72, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_62 = alloca <8 x i16>, align 16
# |   %__s0_62 = alloca <8 x i16>, align 16
# |   %__s1_62 = alloca <8 x i16>, align 16
# |   %__s2_62 = alloca <4 x i16>, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_62, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_62, align 16
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_62, align 8
# |   %3 = load <8 x i16>, ptr %__s0_62, align 16
# |   %4 = load <8 x i16>, ptr %__s1_62, align 16
# |   %5 = load <4 x i16>, ptr %__s2_62, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   %mul = mul <8 x i16> %4, %10
# |   %add = add <8 x i16> %3, %mul
# |   store <8 x i16> %add, ptr %__ret_62, align 16
# |   %11 = load <8 x i16>, ptr %__ret_62, align 16
# |   store <8 x i16> %11, ptr %tmp1, align 16
# |   %12 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_70 = alloca <2 x i32>, align 8
# |   %__s0_70 = alloca <2 x i32>, align 8
# |   %__s1_70 = alloca <2 x i32>, align 8
# |   %__s2_70 = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_70, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_70, align 8
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_70, align 8
# |   %3 = load <2 x i32>, ptr %__s0_70, align 8
# |   %4 = load <2 x i32>, ptr %__s1_70, align 8
# |   %5 = load <2 x i32>, ptr %__s2_70, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   %mul = mul <2 x i32> %4, %10
# |   %add = add <2 x i32> %3, %mul
# |   store <2 x i32> %add, ptr %__ret_70, align 8
# |   %11 = load <2 x i32>, ptr %__ret_70, align 8
# |   store <2 x i32> %11, ptr %tmp1, align 8
# |   %12 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_60 = alloca <4 x i32>, align 16
# |   %__s0_60 = alloca <4 x i32>, align 16
# |   %__s1_60 = alloca <4 x i32>, align 16
# |   %__s2_60 = alloca <2 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_60, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1_60, align 16
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_60, align 8
# |   %3 = load <4 x i32>, ptr %__s0_60, align 16
# |   %4 = load <4 x i32>, ptr %__s1_60, align 16
# |   %5 = load <2 x i32>, ptr %__s2_60, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x i32> %lane, ptr %ref.tmp, align 16
# |   %8 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %8, ptr %__ret, align 16
# |   %9 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %9, ptr %tmp, align 16
# |   %10 = load <4 x i32>, ptr %tmp, align 16
# |   %mul = mul <4 x i32> %4, %10
# |   %add = add <4 x i32> %3, %mul
# |   store <4 x i32> %add, ptr %__ret_60, align 16
# |   %11 = load <4 x i32>, ptr %__ret_60, align 16
# |   store <4 x i32> %11, ptr %tmp1, align 16
# |   %12 = load <4 x i32>, ptr %tmp1, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_482 = alloca <4 x i16>, align 8
# |   %__s0_482 = alloca <4 x i16>, align 8
# |   %__s1_482 = alloca <4 x i16>, align 8
# |   %__s2_482 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_482, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_482, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_482, align 16
# |   %3 = load <4 x i16>, ptr %__s0_482, align 8
# |   %4 = load <4 x i16>, ptr %__s1_482, align 8
# |   %5 = load <8 x i16>, ptr %__s2_482, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_482, align 8
# |   %11 = load <4 x i16>, ptr %__ret_482, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_472 = alloca <8 x i16>, align 16
# |   %__s0_472 = alloca <8 x i16>, align 16
# |   %__s1_472 = alloca <8
# | ...
# `---data was truncated (10240/857511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562e6bef8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e6bef5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e6bef962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64fa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64fa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64fa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64fa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e6be8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e6be8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e6be738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e6bb22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e6bb22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64fa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64fa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64fa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e6bb22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557434b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557434b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557434b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f0b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f0b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f0b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f0b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555743449bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555743449a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055574342e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557430dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557430ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f0b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f0b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f0b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557430dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (453 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ab1f5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ab1f59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ab1f5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0123d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0123d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0123d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0123d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ab1ef2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ab1ef2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ab1ed78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ab1b86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ab1b86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0123d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0123d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0123d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ab1b86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (454 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625f0f3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625f0f3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625f0f3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68b0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68b06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68b0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68b0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625f0ed3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625f0ed3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625f0eb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625f0b67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625f0b67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68b0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68b06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68b06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625f0b67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (455 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596d15aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596d15a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596d15ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a0203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596d1540bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596d1540a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596d15258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596d11d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596d11d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74a0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a02050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596d11d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (456 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555bc5320eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bc531de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bc532162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12de933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12de98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12de933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12de91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bc52b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bc52b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bc529b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bc4f4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bc4f4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12de91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12de91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12de91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bc4f4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (457 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za16_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za32_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558eaad53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558eaad50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558eaad5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3ec333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3ec38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3ec333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3ec31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eaace9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558eaace9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558eaacce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558eaa97de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558eaa97db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3ec31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3ec31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3ec31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558eaa97da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (458 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056205657ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562056579e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056205657d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ae8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ae878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ae8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ae871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562056512bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562056512a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620564f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620561a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620561a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ae871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ae871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ae871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620561a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/len.c (459 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c         | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vscale.i64() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000560b10e62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b10e5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b10e6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa70ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b10df8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b10df8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b10ddd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b10a8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b10a8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7aa70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa70ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b10a8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (460 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr
# | ...
# `---data was truncated (10240/26796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005604f8476eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604f8473e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604f847762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff02ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff02ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff02ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff02ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604f840cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604f840ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604f83f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604f80a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604f80a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff02ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff02ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff02ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604f80a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (461 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x flo
# | ...
# `---data was truncated (10240/29327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc45c23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc45c20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc45c2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7928449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79284a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7928449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7928431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc45bb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc45bb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc45b9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc4584de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc4584db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7928432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79284330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79284330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc4584da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (462 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb3425ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb34259e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb3425d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9e2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9e235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9e2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9e22ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb341f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb341f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb341d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb33e86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb33e86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9e22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9e22ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9e22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb33e86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (463 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv
# | ...
# `---data was truncated (10240/75133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563275dfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563275dfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563275dff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc24f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc24f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc24f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc24f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563275d94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563275d94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563275d798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563275a28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563275a28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc24f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc24f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc24f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563275a28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (464 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561d11b67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d11b64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d11b6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1015049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10150a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1015049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1015031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d11afdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d11afda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d11ae28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d11791e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d11791b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1015032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10150330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10150330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d11791a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/load.c (465 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %0, align 2
# |   store <8 x half> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %2, ptr %__ret, align 16
# |   %3 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %3, ptr %tmp, align 16
# |   %4 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %0, align 4
# |   store <4 x float> %1, ptr %ref.tmp, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %2, ptr %__ret, align 16
# |   %3 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %3, ptr %tmp, align 16
# |   %4 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <2 x double>, ptr %0, align 8
# |   store <2 x double> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %2, ptr %__ret, align 16
# |   %3 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %3, ptr %tmp, align 16
# |   %4 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   store <2 x i64> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %2, ptr %__ret, align 16
# |   %3 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %3, ptr %tmp, align 16
# |   %4 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store ptr %a
# | ...
# `---data was truncated (10240/415795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x0000563bcf1c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bcf1c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bcf1c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd38e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd38e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd38e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd38e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bcf15cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bcf15ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bcf1418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bcedf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bcedf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd38e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd38e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd38e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bcedf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (466 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a679753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a679750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a67975462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75db849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75db8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75db849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75db831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6796e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6796e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6796ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a67937de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a67937db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75db832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75db8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75db8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a67937da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (467 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e9abdd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9abdcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9abdd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3ace49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3acea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3ace49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3ace31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9abd68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9abd68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9abd4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9ab9fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9ab9fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3ace32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3ace330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3ace330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9ab9fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (468 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c8eb2a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8eb29de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8eb2a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec78933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec7898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec78933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec7891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8eb236bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8eb236a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8eb21b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8eaecae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8eaecab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec7891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec7891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec7891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8eaecaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (469 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = sub <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fsub <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = sub <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fsub <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000563e091b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e091b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e091b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f466ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f466ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f466ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f466eced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e0914bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e0914ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e091308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e08ddfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e08ddfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f466eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f466ecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f466ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e08ddfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056417dcedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056417dceae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056417dcee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f464e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f464e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f464e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f464e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056417dc83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056417dc83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056417dc688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056417d917e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056417d917b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f464e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f464e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f464e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056417d917a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (471 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cda10faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cda10f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cda10fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f156ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f156ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f156ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f156ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cda1090bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cda1090a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cda10758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cda0d24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cda0d24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f156ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f156ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f156ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cda0d24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (472 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005625c0150eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625c014de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625c015162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e38649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e386a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e38649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e38631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625c00e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625c00e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625c00cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625bfd7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625bfd7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e38632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e386330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e386330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625bfd7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (473 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5fdd0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5fdd0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5fdd1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f060c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f060c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f060c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f060c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5fdca5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5fdca5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5fdc8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5fd939e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5fd939b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f060c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f060c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f060c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5fd939a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (474 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fce7a82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fce7a7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fce7a8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a8f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a8f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a8f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a8f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fce7a18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fce7a18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fce79fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fce76ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fce76acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a8f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a8f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a8f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fce76aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/linker-diagnostic.ll (475 of 27910)
******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# |  #0 0x00005574ad002eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574acfffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574ad00362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea3db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea3db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea3db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea3daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574acf98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574acf98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574acf7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574acc2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574acc2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea3daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea3daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea3daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574acc2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (476 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <16 x i8> %4 to <8 x half>
# |   %fmla1 = bitcast <16 x i8> %3 to <8 x half>
# |   %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %fmla2, ptr %ref.tmp, align 16
# |   %7 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %7, ptr %__ret, align 16
# |   %8 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %8, ptr %tmp, align 16
# |   %9 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %10, ptr %__ret, align 8
# |   %11 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %11, ptr %tmp, align 8
# |   %12 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16
# | ...
# `---data was truncated (10240/13273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005651eb664eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651eb661e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651eb66562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2673649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26736a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2673649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2673631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651eb5fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651eb5faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651eb5df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651eb28ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651eb28eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2673632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26736330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26736330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651eb28ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (477 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564bf8cdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bf8cd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bf8cdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbd6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbd62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbd6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbd6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bf8c71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bf8c71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bf8c568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bf8905e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bf8905b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbd6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbd62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbd62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bf8905a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (478 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaa2a51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaa2a4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaa2a5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc303a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc303aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc303a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc303a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa29e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaa29e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaa29cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaa267be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaa267bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc303a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc303a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc303a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaa267ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (479 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557ecffd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ecffd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ecffd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4da1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4da1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4da1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4da1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ecff6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ecff6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ecff508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ecfbffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ecfbffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4da1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4da1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4da1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ecfbffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (480 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563b87823eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b87820e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b8782462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8616a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8616aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8616a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8616a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b877b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b877b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b8779e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b8744de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b8744db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8616a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8616a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8616a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b8744da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (481 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |  
# | ...
# `---data was truncated (10240/16804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563d34ac0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d34abde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d34ac162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe225c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe225c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe225c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe225c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d34a56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d34a56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d34a3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d346eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d346eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe225c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe225c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe225c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d346eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (482 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtblq_f16(<vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtblq_f32(<vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtblq_f64(<vscale x 2 x double> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtblq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta
# | ...
# `---data was truncated (10240/10820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562832002eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562831fffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056283200362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5457849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5457849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5457831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562831f98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562831f98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562831f7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562831c2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562831c2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5457832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54578330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562831c2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (483 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate4_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1, <vscale x 16 x i1> %x2, <vscale x 16 x i1> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   %x2.addr = alloca <vscale x 16 x i1>, align 2
# |   %x4.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   store <vscale x 16 x i1> %x2, ptr %x2.addr, align 2
# |   store <vscale x 16 x i1> %x4, ptr %x4.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %x2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x4.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6, <vscale x 16 x i1> %3, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %7
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557333b21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557333b1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557333b2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc52661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5266725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc52661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc526603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557333ab7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557333ab7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557333a9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055733374be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055733374bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc526604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5266050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5266050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055733374ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (484 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611c7700eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611c76fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611c770162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe9c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe9c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe9c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe9c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611c7696bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611c7696a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611c767b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611c732ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611c732ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe9c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe9c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe9c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611c732aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (485 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svld2_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm
# | ...
# `---data was truncated (10240/24404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556b8fdd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b8fdcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b8fdd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1ae61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1ae6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1ae61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1ae603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b8fd66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b8fd66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b8fd4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b8f9fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b8f9fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa1ae604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1ae6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1ae6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b8f9faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (486 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560e69d40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e69d3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e69d4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe017505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe01755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe017505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0174ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e69cd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e69cd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e69cbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e6996ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e6996ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0174eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0174ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0174ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e6996aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (487 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b35bdadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b35bdaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b35bdae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc227c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc227c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc227c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc227c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b35bd43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b35bd43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b35bd288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b35b9d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b35b9d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc227c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc227c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc227c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b35b9d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (488 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560647266eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560647263e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056064726762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f035ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f035ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f035ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f035ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606471fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606471fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606471e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560646e90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560646e90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f035ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f035ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f035ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560646e90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (489 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bee76a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bee76a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bee76a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc8b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc8b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc8b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc8b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bee763ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bee763ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bee76238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bee72d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bee72d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc8b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc8b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc8b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bee72d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (490 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llv
# | ...
# `---data was truncated (10240/59779) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557489e82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557489e7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557489e8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6ded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6ded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6ded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6ded1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557489e18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557489e18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557489dfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557489aace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557489aacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6ded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6ded1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6ded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557489aaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (491 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmmla_f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 2 x double>, align 16
# |   %y.addr = alloca <vscale x 2 x double>, align 16
# |   %z.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x, ptr %x.addr, align 16
# |   store <vscale x 2 x double> %y, ptr %y.addr, align 16
# |   store <vscale x 2 x double> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %y.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %z.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056269b327eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056269b324e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056269b32862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96d2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96d2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96d2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96d2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056269b2bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056269b2bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056269b2a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056269af51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056269af51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96d2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96d2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96d2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056269af51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (492 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557190825eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557190822e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055719082662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc8f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc8f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc8f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc8f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571907bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571907bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571907a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055719044fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055719044fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc8f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc8f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc8f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055719044fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (493 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8e1dafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8e1dace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8e1db062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc38a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc38a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc38a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc38a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8e1d45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8e1d45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8e1d2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8e19d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8e19d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc38a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc38a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc38a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8e19d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (494 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da82b42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da82b3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da82b4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3091933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f309198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3091933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f309191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da82ad8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da82ad8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da82abd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da8276ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da8276cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f309191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f309191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f309191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da8276ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (495 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.1a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %c.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   %2 = load <8 x i16>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %c.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   %2 = load <4 x i32>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   store <4 x i32> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32>
# |   %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32>
# |   %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i)
# |   %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   %__ret_140 = alloca <4 x i16>, align 8
# |   %__s0_140 = alloca <4 x i16>, align 8
# |   %__s1_140 = alloca <4 x i16>, align 8
# |   %__s2_140 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_140, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_140, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_140, align 8
# |   %3 = load <4 x i16>, ptr %__s0_140, align 8
# |   %4 = load <4 x i16>, ptr %__s1_140, align 8
# |   %5 = load <4 x i16>, ptr %__s2_140, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_140, align 8
# |   %16 = load <4 x i16>, ptr %__ret_140, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr
# | ...
# `---data was truncated (10240/38786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x000055ccd2098eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccd2095e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccd209962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5b1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5b195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5b1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5b18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccd202ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccd202ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccd20138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccd1cc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccd1cc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5b18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5b18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5b18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccd1cc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (496 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555d422edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d422eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d422ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9814e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9814e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9814e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9814e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d42283bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d42283a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d422688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d41f17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d41f17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9814e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9814e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9814e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d41f17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (497 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/235596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564dc162deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564dc162ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564dc162e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e37333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e3738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e37333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e3731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564dc15c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564dc15c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564dc15a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564dc1257e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564dc1257b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e3731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e3731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e3731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564dc1257a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (498 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align
# | ...
# `---data was truncated (10240/19041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564bcf86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564bcf83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564bcf8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f507a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f507a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f507a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f507a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564bcf1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564bcf1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564bcf018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564bcbb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564bcbb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f507a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f507a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f507a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564bcbb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (499 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/68429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630f19a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630f19a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630f19a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa14a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa14a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa14a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa14a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630f193cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630f193ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630f19218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630f15d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630f15d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa14a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa14a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa14a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630f15d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (500 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056144e42deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056144e42ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056144e42e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5aa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5aa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5aa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5aa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056144e3c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056144e3c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056144e3a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056144e057e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056144e057b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5aa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5aa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5aa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056144e057a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (501 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564116db8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564116db5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564116db962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cca333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cca38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cca333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cca31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564116d4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564116d4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564116d338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641169e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641169e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cca31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cca31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cca31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641169e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (502 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2c650deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2c650ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2c650e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7390133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f739018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7390133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f739011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2c64a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2c64a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2c64888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2c6137e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2c6137b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f739011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f739011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f739011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2c6137a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (503 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, 
# | ...
# `---data was truncated (10240/288103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564713c2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564713c27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564713c2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb586b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb586b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb586b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb586b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564713bc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564713bc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564713ba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564713854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564713854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb586b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb586b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb586b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564713854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/widen.c (504 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = sext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = sext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = sext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = zext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = zext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = zext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i1 = alloca <8 x i8>, align 8
# |   %__p0_561.addr.i = alloca <16 x i8>, align 16
# |   %__ret_561.i = alloca <8 x i16>, align 16
# |   %__a1_561.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %__s0.i = alloca <8 x i8>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0_561.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i1, align 8
# |   store <8 x i8> %4, ptr %__a1_561.i, align 8
# |   %5 = load <8 x i8>, ptr %__a1_561.i, align 8
# |   store <8 x i8> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = sext <8 x i8> %6 to <8 x i16>
# |   store <8 x i16> %7, ptr %ref.tmp1.i, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16
# |   store <8 x i16> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %9, ptr %tmp.i, align 16
# |   %10 = load <8 x i16>, ptr %tmp.i, align 16
# |   store <8 x i16> %10, ptr %ref.tmp.i, align 16
# |   %11 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %11, ptr %__ret_561.i, align 16
# |   %12 = load <8 x i16>, ptr %__ret_561.i, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i1 = alloca <4 x i16>, align 8
# |   %__p0_567.addr.i = alloca <8 x i16>, align 16
# |   %__ret_567.i = alloca <4 x i32>, align 16
# |   %__a1_567.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0_567.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i1, align 8
# |   store <4 x i16> %4, ptr %__a1_567.i, align 8
# |   %5 = load <4 x i16>, ptr %__a1_567.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = sext <4 x i16> %7 to <4 x i32>
# |   store <4 x i32> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %12, ptr %__ret_567.i, align 16
# |   %13 = load <4 x i32>, ptr %__ret_567.i, align 16
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i1 = alloca <2 x i32>, align 8
# |   %__p0_564.addr.i = alloca <4 x i32>, align 16
# |   %__ret_564.i = alloca <2 x i64>, align 16
# |   %__a1_564.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %__s0.i = alloca <2 x i32>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0_564.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i1, align 8
# |   store <2 x i32> %4, ptr %__a1_564.i, align 8
# |   %5 = load <2 x i32>, ptr %__a1_564.i, align 8
# |   store <2 x i32> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %8 = sext <2 x i32> %7 to <2 x i64>
# |   store <2 x i64> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16
# |   store <2 x i64> %9, ptr %__ret.i, align 16
# |   %10 = load <2 x i64>, ptr %__ret.i, align 16
# |   store <2 x i64> %10, ptr %tmp.i, align 16
# |   %11 = load <2 x i64>, ptr %tmp.i, align 16
# |   store <2 x i64> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <2 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005569d9f76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569d9f73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569d9f7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f458cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f458cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f458cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f458cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569d9f0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569d9f0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569d9ef18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569d9ba0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569d9ba0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f458cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f458cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f458cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569d9ba0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/nand.c (505 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnand_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005625fac82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625fac7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625fac8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8c7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8c78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8c7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8c7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625fac18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625fac18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625fabfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625fa8ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625fa8acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8c7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8c78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8c78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625fa8aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (506 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005615c474deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615c474ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615c474e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dc5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dc558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dc5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dc551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615c46e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615c46e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615c46c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615c4377e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615c4377b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dc551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dc551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dc551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615c4377a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/add.c (507 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %add.i = add <16 x i8> %2, %3
# |   store <16 x i8> %add.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %add.i = add <8 x i16> %2, %3
# |   store <8 x i16> %add.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b
# | ...
# `---data was truncated (10240/221881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055a236c98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a236c95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a236c9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab62133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab6218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab62133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab6211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a236c2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a236c2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a236c138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2368c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2368c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab6211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab6211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab6211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2368c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (508 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560740242eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056074023fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056074024362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab2301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab230725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab2301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab23003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607401d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607401d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607401bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056073fe6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056073fe6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab23004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab230050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab230050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056073fe6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (509 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564003703eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564003700e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056400370462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f043e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f043e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f043e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f043e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564003699bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564003699a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056400367e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056400332de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056400332db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f043e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f043e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f043e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056400332da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (510 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055844421ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558444219e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055844421d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69acf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69acf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69acf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69aceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584441b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584441b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584441978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558443e46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558443e46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69aceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69aceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69aceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558443e46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (511 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be0553ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be05539e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be0553d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf19849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf198a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf19849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf19831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be054d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be054d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be054b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be05166e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be05166b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf19832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf198330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf198330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be05166a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056210d7b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056210d7b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056210d7b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17af449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17af4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17af449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17af431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210d74dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056210d74da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056210d7328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056210d3e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056210d3e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17af432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17af4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17af4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056210d3e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (513 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bi
# | ...
# `---data was truncated (10240/136481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ba874deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ba874ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ba874e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce4bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce4bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce4bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce4bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ba86e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ba86e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ba86c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ba8377e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ba8377b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce4bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce4bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce4bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ba8377a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (514 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605648abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605648a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605648ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f453c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f453c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f453c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f453c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560564841bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560564841a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605648268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605644d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605644d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f453c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f453c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f453c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605644d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (515 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e8a27feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e8a27ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e8a28062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a2cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a2cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a2cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a2cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e8a215bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e8a215a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e8a1fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e89ea9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e89ea9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a2cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a2cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a2cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e89ea9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (516 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056060f949eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056060f946e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056060f94a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98c0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98c0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98c0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98c0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056060f8dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056060f8dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056060f8c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056060f573e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056060f573b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98c0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98c0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98c0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056060f573a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/poly64.c (517 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none  -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %cmp.i = icmp eq <1 x i64> %2, %3
# |   %sext.i = sext <1 x i1> %cmp.i to <1 x i64>
# |   store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %cmp.i = icmp eq <2 x i64> %2, %3
# |   %sext.i = sext <2 x i1> %cmp.i to <2 x i64>
# |   store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %6 = and <1 x i64> %4, %5
# |   %7 = icmp ne <1 x i64> %6, zeroinitializer
# |   %vtst.i = sext <1 x i1> %7 to <1 x i64>
# |   store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8
# |   %8 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %8, ptr %__ret.i, align 8
# |   %9 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %6 = and <2 x i64> %4, %5
# |   %7 = icmp ne <2 x i64> %6, zeroinitializer
# |   %vtst.i = sext <2 x i1> %7 to <2 x i64>
# |   store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16
# |   %8 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %8, ptr %__ret.i, align 16
# |   %9 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_913 = alloca <1 x i64>, align 8
# |   %__s0_913 = alloca <1 x i64>, align 8
# |   %__s2_913 = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp3 = alloca <1 x i64>, align 8
# |   %tmp4 = alloca <1 x i64>, align 8
# |   %tmp5 = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0_913, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_913, align 8
# |   %2 = load <1 x i64>, ptr %__s2_913, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <1 x i64>, ptr %__s0_913, align 8
# |   store <1 x i64> %7, ptr %__s1, align 8
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <1 x i64>, ptr %__s1, align 8
# |   %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0
# |   store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <1 x i64>, ptr %ref.tmp3, align 8
# |   store <1 x i64> %10, ptr %__ret, align 8
# |   %11 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %11, ptr %tmp4, align 8
# |   %12 = load <1 x i64>, ptr %tmp4, align 8
# |   store <1 x i64> %12, ptr %__ret_913, align 8
# |   %13 = load <1 x i64>, ptr %__ret_913, align 8
# |   store <1 x i64> %13, ptr %tmp5, align 8
# |   %14 = load <1 x i64>, ptr %tmp5, align 8
# |   ret <1 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_909 = alloca <2 x i64>, align 16
# |   %__s0_909 = alloca <2 x i64>, align 16
# |   %__s2_909 = alloca <1 x i64>, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_909, align 16
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_909, align 8
# |   %2 = load <1 x i64>, ptr %__s2_909, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <2 x i64>, ptr %__s0_909, align 16
# |   store <2 x i64> %7, ptr %__s1, align 16
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <2 x i64>, ptr %__s1, align 16
# |   %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1
# |   store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <2 x i64>, ptr %ref.tmp3, align 16
# |   store <2 x i64> %10, ptr %__ret, align 16
# |   %11 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %11, ptr %tmp4, align 16
# |   %12 = load <2 x i64>, ptr %tmp4, align 16
# |   store <2 x i64> %12, ptr %__ret_909, align 16
# |   %13 = load <2 x i64>, ptr %__ret_909, align 16
# |   store <2 x i64> %13, ptr %tmp5, align 16
# |   %14 = load <2 x i64>, ptr %tmp5, align 16
# |   ret <2 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret_915 = alloca <2 x i64>, align 16
# |   %__s0_915 = alloca <2 x i64>, align 16
# |   %__s2_915 = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_915, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s2_915, align 16
# |   %2 = load <2 x i64>, ptr %__s2_915, align 16
# |   store <2 x i64> %2, ptr %__s02, align 16
# |   %3 = load <2 x i64>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <2 x i64> %3, i32 1
# |   store i64 %vgetq_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = 
# | ...
# `---data was truncated (10240/22456) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561a42295eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a42292e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a4229662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a5bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a5bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a5bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a5bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a4222bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a4222ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a422108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a41ebfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a41ebfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a5bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a5bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a5bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a41ebfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (518 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619f5d08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619f5d05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619f5d0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1657a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1657a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1657a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1657a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619f5c9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619f5c9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619f5c838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619f5932e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619f5932b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1657a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1657a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1657a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619f5932a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (519 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595eaeb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595eaeaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595eaeb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5562305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f556235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5562305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55622ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595eae47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595eae47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595eae2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595eaadbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595eaadbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55622eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55622ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55622ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595eaadba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (520 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005613ba136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613ba133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613ba13762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd395249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3952a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd395249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd395231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613ba0ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613ba0cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613ba0b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613b9d60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613b9d60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd395232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3952330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3952330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613b9d60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (521 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d0073beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d00738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d0073c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4426133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f442618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4426133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f442611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d006d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d006d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d006b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d00365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d00365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f442611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f442611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f442611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d00365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (522 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef5ef54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef5ef51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef5ef5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e6dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e6dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e6dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e6dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef5eeeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef5eeeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef5eecf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef5eb7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef5eb7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e6dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e6dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e6dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef5eb7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (523 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_bf16(<vscale x 8 x bfloat> %zn_zm.coerce0, <vscale x 8 x bfloat> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16(<vscale x 8 x half> %zn_zm.coerce0, <vscale x 8 x half> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnb_f8_f32(<vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnt_f8_f32(<vscale x 16 x i8> %zd, <vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zd.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store <vscale x 16 x i8> %zd, ptr %zd.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zd.addr, align 16
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   %7 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret <vscale x 16 x i8> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561593529eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561593526e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056159352a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8e6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8e655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8e6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8e64ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615934bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615934bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615934a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561593153e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561593153b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8e64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8e64ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8e64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561593153a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (524 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef3_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef3_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef3_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef3_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a97b11ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a97b119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a97b11d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc16c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc16c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc16c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc16c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a97b0b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a97b0b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a97b0978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a97ad46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a97ad46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc16c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc16c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc16c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a97ad46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (525 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056461a9cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056461a9cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056461a9d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cbae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cbaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cbae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cbae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056461a965bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056461a965a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056461a94a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056461a5f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056461a5f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0cbae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cbae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cbae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056461a5f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (526 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s16_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, <vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u16_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <v
# | ...
# `---data was truncated (10240/25017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556cc1206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cc1203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cc120762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86b4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86b44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86b4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86b4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cc119cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cc119ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cc11818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cc0e30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cc0e30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86b4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86b44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86b44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cc0e30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/124506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c8646beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c86468e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c8646c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7771933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f777198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7771933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f777191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c86401bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c86401a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c863e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c86095e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c86095b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f777191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f777191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f777191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c86095a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (528 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1, <vscale x 8 x bfloat> %zm.coerce2, <vscale x 8 x bfloat> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, <vscale x 8 x bfloat> %zm.coerce2, 2
# |   %7 = insertvalue { <v
# | ...
# `---data was truncated (10240/13687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564ab7b60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ab7b5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ab7b6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc62b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc62b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc62b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc62b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ab7af6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ab7af6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ab7adb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ab778ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ab778ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc62b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc62b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc62b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ab778aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (529 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 8 x half
# | ...
# `---data was truncated (10240/88476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f597dc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f597dc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f597dc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a90e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a90ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a90e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a90e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f597d5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f597d5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f597d438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5979f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5979f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a90e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a90e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a90e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5979f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (530 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1c17c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1c17bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1c17c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38df505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38df55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38df505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38df4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1c1756bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1c1756a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1c173b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1c13eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1c13eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38df4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38df4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38df4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1c13eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (531 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_m(<vscale x 8 x bfloat> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558efede2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558efeddfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558efede362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2799f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2799f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2799f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2799f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558efed78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558efed78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558efed5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558efea0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558efea0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2799f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2799f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2799f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558efea0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (532 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557af33d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557af33d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557af33d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff07449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff074a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff07449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff07431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557af3369bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557af3369a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557af334e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557af2ffde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557af2ffdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff07432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff074330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff074330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557af2ffda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (533 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a989b80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a989b7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a989b8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9b8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9b8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9b8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9b8ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a989b16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a989b16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a989afb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9897aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9897aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9b8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9b8cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9b8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9897aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (534 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call
# | ...
# `---data was truncated (10240/48703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558693cd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558693cd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558693cd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff38933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff3898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff38933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff3891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558693c6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558693c6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558693c518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558693900e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558693900b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff3891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff3891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff3891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558693900a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (535 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf0fbb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf0fbade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf0fbb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37a3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37a3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37a3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37a3e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf0fb46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf0fb46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf0fb2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf0f7dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf0f7dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37a3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37a3e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37a3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf0f7daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (536 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 
# | ...
# `---data was truncated (10240/21465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4b34c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4b34bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4b34c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f083f305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f083f35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f083f305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f083f2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4b3456bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4b3456a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4b343b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4b30eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4b30eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f083f2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f083f2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f083f2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4b30eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (537 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcf7461eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcf745ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcf746262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ec9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ec94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ec9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ec9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcf73f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcf73f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcf73dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcf708be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcf708bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ec9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ec94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ec94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcf708ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (538 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd91816eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd91813e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd9181762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75ff733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75ff78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75ff733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75ff71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd917acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd917aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd917918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd91440e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd91440b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75ff71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75ff71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75ff71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd91440a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (539 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %cmp = icmp eq <8 x i8> %2, %3
# |   %sext = sext <8 x i1> %cmp to <8 x i8>
# |   store <8 x i8> %sext, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i32>
# |   store <16 x i32> %sext, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <8 x i64> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i64>
# |   store <8 x i64> %sext, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x 
# | ...
# `---data was truncated (10240/78785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000556f5324eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f5324be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f5324f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37c9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37c90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37c9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37c9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f531e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f531e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f531c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f52e78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f52e78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37c9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37c90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37c90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f52e78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (540 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056467dcb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056467dcb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056467dcba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67e4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67e458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67e4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67e451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056467dc4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056467dc4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056467dc348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056467d8e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056467d8e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67e451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67e451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67e451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056467d8e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (541 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvt_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvt_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_u32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_s32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, p
# | ...
# `---data was truncated (10240/39207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556d4434deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d4434ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d4434e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95e6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95e6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95e6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95e6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d442e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d442e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d442c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d43f77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d43f77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95e6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95e6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95e6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d43f77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (542 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad84802eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad847ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad8480362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd952133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd95218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd952133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd95211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad84798bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad84798a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad8477d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad8442ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad8442cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd95211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd95211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd95211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad8442ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, alig
# | ...
# `---data was truncated (10240/26754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564746ae5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564746ae2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564746ae662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b3f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b3f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b3f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b3f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564746a7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564746a7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564746a608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056474670fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056474670fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b3f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b3f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b3f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056474670fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (544 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564aa0c85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564aa0c82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564aa0c8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0af3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0af358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0af3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0af351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aa0c1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aa0c1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aa0c008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aa08afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aa08afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0af351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0af351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0af351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aa08afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (545 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b59861eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b5985ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b5986262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d91333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d9138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d91333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d9131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b597f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b597f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b597dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b5948be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b5948bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d9131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d9131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d9131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b5948ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (546 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_u8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_u16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_u32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_s64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_u64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svreinterpret_f16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svreinterpret_bf16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svreinterpret_f32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x float>
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svreinterpret_f64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 t
# | ...
# `---data was truncated (10240/168193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x000055cdceccdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdceccae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdcecce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dedb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dedb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dedb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dedb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdcec63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdcec63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdcec488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdce8f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdce8f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dedb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dedb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dedb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdce8f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (547 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005576115b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576115b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576115b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb038933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb03898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb038933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb03891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557611549bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557611549a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055761152e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576111dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576111ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb03891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb03891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb03891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576111dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (548 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d057513eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d057510e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d05751462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb977133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb97718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb977133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb97711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0574a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0574a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d05748e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d05713de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d05713db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb97711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb97711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb97711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d05713da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (549 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32> %maske
# | ...
# `---data was truncated (10240/75397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bccf5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bccf5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bccf6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48ca933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48ca98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48ca933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48ca91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bccef5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bccef5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bcceda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bccb89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bccb89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48ca91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48ca91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48ca91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bccb89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (550 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp eq <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 2 x double> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @neq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ne <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @neq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @neq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @neq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @neq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   stor
# | ...
# `---data was truncated (10240/44453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000563702d18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563702d15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563702d1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcc0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcc018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcc0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcc011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563702caebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563702caea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563702c938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563702942e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563702942b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcc011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcc011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcc011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563702942a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (551 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e96632eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e9662fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e9663362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f894cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f894cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f894cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f894cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e965c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e965c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e965ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e9625ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e9625cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f894cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f894cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f894cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e9625ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (552 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b70dc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b70dbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b70dc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f92649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f926a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f92649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f92631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b70d57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b70d57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b70d3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b709ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b709ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f92632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f926330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f926330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b709eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (553 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcompact_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcompact_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ab4ab50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab4ab4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab4ab5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f649f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f649f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f649f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f649f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab4aae6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab4aae6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab4aacb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab4a77ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab4a77ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f649f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f649f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f649f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab4a77aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (554 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d00b6eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d00b6ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d00b6ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7826505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f782655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7826505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78264ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d00b684bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d00b684a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d00b6698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d00b318e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d00b318b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78264eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78264ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78264ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d00b318a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (555 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9dac44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9dac41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9dac4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52bb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52bb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52bb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52bb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9dabdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9dabdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9dabbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9da86ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9da86eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52bb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52bb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52bb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9da86ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (556 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svget2_f16(<vscale x 8 x half> %tuple.coerce0, <vscale x 8 x half> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %tuple.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svget2_f32(<vscale x 4 x float> %tuple.coerce0, <vscale x 4 x float> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %tuple.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | d
# | ...
# `---data was truncated (10240/14679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ae97e7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae97e79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae97e7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ea461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ea46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ea461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ea4603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae97e12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae97e12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae97df78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae97aa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae97aa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ea4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ea46050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ea46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae97aa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (557 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b598b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b598b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b598b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b09f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b09f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b09f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b09eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b59849bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b59849a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b5982e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b594dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b594ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b09eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b09eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b09eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b594dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (558 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055698f317eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055698f314e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055698f31862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8d9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8d9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8d9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8d9aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055698f2adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055698f2ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055698f2928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055698ef41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055698ef41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8d9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8d9aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8d9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055698ef41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (559 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/176535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b5ceb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b5ceb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b5ceb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc30d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc30d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc30d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc30d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b5ce4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b5ce4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b5ce308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b5cadfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b5cadfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc30d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc30d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc30d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b5cadfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (560 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   ret <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/58597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ccc50fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccc50f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccc50fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30a3305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30a335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30a3305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30a32ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccc5092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccc5092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccc50778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccc4d26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccc4d26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30a32eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30a32ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30a32ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccc4d26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (561 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8>, <vscale x 8 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 8 x i16> %3 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %6, <vscale x 8 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | e
# | ...
# `---data was truncated (10240/32866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005589d8f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589d8f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589d8f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4eac533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4eac58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4eac533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4eac51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589d8f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589d8f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589d8ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589d8ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589d8ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4eac51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4eac51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4eac51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589d8ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (562 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/13581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc0933aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc09337e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc0933b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc000533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc00058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc000533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc00051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc092d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc092d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc092b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc08f64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc08f64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc00051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc00051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc00051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc08f64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (563 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570fd2f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570fd2eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570fd2f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9a851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570fd287bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570fd287a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570fd26c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570fcf1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570fcf1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9a851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570fcf1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056148f490eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056148f48de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056148f49162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e47733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e4778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e47733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e4771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056148f426bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056148f426a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056148f40b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056148f0bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056148f0bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e4771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e4771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e4771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056148f0baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (565 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7c6282eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7c627fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7c628362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5dd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5dd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5dd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5dd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7c6218bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7c6218a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7c61fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7c5eace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7c5eacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5dd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5dd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5dd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7c5eaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (566 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e92b8d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e92b8d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e92b8d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f58f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f58f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f58f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f58f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e92b86cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e92b86ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e92b8518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e92b500e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e92b500b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f58f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f58f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f58f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e92b500a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (567 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4068c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4068c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4068c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2034249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20342a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2034249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2034231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b40685dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b40685da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4068428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4064f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4064f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2034232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20342330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20342330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4064f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (568 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b53a2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b53a28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b53a2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ec4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ec438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ec4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ec431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b539c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b539c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b539a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b53655e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b53655b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ec431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ec431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ec431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b53655a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (569 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055da3c4a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da3c4a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da3c4a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d4f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d4f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d4f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d4f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da3c43cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da3c43ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da3c4218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da3c0d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da3c0d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d4f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d4f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d4f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da3c0d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (570 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9162d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9162d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9162d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39d7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39d7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39d7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39d7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c91626abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c91626aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c91624f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c915efee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c915efeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39d7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39d7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39d7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c915efea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (571 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/71955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605be0d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605be0d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605be0d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d4c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d4c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d4c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d4c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605be069bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605be069a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605be04e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605bdcfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605bdcfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d4c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d4c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d4c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605bdcfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (572 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2088ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2088dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2088de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe653733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe65378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe653733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe65371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b208873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b208873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2088588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b208507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b208507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe65371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe65371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe65371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b208507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (573 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, 
# | ...
# `---data was truncated (10240/211231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056033bd76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056033bd73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056033bd7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74b8305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74b835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74b8305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74b82ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056033bd0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056033bd0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056033bcf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056033b9a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056033b9a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74b82eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74b82ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74b82ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056033b9a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (574 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556091ff1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556091feee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556091ff262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9f4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9f418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9f4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9f411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556091f87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556091f87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556091f6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556091c1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556091c1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9f411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9f411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9f411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556091c1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (575 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x float>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_f64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x double> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %zt, ptr %zt.addr
# | ...
# `---data was truncated (10240/12466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ac4ed0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac4ed09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac4ed0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5544533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f554458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5544533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f554451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac4eca2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac4eca2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac4ec878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac4e936e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac4e936b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f554451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f554451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f554451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac4e936a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (576 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df11444eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df11441e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df1144562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1390d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1390d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1390d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1390ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df113dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df113daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df113bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df1106ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df1106eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1390ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1390cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1390cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df1106ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (577 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055787d7b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055787d7b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055787d7b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8e1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8e1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8e1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8e1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055787d74ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055787d74ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055787d7338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055787d3e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055787d3e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8e1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8e1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8e1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055787d3e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (578 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 16
# |   %__s0_827 = alloca <4 x i32>, align 16
# |   %__s1_827 = alloca <16 x i8>, align 16
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp2 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_827, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1_827, align 16
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 16
# |   %4 = load <16 x i8>, ptr %__s1_827, align 16
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__
# | ...
# `---data was truncated (10240/29862) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055c2bb015eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2bb012e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2bb01662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba50533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba5058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba50533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba5051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2bafabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2bafaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2baf908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2bac3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2bac3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba5051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba5051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba5051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2bac3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (579 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bb6caaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bb6ca7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bb6cab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8742733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f874278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8742733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f874271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bb6c40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bb6c40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bb6c258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bb68d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bb68d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f874271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f874271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f874271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bb68d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (580 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/32702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055639a800eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055639a7fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055639a80162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa30de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa30de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa30de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa30de03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055639a796bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055639a796a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055639a77b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055639a42ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055639a42ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa30de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa30de050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa30de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055639a42aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (581 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571d24b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571d24b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571d24b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7e0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7e0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7e0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7e0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571d244ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571d244ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571d24338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571d20e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571d20e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7e0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7e0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7e0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571d20e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (582 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldff1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldff1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldff1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/64727) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055791db7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055791db7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055791db7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f312d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f312d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f312d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f312d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055791db14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055791db14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055791daf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055791d7a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055791d7a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f312d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f312d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f312d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055791d7a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (583 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e15bfa3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e15bfa0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e15bfa462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa081533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa08158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa081533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa08151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e15bf39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e15bf39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e15bf1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e15bbcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e15bbcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa08151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa08151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa08151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e15bbcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (584 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/33353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005629e0478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629e0475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629e047962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe66933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe6698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe66933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe6691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629e040ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629e040ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629e03f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629e00a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629e00a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe6691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe6691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe6691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629e00a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (585 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b203070eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b20306de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b20307162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa17e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa17e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa17e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa17e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b203006bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b203006a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b202feb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b202c9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b202c9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa17e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa17e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa17e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b202c9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (586 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635f273ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635f2739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635f273d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f288201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28820725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f288201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2882003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635f26d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635f26d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635f26b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635f2366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635f2366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2882004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28820050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28820050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635f2366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (587 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 0
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 1
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 3
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eb370dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb370dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb370e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9037f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9037f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9037f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9037f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb37075bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb37075a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb3705a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb36d09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb36d09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9037f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9037f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9037f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb36d09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (588 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055924409feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055924409ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592440a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa479b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa479b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa479b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa479b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559244035bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559244035a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055924401a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559243cc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559243cc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa479b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa479b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa479b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559243cc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (589 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <16 x i8> %2, %3
# |   store <16 x i8> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <8 x i16> %2, %3
# |   store <8 x i16> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <4 x i32> %2, %3
# |   store <4 x i32> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   store <1 x i64> %v2, ptr %v2.addr, align 8
# |   %0 = load <1 x i64>, ptr %v1.addr, align 8
# |   %1 = load <1 x i64>, ptr %v2.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <1 x i64> %2, %3
# |   store <1 x i64> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v1.addr = alloca <2 x i64>, align 16
# |   %v2.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %v1, ptr %v1.addr, align 16
# |   store <2 x i64> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x i64>, ptr %v1.addr, align 16
# |   %1 = load <2 x i64>, ptr %v2.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <2 x i64> %2, %3
# |   store <2 x i64> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/170019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x0000555fc75eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fc75ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fc75ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2324e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2324e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2324e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2324e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fc7584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fc7584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fc75698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fc7218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fc7218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2324e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2324e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2324e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fc7218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (590 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e32df8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e32df5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e32df962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0484c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0484c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0484c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0484c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e32d8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e32d8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e32d738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e32a22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e32a22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0484c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0484c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0484c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e32a22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (591 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f304552eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f30454fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f30455362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f917e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f917e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f917e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f917e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3044e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3044e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3044cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f30417ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f30417cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f917e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f917e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f917e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f30417ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (592 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562973958eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562973955e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056297395962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9861105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f986115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9861105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98610ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629738eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629738eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629738d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562973582e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562973582b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98610eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98610ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98610ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562973582a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (593 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to double
# |   %7 = bitcast <8 x i8> %4 to double
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %extract = extractelement <2 x double> %8, i32 0
# |   %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   %10 = bitcast double %9 to <1 x double>
# |   store <1 x double> %10, ptr %ref.tmp, align 8
# |   %11 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %11, ptr %__ret, align 8
# |   %12 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %12, ptr %tmp, align 8
# |   %13 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %13
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__s0, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1, align 16
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> <i32 1, i32 1>
# |   %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %9, ptr %ref.tmp, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %10, ptr %__ret, align 16
# |   %11 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %11, ptr %tmp, align 16
# |   %12 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load float, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %5, i32 1
# |   %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store float %6, ptr %ref.tmp, align 4
# |   %7 = load float, ptr %ref.tmp, align 4
# |   store float %7, ptr %__ret, align 4
# |   %8 = load float, ptr %__ret, align 4
# |   store float %8, ptr %tmp, align 4
# |   %9 = load float, ptr %tmp, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a00dd54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a00dd51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a00dd5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb942133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb94218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb942133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb94211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a00dceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a00dceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a00dccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a00d97ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a00d97eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb94211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb94211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb94211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a00d97ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (594 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056100e6c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056100e6c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056100e6c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe311c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe311ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe311c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe311c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056100e65bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056100e65ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056100e6408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056100e2efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056100e2efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe311c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe311c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe311c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056100e2efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (595 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d935f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d935f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d935f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa1b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa1b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa1b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa1b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d9358bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d9358ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d935708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d9321fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d9321fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa1b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa1b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa1b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d9321fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (596 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfe7aa7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfe7aa4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfe7aa862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f441ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f441ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f441ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f441ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfe7a3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfe7a3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfe7a228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfe76d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfe76d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f441ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f441ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f441ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfe76d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (597 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %5 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %5, ptr %__ret, align 8
# |   %6 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %6, ptr %tmp, align 8
# |   %7 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %9 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_39 = alloca <4 x half>, align 8
# |   %__s0_39 = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_39, align 8
# |   %1 = load <4 x half>, ptr %__s0_39, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_39, align 8
# |   %7 = load <4 x half>, ptr %__ret_39, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_20 = alloca <8 x half>, align 16
# |   %__s0_20 = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_20, align 8
# |   %1 = load <4 x half>, ptr %__s0_20, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_20, align 16
# |   %7 = load <8 x half>, ptr %__ret_20, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_432 = alloca <4 x half>, align 8
# |   %__s0_432 = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_432, align 16
# |   %1 = load <8 x half>, ptr %__s0_432, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_432, align 8
# |   %7 = load <4 x half>, ptr %__ret_432, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_408 = alloca <8 x half>, align 16
# |   %__s0_408 = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_408, align 16
# |   %1 = load <8 x half>, ptr %__s0_408, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_408, align 16
# |   %7 = load <8 x half>, ptr %__ret_408, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <4 x half>, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <4 x half> %vec, ptr %vec.addr, align 8
# |   %0 = load <4 x half>, ptr %vec.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x half> %1, i32 3
# |   store half %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <8 x half>, align 16
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <8 x half> %vec, ptr %vec.addr, align 16
# |   %0 = load <8 x half>, ptr %vec.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x half> %1, i32 7
# |   store half %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-s
# | ...
# `---data was truncated (10240/10414) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000555d03cddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d03cdae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d03cde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa62621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6262725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa62621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa626203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d03c73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d03c73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d03c588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d03907e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d03907b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa626204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6262050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6262050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d03907a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (598 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005643afc12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643afc0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643afc1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effdbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effdbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effdbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effdbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643afba8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643afba8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643afb8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643af83ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643af83cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effdbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effdbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effdbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643af83ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (599 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nx
# | ...
# `---data was truncated (10240/83629) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b664bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b664bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b664be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11bf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11bf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11bf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11bf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b66453bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b66453a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b664388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b660e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b660e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11bf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11bf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11bf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b660e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (600 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a2d98eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a2d98be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a2d98f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9be8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9be8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9be8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9be8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a2d924bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a2d924a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a2d9098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a2d5b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a2d5b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9be8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9be8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9be8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a2d5b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (601 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   
# | ...
# `---data was truncated (10240/169917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b41329ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b413299e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b41329d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0edaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0edaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0edaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0edaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b413232bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b413232a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4132178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b412ec6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b412ec6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0edaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0edaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0edaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b412ec6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (602 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i32>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store 
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005612f014feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612f014ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612f015062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2808333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f280838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2808333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f280831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612f00e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612f00e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612f00ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612efd79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612efd79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f280831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f280831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f280831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612efd79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (603 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr_z(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055f93aa1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f93aa18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f93aa1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff84b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff84b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff84b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff84b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f93a9b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f93a9b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f93a9968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f93a645e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f93a645b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff84b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff84b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff84b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f93a645a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (604 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556251206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556251203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055625120762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf1f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf1f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf1f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf1f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055625119cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055625119ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562511818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556250e30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556250e30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf1f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf1f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf1f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556250e30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c431eb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c431eaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c431eb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f97d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f97d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f97d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f97d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c431e47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c431e47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c431e2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c431adbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c431adbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f97d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f97d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f97d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c431adba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (606 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, pt
# | ...
# `---data was truncated (10240/73955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e756ebfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e756ebce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e756ec062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5190649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5190649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5190631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e756e55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e756e55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e756e3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e756ae9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e756ae9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5190632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51906330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e756ae9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (607 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056154f9bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056154f9b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056154f9bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe734e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe734ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe734e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe734e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056154f952bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056154f952a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056154f9378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056154f5e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056154f5e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe734e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe734e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe734e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056154f5e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (608 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dc15d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dc15d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dc15d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9912a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9912aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9912a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9912a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dc156ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dc156ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dc15538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dc1202e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dc1202b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9912a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9912a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9912a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dc1202a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (609 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c82ebd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c82ebd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c82ebd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fa7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fa718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fa7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fa711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c82eb6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c82eb6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c82eb538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c82e802e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c82e802b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fa711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fa711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fa711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c82e802a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559276004eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559276001e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055927600562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18a4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18a4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18a4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18a4e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559275f9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559275f9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559275f7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559275c2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559275c2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18a4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18a4e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18a4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559275c2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (611 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/18691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f696c3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f696c38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f696c3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa164b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa164b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa164b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa164b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f696bd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f696bd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f696bb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f696865e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f696865b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa164b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa164b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa164b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f696865a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (612 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 
# | ...
# `---data was truncated (10240/27063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd05986eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd05983e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd0598762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2af649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2af6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2af649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2af631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd0591cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd0591ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd059018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd055b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd055b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2af632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2af6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2af6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd055b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (613 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c83cb30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c83cb2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c83cb3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc13a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc13a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc13a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc13a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c83cac6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c83cac6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c83caab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c83c75ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c83c75ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc13a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc13a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc13a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c83c75aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (614 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ffabbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ffabbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ffabbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02c2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02c258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02c2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02c251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ffab54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ffab54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ffab398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ffa7e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ffa7e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02c251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02c251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02c251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ffa7e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (615 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.
# | ...
# `---data was truncated (10240/78690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578db818eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578db815e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578db81962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8fa01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8fa0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8fa01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8fa003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578db7aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578db7aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578db7938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578db442e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578db442b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8fa004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8fa0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8fa0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578db442a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (616 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   
# | ...
# `---data was truncated (10240/223129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a62068eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a62068be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a62068f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e2f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e2f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e2f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e2f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a620624bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a620624a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6206098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6202b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6202b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e2f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e2f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e2f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6202b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (617 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1, <vscale x 16 x i8> %val.coerce2, <vscale x 16 x i8> %val.coerce3) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %val.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %val.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %4 = load i32, ptr %base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale
# | ...
# `---data was truncated (10240/150970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558d263aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d263a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d263ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff46c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff46c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff46c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff46c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d26342bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d26342a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d263278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d25fd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d25fd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff46c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff46c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff46c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d25fd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (618 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpkhi_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056440c5efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056440c5ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056440c5f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6aa8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6aa88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6aa8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6aa8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056440c585bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056440c585a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056440c56a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056440c219e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056440c219b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6aa8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6aa88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6aa88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056440c219a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (619 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561608904eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561608901e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056160890562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7600733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f760078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7600733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f760071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056160889abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056160889aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056160887f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056160852ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056160852eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f760071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f760071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f760071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056160852ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (620 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611b80d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611b80d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611b80d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f005d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f005d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f005d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f005d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611b806bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611b806ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611b80508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611b7cffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611b7cffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f005d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f005d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f005d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611b7cffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (621 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee4d1beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee4d1bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee4d1bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a81933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a8198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a81933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a8191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee4d154bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee4d154a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee4d1398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee4cde8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee4cde8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a8191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a8191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a8191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee4cde8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (622 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdf8460eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdf845de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdf846162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aae333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aae38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aae333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aae31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdf83f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdf83f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdf83db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdf808ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdf808ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aae31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aae31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aae31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdf808aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (623 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/70971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4ec7ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4ec7fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4ec80062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe46541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4654725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe46541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe465403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4ec795bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4ec795a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4ec77a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4ec429e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4ec429b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe465404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4654050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4654050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4ec429a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (624 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1rq_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1rq_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1rq_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1rq_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557fb9fc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fb9fbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fb9fc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ede933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ede98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ede933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ede91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fb9f57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fb9f57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fb9f3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fb9bebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fb9bebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ede91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ede91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ede91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fb9beba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (625 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   %10 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %10)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/15164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c9286b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9286b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9286b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9f8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9f8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9f8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9f8eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c92864cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c92864ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9286318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9282e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9282e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9f8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9f8eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9f8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9282e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (626 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648532d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648532d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648532d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe61d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe61d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe61d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe61d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056485326cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056485326ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648532518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564852f00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564852f00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe61d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe61d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe61d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564852f00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (627 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc633c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc633c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc633c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ffb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ffb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ffb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ffb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc6335abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc6335aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc6333f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc62feee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc62feeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ffb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ffb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ffb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc62feea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (628 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562842f08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562842f05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562842f0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d7a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d7a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d7a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d7a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562842e9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562842e9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562842e838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562842b32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562842b32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d7a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d7a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d7a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562842b32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (629 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnt1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %b
# | ...
# `---data was truncated (10240/22231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055891c77aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055891c777e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055891c77b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4eb8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4eb898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4eb8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4eb891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055891c710bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055891c710a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055891c6f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055891c3a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055891c3a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4eb891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4eb891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4eb891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055891c3a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (630 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, ali
# | ...
# `---data was truncated (10240/280217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f42e34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f42e31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f42e3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a18f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a18f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a18f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a18f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f42dcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f42dcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f42daf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f42a5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f42a5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a18f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a18f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a18f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f42a5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (631 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16_1(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtmad_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtmad_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005638a4281eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638a427ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638a428262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f952f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f952f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f952f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f952f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638a4217bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638a4217a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638a41fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638a3eabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638a3eabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f952f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f952f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f952f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638a3eaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (632 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580fcd12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580fcd0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580fcd1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f872e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f872e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f872e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f872e803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580fcca8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580fcca8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580fcc8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580fc93ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580fc93cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f872e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f872e8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f872e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580fc93ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <
# | ...
# `---data was truncated (10240/84810) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055586f33ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055586f339e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055586f33d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6beaa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6beaa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6beaa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6beaa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055586f2d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055586f2d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055586f2b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055586ef66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055586ef66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6beaa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6beaa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6beaa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055586ef66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (634 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e28407eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e28404e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e2840862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe86c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe86c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe86c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe86c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e2839dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e2839da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e283828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e28031e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e28031b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe86c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe86c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe86c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e28031a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (635 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005590ce304eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590ce301e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590ce30562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf38733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf3878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf38733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf3871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590ce29abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590ce29aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590ce27f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590cdf2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590cdf2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf3871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf3871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf3871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590cdf2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (636 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d83ed59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d83ed56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d83ed5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2d0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2d04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2d0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2d0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d83ecefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d83ecefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d83ecd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d83e983e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d83e983b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2d0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2d04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2d04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d83e983a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (637 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fbd079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fbd076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fbd07a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde2201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde220725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde2201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde22003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fbd00fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fbd00fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fbcff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fbcca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fbcca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde22004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde220050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde220050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fbcca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (638 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecec59feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecec59ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecec5a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe23305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe2335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe23305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe232ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecec535bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecec535a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecec51a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecec1c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecec1c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe232eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe232ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe232ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecec1c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (639 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaa
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7c9946eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7c9943e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7c994762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb63733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb6378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb63733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb6371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7c98dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7c98dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7c98c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7c9570e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7c9570b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb6371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb6371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb6371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7c9570a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (640 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632553a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632553a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632553a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f782e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f782e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f782e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f782e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056325533bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056325533ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632553208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563254fcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563254fcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f782e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f782e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f782e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563254fcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (641 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a8467ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a84679e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a8467d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f532cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f532cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f532cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f532cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a84612bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a84612a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a845f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a842a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a842a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f532cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f532cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f532cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a842a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (642 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b6278b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6278afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6278b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb515849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5158a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb515849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb515831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b627848bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b627848a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b62782d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6274dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6274dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb515832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5158330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5158330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6274dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (643 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 im
# | ...
# `---data was truncated (10240/78242) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ec64a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ec649de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ec64a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9834249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98342a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9834249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9834231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ec6436bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ec6436a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ec641b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ec60cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ec60cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9834232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98342330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98342330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ec60caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (644 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1
# | ...
# `---data was truncated (10240/87183) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056271a0efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056271a0ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056271a0f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2309933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f230998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2309933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f230991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056271a085bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056271a085a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056271a06a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562719d19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562719d19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f230991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f230991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f230991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562719d19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (645 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568d3e0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568d3e09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568d3e0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed4301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed430725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed4301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed43003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568d3da2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568d3da2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568d3d878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568d3a36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568d3a36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed43004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed430050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed430050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568d3a36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (646 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055ffb6215eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffb6212e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffb621662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19ea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19ea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19ea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19ea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffb61abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffb61aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffb61908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffb5e3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffb5e3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19ea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19ea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19ea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffb5e3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (647 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrffr(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005611cf5f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611cf5f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611cf5f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe404d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe404d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe404d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe404d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611cf58bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611cf58ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611cf5708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611cf21fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611cf21fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe404d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe404d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe404d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611cf21fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (648 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect
# | ...
# `---data was truncated (10240/32932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eff4234eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eff4231e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eff423562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5a9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5a918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5a9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5a911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eff41cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eff41caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eff41af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eff3e5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eff3e5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5a911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5a911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5a911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eff3e5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (649 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a562028eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a562025e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a56202962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb629849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6298a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb629849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb629831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a561fbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a561fbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a561fa38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a561c52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a561c52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb629832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6298330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6298330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a561c52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (650 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fac78feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fac78ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fac79062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f530da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f530daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f530da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f530da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fac725bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fac725a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fac70a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fac3b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fac3b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f530da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f530da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f530da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fac3b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (651 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a93dfd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a93dfcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a93dfd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53b6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53b678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53b6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53b671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a93df68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a93df68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a93df4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a93dbfce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a93dbfcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53b671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53b671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53b671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a93dbfca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (652 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005621bbba3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621bbba0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621bbba462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb67533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb6758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb67533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb6751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621bbb39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621bbb39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621bbb1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621bb7cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621bb7cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb6751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb6751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb6751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621bb7cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (653 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563f2d14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563f2d11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563f2d1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb035305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb03535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb035305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0352ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563f2caabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563f2caaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563f2c8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563f293ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563f293eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0352eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0352ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0352ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563f293ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (654 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x half> %ma
# | ...
# `---data was truncated (10240/619127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575fd9cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575fd9cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575fd9ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f94933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f9498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f94933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f9491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575fd963bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575fd963a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575fd9488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575fd5f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575fd5f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f9491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f9491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f9491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575fd5f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (655 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563db647beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563db6478e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563db647c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff68649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff686a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff68649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff68631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563db6411bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563db6411a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563db63f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563db60a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563db60a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff68632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff686330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff686330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563db60a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4a40f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4a40f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4a40f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f185c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f185c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f185c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f185c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4a408dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4a408da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4a40728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4a3d21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4a3d21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f185c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f185c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f185c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4a3d21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (657 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5096c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5096bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5096c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62e7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62e74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62e7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62e7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f509658bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f509658a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f50963d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5092ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5092ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62e7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62e74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62e74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5092eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (658 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf8cfa3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf8cfa0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf8cfa462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69e9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69e9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69e9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69e9aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf8cf39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf8cf39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf8cf1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf8cbcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf8cbcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69e9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69e9aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69e9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf8cbcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (659 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056193ceb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056193ceb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056193ceb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21d7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21d7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21d7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21d7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056193ce4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056193ce4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056193ce328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056193cae1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056193cae1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21d7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21d7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21d7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056193cae1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (660 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b768f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b768f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b768f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eac449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eac4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eac449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eac431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b7688dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b7688da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b768728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b76521e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b76521b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2eac432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eac4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eac4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b76521a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (661 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dee2a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562dee2a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562dee2a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b8e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b8e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b8e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b8e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dee239bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562dee239a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562dee21e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562dedecde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562dedecdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b8e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b8e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b8e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dedecda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (662 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon   -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_790 = alloca <4 x i16>, align 8
# |   %__s0_790 = alloca <4 x i16>, align 8
# |   %__s1_790 = alloca <4 x i16>, align 8
# |   %__s2_790 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_790, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_790, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_790, align 16
# |   %3 = load <4 x i16>, ptr %__s0_790, align 8
# |   %4 = load <4 x i16>, ptr %__s1_790, align 8
# |   %5 = load <8 x i16>, ptr %__s2_790, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_790, align 8
# |   %16 = load <4 x i16>, ptr %__ret_790, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_788 = alloca <2 x i32>, align 8
# |   %__s0_788 = alloca <2 x i32>, align 8
# |   %__s1_788 = alloca <2 x i32>, align 8
# |   %__s2_788 = alloca <4 x i32>, align 16
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_788, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_788, align 8
# |   %2 = load <4 x i32>, ptr %v.addr, align 16
# |   store <4 x i32> %2, ptr %__s2_788, align 16
# |   %3 = load <2 x i32>, ptr %__s0_788, align 8
# |   %4 = load <2 x i32>, ptr %__s1_788, align 8
# |   %5 = load <4 x i32>, ptr %__s2_788, align 16
# |   store <4 x i32> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x i32>
# |   %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> <i32 3, i32 3>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %14 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %14, ptr %__ret.i, align 8
# |   %15 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %15, ptr %__ret_788, align 8
# |   %16 = load <2 x i32>, ptr %__ret_788, align 8
# |   store <2 x i32> %16, ptr %tmp1, align 8
# |   %17 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_786 = alloca <8 x i16>, align 16
# |   %__s0_786 = alloca <8 x i16>, align 16
# |   %__s1_786 = alloca <8 x i16>, align 16
# |   %__s2_786 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_786, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_786, align 16
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_786, align 16
# |   %3 = load <8 x i16>, ptr %__s0_786, align 16
# |   %4 = load <8 x i16>, ptr %__s1_786, align 16
# |   %5 = load <8 x i16>, ptr %__s2_786, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   store <8 x i16> %3, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %4, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %10, ptr %__p2.addr.i, align 16
# |   %11 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %14 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %15, ptr %__ret_786, align 16
# |   %16 = load <8 x i16>, ptr %__ret_786, align 16
# |   store <8 x i16> %16, ptr %tmp1, align 16
# |   %17 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_784 = alloca <4 x i32>, align 16
# |   %__s0_784 = alloca <4 x i32>, align 16
# |   %__s1_784 = alloca <4 x i32>, align 16
# |   %__s2_784 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <4
# | ...
# `---data was truncated (10240/50621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x0000556ac0d60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ac0d5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ac0d6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf0621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf062725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf0621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf06203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ac0cf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ac0cf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ac0cdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ac098ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ac098ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf06204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf062050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf062050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ac098aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (663 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i)
# |   store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i)
# |   store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane)
# |   store <4 x float> %vdot2, ptr %ref.tmp, align 16
# |   %7 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %7, ptr %__ret, align 16
# |   %8 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %8, ptr %tmp, align 16
# |   %9 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aa
# | ...
# `---data was truncated (10240/11256) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x00005586cc77deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586cc77ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586cc77e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cc7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cc78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cc7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cc7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586cc713bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586cc713a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586cc6f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586cc3a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586cc3a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cc7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cc78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cc78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586cc3a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (664 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>,
# | ...
# `---data was truncated (10240/159327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556f661d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f661d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f661d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84a341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84a34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84a341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84a3403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f6616cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f6616ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f661518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f65e00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f65e00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84a3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84a34050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84a34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f65e00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (665 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac1f9fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac1f9fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac1f9fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55bd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55bd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55bd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55bd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac1f993bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac1f993a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac1f9788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac1f627e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac1f627b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55bd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55bd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55bd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac1f627a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (666 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571b6758eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571b6755e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571b675962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa480d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa480d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa480d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa480ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571b66eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571b66eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571b66d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571b6382e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571b6382b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa480ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa480cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa480cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571b6382a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (667 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442f3ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056442f3e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056442f3ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7c7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7c778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7c7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7c771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056442f381bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056442f381a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056442f3668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056442f015e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056442f015b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7c771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7c771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7c771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056442f015a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (668 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x
# | ...
# `---data was truncated (10240/66009) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055af38fcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af38fcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af38fd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81c1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81c118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81c1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81c111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af38f65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af38f65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af38f4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af38bf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af38bf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81c111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81c111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81c111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af38bf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (669 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056370dea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056370de9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056370dea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b0c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b0c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b0c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b0c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056370de37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056370de37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056370de1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056370dacbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056370dacbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b0c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b0c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b0c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056370dacba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (670 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565056b4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565056b48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565056b4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b39849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b398a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b39849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b39831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565056ae1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565056ae1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565056ac68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565056775e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565056775b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b39832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b398330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b398330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565056775a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (671 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svmov_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a7b55b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7b55aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7b55b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d75c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d75ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d75c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d75c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7b5547bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7b5547a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7b552c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7b51dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7b51dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d75c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d75c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d75c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7b51dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/poly128.c (672 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   ret i128 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__s1 = alloca i128, align 16
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   store i128 %4, ptr %__s1, align 16
# |   %5 = load ptr, ptr %ptr.addr, align 8
# |   %add.ptr = getelementptr inbounds i128, ptr %5, i64 1
# |   %6 = load i128, ptr %__s1, align 16
# |   store i128 %6, ptr %add.ptr, align 16
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca i128, align 16
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load i64, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3)
# |   %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128
# |   store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16
# |   %4 = load i128, ptr %ref.tmp.i, align 16
# |   store i128 %4, ptr %__ret.i, align 16
# |   %5 = load i128, ptr %__ret.i, align 16
# |   ret i128 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
# | entry:
# |   %__p0.addr.i3 = alloca <2 x i64>, align 16
# |   %__ret.i4 = alloca <1 x i64>, align 8
# |   %__p0.addr.i1 = alloca <2 x i64>, align 16
# |   %__ret.i2 = alloca <1 x i64>, align 8
# |   %__p0.addr.i.i = alloca i64, align 8
# |   %__p1.addr.i.i = alloca i64, align 8
# |   %__ret.i.i = alloca i128, align 16
# |   %ref.tmp.i.i = alloca i128, align 16
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %ref.tmp1.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %2, ptr %__p0.addr.i3, align 16
# |   %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i4, align 8
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load i64, ptr %ref.tmp.i, align 8
# |   %7 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   store <2 x i64> %7, ptr %__p0.addr.i1, align 16
# |   %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8
# |   %10 = load <1 x i64>, ptr %__ret.i2, align 8
# |   store <1 x i64> %10, ptr %ref.tmp1.i, align 8
# |   %11 = load i64, ptr %ref.tmp1.i, align 8
# |   store i64 %6, ptr %__p0.addr.i.i, align 8
# |   store i64 %11, ptr %__p1.addr.i.i, align 8
# |   %12 = load i64, ptr %__p0.addr.i.i, align 8
# |   %13 = load i64, ptr %__p1.addr.i.i, align 8
# |   %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13)
# |   %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128
# |   store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16
# |   %14 = load i128, ptr %ref.tmp.i.i, align 16
# |   store i128 %14, ptr %__ret.i.i, align 16
# |   %15 = load i128, ptr %__ret.i.i, align 16
# |   store i128 %15, ptr %__ret.i, align 16
# |   %16 = load i128, ptr %__ret.i, align 16
# |   ret i128 %16
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.ad
# | ...
# `---data was truncated (10240/19795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005590e0c02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590e0bffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590e0c0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80dd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80dd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80dd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80dd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590e0b98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590e0b98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590e0b7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590e082ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590e082cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80dd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80dd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80dd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590e082ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (673 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005575940bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575940b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575940bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7df449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7df4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7df449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7df431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557594052bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557594052a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575940378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557593ce6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557593ce6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7df432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7df4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7df4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557593ce6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (674 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, 
# | ...
# `---data was truncated (10240/142319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b708e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b708e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b708e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5ecd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5ecd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5ecd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5ecd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b70879bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b70879a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b7085e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b7050de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b7050db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5ecd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5ecd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5ecd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7050da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (675 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/40883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be84529eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be84526e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be8452a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f536dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f536dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f536dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f536dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be844bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be844bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be844a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be84153e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be84153b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f536dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f536dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f536dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be84153a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (676 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fdcdc30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdcdc2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdcdc3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5eec133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5eec18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5eec133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5eec11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdcdbc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdcdbc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdcdbab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdcd85ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdcd85ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5eec11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5eec11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5eec11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdcd85aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (677 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c80e02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c80dffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c80e0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe47e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe47e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe47e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe47e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c80d98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c80d98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c80d7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c80a2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c80a2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe47e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe47e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe47e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c80a2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (678 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcreate_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %2, <vscale x 4 x bfloat> %1, i64 4)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %4, <vscale x 4 x bfloat> %1, i64 4)
# |   %6 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %5, <vscale x 4 x bfloat> %2, i64 8)
# |   %7 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %6, <vscale x 4 x bfloat> %3, i64 12)
# |   ret <vscale x 16 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v4.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v5.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v6.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v7.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x bfloat> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x bfloat> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x bfloat> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x bfloat> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x bfloat>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x bfloat>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x bfloat>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x bfloat>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %9 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %8, <vscale x 4 x bfloat> %1, i64 4)
# |   %10 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %9, <vscale x 4 x bfloat> %2, i64 8)
# |   %11 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %10, <vscale x 4 x bfloat> %3, i64 12)
# |   %12 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %11, <vscale x 4 x bfloat> %4, i64 16)
# |   %13 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %12, <vscale x 4 x bfloat> %5, i64 20)
# |   %14 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %13, <vscale x 4 x bfloat> %6, i64 24)
# |   %15 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %14, <vscale x 4 x bfloat> %7, i64 28)
# |   ret <vscale x 32 x bfloat> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %2, <vscale x 8 x bfloat> %1, i64 8)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %4, <vscale x 8 x bfloat> %1, i64 8)
# |   %6 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %5, <vscale x 8 x bfloat> %2, i64 16)
# |   %7 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %6, <vscale x 8 x bfloat> %3, i64 24)
# |   ret <vscale x 32 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m4_bf16m8(<vscale x 16 x bfloat> %v0, <vscale x 16 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %2, <vscale x 16 x bfloat> %1, i64 16)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vcreate_v_bf16mf4x2(<vscale x 1 x bfloat> %v0, <vscale x 1 x bfloat> %v1) #0 {
# | entry:
# |   %v0.add
# | ...
# `---data was truncated (10240/71275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c794938eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c794935e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c79493962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9901649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99016a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9901649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9901631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7948cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7948cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7948b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c794562e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c794562b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9901632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99016330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99016330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c794562a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (679 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f61281deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f61281ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f61281e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f875a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f875a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f875a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f875a803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6127b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6127b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6127988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f612447e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f612447b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f875a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f875a8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f875a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f612447a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (680 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a36aee1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a36aedee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a36aee262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc941333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc94138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc941333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc94131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a36ae77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a36ae77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a36ae5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a36ab0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a36ab0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc94131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc94131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc94131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a36ab0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (681 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1e0b91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1e0b8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1e0b9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff088305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff08835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff088305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0882ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1e0b27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1e0b27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1e0b0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1e07bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1e07bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0882eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0882ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0882ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1e07bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (682 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1dd59feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1dd59ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1dd5a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55c6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55c64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55c6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55c6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1dd535bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1dd535a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1dd51a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1dd1c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1dd1c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55c6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55c64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55c64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1dd1c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (683 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5bd093eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5bd090e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5bd09462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb65133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb6518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb65133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb6511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5bd029bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5bd029a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5bd00e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5bccbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5bccbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb6511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb6511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb6511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5bccbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (684 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i
# | ...
# `---data was truncated (10240/14325) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607e9aa2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607e9a9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607e9aa362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44ab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e9a38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607e9a38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607e9a1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607e96cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607e96ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e96cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (685 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_s32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_s64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_u32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_u64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556e771d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e771cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e771d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffafad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffafad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffafad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffafad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e77166bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e77166a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e7714b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e76dfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e76dfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffafad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffafad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffafad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e76dfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (686 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("ris
# | ...
# `---data was truncated (10240/26965) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca25929eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca25926e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca2592a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8094d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8094d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8094d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8094ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca258bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca258bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca258a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca25553e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca25553b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8094ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8094cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8094cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca25553a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (687 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056154b230eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056154b22de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056154b23162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb05d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb05d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb05d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb05d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056154b1c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056154b1c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056154b1ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056154ae5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056154ae5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb05d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb05d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb05d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056154ae5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (688 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32mf8(<vscale x 4 x float> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556c4b0f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c4b0f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c4b0fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3bd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3bd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3bd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3bd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c4b08fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c4b08fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c4b0748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c4ad23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c4ad23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3bd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3bd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3bd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c4ad23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (689 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c99f90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c99f8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c99f9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8cd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8cd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8cd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8cd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c99f26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c99f26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c99f0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c99bbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c99bbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8cd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8cd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8cd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c99bbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (690 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c06da27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c06da24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c06da2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd67f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd67f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd67f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd67f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c06d9bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c06d9bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c06d9a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c06d651e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c06d651b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd67f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd67f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd67f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c06d651a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (691 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16
# | ...
# `---data was truncated (10240/33616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6ea098eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6ea095e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6ea09962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe72f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe72f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe72f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe72f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6ea02ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6ea02ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6ea0138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6e9cc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6e9cc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe72f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe72f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe72f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6e9cc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (692 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a1901feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a1901ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a1902062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ce2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ce218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ce2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ce211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a18fb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a18fb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a18f9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a18c49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a18c49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ce211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ce211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ce211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a18c49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (693 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 
# | ...
# `---data was truncated (10240/97506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604cb832eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604cb82fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604cb83362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc203c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc203ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc203c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc203c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604cb7c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604cb7c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604cb7ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604cb45ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604cb45cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc203c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc203c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc203c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604cb45ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (694 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 2)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_laneq_f16(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half> %0, i32 4)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_laneq_f32(<vscale x 4 x float> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float> %0, i32 1)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_laneq_f64(<vscale x 2 x double> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double> %0, i32 1)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_laneq_bf16(<vscale x 8 x bfloat> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat> %0, i32 3)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 1)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ff176abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff176a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff176ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0aa01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0aa0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0aa01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0aa003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff17641bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff17641a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff176268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff172d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff172d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0aa004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0aa0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0aa0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff172d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (695 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ef0831eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ef082ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ef083262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa415705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa41575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa415705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4156ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ef07c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ef07c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ef07ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ef045be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ef045bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4156eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4156ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4156ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ef045ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (696 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577217c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577217c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577217ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca0ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca0aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca0ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca0ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772175fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055772175fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577217448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577213f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577213f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca0ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca0ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca0ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577213f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (697 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056460a6b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056460a6b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056460a6ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f486e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f486e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f486e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f486e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056460a64fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056460a64fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056460a6348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056460a2e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056460a2e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f486e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f486e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f486e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056460a2e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mfp8.c (698 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 {
# | entry:
# |   %mfp8.addr = alloca <1 x i8>, align 1
# |   %f1n = alloca [10 x <1 x i8>], align 1
# |   store <1 x i8> %mfp8, ptr %mfp8.addr, align 1
# |   %0 = load <1 x i8>, ptr %mfp8.addr, align 1
# |   %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   store <1 x i8> %0, ptr %arrayidx, align 1
# |   %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   %1 = load <1 x i8>, ptr %arrayidx1, align 1
# |   ret <1 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   ret <1 x i8> %mfp8ext
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   %v.addr = alloca <1 x i8>, align 1
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   store <1 x i8> %v, ptr %v.addr, align 1
# |   %0 = load <1 x i8>, ptr %v.addr, align 1
# |   %1 = load i32, ptr %i.addr, align 4
# |   %2 = load <16 x i8>, ptr %x.addr, align 16
# |   %3 = bitcast <1 x i8> %0 to i8
# |   %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1
# |   store <16 x i8> %vecins, ptr %x.addr, align 16
# |   %4 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# |  #0 0x000055875e88deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055875e88ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055875e88e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f690a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f690a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f690a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f690a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055875e823bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055875e823a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055875e8088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055875e4b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055875e4b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f690a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f690a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f690a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055875e4b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (699 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svuzp_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svuzp_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svuzp_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005630283b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630283b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630283b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9fc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9fc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9fc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9fc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056302834bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056302834ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630283308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563027fdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563027fdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9fc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9fc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9fc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563027fdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (700 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = add <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fadd <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = add <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fadd <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055904e32feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055904e32ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055904e33062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f819cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f819cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f819cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f819cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055904e2c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055904e2c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055904e2aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055904df59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055904df59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f819cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f819cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f819cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055904df59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (701 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d76609deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d76609ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d76609e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ad381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ad38725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ad381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ad3803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d766033bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d766033a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7660188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d765cc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d765cc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ad3804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ad38050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ad38050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d765cc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (702 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef2e64beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef2e648e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef2e64c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcff3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcff34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcff3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcff3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef2e5e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef2e5e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef2e5c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef2e275e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef2e275b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcff3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcff34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcff34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef2e275a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (703 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617ab26feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617ab26ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617ab27062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6bae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6baea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6bae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6bae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617ab205bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617ab205a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617ab1ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617aae99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617aae99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6bae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6bae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6bae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617aae99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (704 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmaxnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svmaxnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svmaxnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563a78674eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a78671e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a7867562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d70c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d70ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d70c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d70c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a7860abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a7860aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a785ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a7829ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a7829eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d70c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d70c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d70c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a7829ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (705 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_1() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 1)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_2() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 2)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_3() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 3)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_4() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 4)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_5() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 5)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_6() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 6)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_7() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 7)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 8)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_9() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 9)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_10() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_11() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_12() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 12)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_13() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 13)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_14() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 29)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_15() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 30)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_16() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 1)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 2)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c44bc09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c44bc06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c44bc0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef43333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef4338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef43333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef4331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c44bb9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c44bb9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c44bb848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c44b833e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c44b833b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef4331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef4331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef4331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c44b833a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (706 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561dba1aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561dba1a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561dba1ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29c0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29c02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29c0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29c0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dba142bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561dba142a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561dba1278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561db9dd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561db9dd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29c0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29c02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29c02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561db9dd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630ca422eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630ca41fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630ca42362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f487bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f487bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f487bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f487bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630ca3b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630ca3b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630ca39d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630ca04ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630ca04cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f487bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f487bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f487bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630ca04ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (708 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621c56f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621c56f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621c56f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbaed649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbaed6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbaed649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbaed631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621c568dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621c568da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621c56728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621c5321e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621c5321b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbaed632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbaed6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbaed6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621c5321a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (709 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/12644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b489812eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b48980fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b48981362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74b1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74b16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74b1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74b1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4897a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4897a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b48978d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b48943ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b48943cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74b1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74b16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74b16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b48943ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (710 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr
# | ...
# `---data was truncated (10240/27541) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac0e4feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac0e4fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac0e4ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f306f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f306f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f306f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f306f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac0e494bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac0e494a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac0e4798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac0e128e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac0e128b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f306f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f306f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f306f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac0e128a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (711 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clasta.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055ef9e65beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef9e658e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef9e65c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f053a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f053a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f053a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f053a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef9e5f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef9e5f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef9e5d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef9e285e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef9e285b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f053a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f053a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f053a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef9e285a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (712 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c6d3adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c6d3aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c6d3ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51db449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51db4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51db449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51db431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c6d343bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c6d343a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c6d3288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c6cfd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c6cfd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51db432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51db4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51db4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c6cfd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (713 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561878b97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561878b94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561878b9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44e7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44e738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44e7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44e731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561878b2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561878b2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561878b128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618787c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618787c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44e731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44e731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44e731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618787c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (714 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b3960feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b3960ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b3961062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6f3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6f338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6f3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6f331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b395a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b395a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b3958a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b39239e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b39239b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6f331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6f331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6f331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b39239a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (715 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a8f7daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a8f7d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a8f7db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6ce649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6ce6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6ce649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6ce631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a8f770bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a8f770a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a8f7558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a8f404e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a8f404b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6ce632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6ce6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6ce6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a8f404a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (716 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfddf7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfddf7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfddf7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c3d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c3d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c3d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c3d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfddf14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfddf14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfddef98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfddba8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfddba8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c3d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c3d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c3d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfddba8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/dup.c (717 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_u8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_u16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_n_f16(half noundef %op) #0 {
# | entry:
# |   %op.addr = alloca half, align 2
# |   store half %op, ptr %op.addr, align 2
# |   %0 = load half, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_n_f32(float noundef %op) #0 {
# | entry:
# |   %op.addr = alloca float, align 4
# |   store float %op, ptr %op.addr, align 4
# |   %0 = load float, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_n_f64(double noundef %op) #0 {
# | entry:
# |   %op.addr = alloca double, align 8
# |   store double %op, ptr %op.addr, align 8
# |   %0 = load double, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b8(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 16 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 16 x i1> %.splatinsert, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
# |   ret <vscale x 16 x i1> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b16(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 8 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 8 x i1> %.splatinsert, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b32(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 4 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 4 x i1> %.splatinsert, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b64(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 2 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 2 x i1> %.splatinsert, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_n_bf16(bfloat noundef %op) #0 {
# | entry:
# |   %op.addr = alloca bfloat, align 2
# |   store bfloat %op, ptr %op.addr, align 2
# |   %0 = load bfloat, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8_z(<vscale x 16 x i1> %pg, i8 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i8, align 1
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i8, ptr %op.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16_z(<vscale x 16 x i1> %pg, i16 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i16, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vsca
# | ...
# `---data was truncated (10240/49557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055a6a0a6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6a0a6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6a0a6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5039705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f503975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5039705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50396ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6a0a03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6a0a03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6a09e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6a0697e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6a0697b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50396eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50396ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50396ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6a0697a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (718 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aba1f1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aba1f1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aba1f1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69aee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69aee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69aee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69aee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aba1eb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aba1eb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aba1e998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aba1b48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aba1b48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69aee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69aee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69aee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aba1b48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (719 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557968dc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557968dc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557968dca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcd9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcd9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcd9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcd9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557968d5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557968d5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557968d448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579689f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579689f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcd9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcd9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcd9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579689f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (720 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b88206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b88203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b8820762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c37f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c37f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c37f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c37eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b8819cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b8819ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b881818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b87e30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b87e30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c37eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c37eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c37eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b87e30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (721 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclamp_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svclamp_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svclamp_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fe8ce41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe8ce3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe8ce4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac2cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac2cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac2cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac2cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe8cdd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe8cdd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe8cdbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe8ca6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe8ca6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac2cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac2cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac2cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe8ca6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (722 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %9 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 0
# |   %11 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 1
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 2
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 3
# |   %14 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 0
# |   %16 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 1
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 2
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 3
# |   %19 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, <vscale x 16 x i8> %10, <vscale x 16 x i8> %11, <vscale x 16 x i8> %12, <vscale x 16 x i8> %13, <vscale x 16 x i8> %15, <vscale x 16 x i8> %16, <vscale x 16 x i8> %17, <vscale x 16 x i8> %18)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %19
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn3.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn4.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %8 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %9 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %8, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   %zn3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %0, align 16
# |   %zn4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %1, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn3, ptr %zn3.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn4, ptr %zn4.addr, align 16
# |   %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 0
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 1
# |   %14 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 2
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 3
# |   %16 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 0
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 1
# |   %19 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 2
# |   %20 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 3
# |   %21 = call { <vscale x 16 x i8>, <vscale x 16 
# | ...
# `---data was truncated (10240/73319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x0000558163aa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558163a9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558163aa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cf1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cf155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cf1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cf14ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558163a37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558163a37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558163a1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581636cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581636cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cf14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cf14ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cf14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581636cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (723 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055891a255eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055891a252e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055891a25662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cf4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cf4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cf4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cf4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055891a1ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055891a1eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055891a1d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558919e7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558919e7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cf4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cf4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cf4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558919e7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (724 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f683d46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f683d43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f683d4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaa6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaa6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaa6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaa6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f683cdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f683cdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f683cc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f683970e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f683970b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaa6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaa6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaa6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f683970a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (725 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3)
# |   store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3)
# |   store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x2_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x2_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [2 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4)
# |   store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x2_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x2_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [2 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4)
# |   store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x3_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x3_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [3 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <8 x i8>, ptr %arrayidx4.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5)
# |   store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x3_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x3_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [3 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <16 x i8>, ptr %arrayidx4.i, align 16
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5)
# |   store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x4_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x4_t, align 8
# |   %b.a
# | ...
# `---data was truncated (10240/125901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563827c7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563827c7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563827c7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8698933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f869898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8698933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f869891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563827c14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563827c14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563827bf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638278a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638278a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f869891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f869891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f869891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638278a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (726 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/97514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603d4ca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603d4ca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603d4ca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04d6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04d6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04d6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04d6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603d4c3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603d4c3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603d4c208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603d48cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603d48cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04d6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04d6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04d6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603d48cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (727 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605d1116eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605d1113e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605d111762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ae9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ae98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ae9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ae9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605d10acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605d10aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605d10918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605d0d40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605d0d40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ae9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ae98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ae98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605d0d40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (728 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/78164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e9f726eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e9f723e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e9f72762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb78d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb78d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb78d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb78d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e9f6bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e9f6bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e9f6a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e9f350e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e9f350b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb78d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb78d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb78d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e9f350a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (729 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b0bcb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b0bcade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b0bcb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f08d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f08d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f08d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f08d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b0bc46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b0bc46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b0bc2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b0b8dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b0b8dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f08d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f08d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f08d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b0b8daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (730 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnf1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnf1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnf1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/22483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055583f646eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055583f643e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055583f64762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d5321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d532725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d5321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d53203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055583f5dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055583f5dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055583f5c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055583f270e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055583f270b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d53204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d532050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d532050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055583f270a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (731 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 
# | ...
# `---data was truncated (10240/97240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557806843eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557806840e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055780684462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff779049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7790a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff779049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff779031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578067d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578067d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578067be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055780646de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055780646db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff779032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7790330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7790330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055780646da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (732 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578638ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578638dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578638de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08e4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08e438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08e4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08e431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557863873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557863873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578638588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557863507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557863507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08e431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08e431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08e431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557863507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (733 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056282dd35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056282dd32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056282dd3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb346049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3460a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb346049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb346031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056282dccbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056282dccba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056282dcb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056282d95fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056282d95fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb346032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3460330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3460330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056282d95fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (734 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561761b31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561761b2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561761b3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71c0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71c0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71c0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71c0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561761ac7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561761ac7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561761aac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056176175be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056176175bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71c0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71c0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71c0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056176175ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (735 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559137f1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559137f19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559137f1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb34f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb34f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb34f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb34f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559137eb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559137eb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559137e978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559137b46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559137b46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb34f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb34f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb34f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559137b46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (736 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# | ...
# `---data was truncated (10240/170489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055745547deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055745547ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055745547e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0019133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f001918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0019133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f001911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557455413bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557455413a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574553f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574550a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574550a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f001911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f001911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f001911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574550a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (737 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000558a8fd84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a8fd81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a8fd8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5498a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5498aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5498a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5498a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a8fd1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a8fd1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a8fcff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a8f9aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a8f9aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5498a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5498a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5498a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a8f9aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (738 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/427567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653beafdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653beafae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653beafe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4182c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4182ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4182c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4182c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653bea93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653bea93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653bea788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653be727e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653be727b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4182c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4182c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4182c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653be727a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (739 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 
# | ...
# `---data was truncated (10240/117397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb46a91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb46a8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb46a9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9032649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90326a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9032649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9032631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb46a27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb46a27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb46a0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb466bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb466bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9032632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90326330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90326330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb466bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (740 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055913218ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559132189e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055913218d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9e5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9e558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9e5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9e551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559132122bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559132122a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591321078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559131db6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559131db6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9e551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9e551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9e551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559131db6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (741 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6)
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <4 x float> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load <4 x float>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %10, ptr %__ret.i, align 16
# |   %11 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %c.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6)
# |   store <2 x double> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %10, ptr %__ret.i, align 16
# |   %11 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x float>
# |   %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> <i32 1, i32 1>
# |   %fmla = bitcast <8 x i8> %4 to <2 x float>
# |   %fmla1 = bitcast <8 x i8> %3 to <2 x float>
# |   %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1)
# |   store <2 x float> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/80179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056001a5fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056001a5f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056001a5fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe061449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0614a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe061449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe061431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056001a592bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056001a592a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056001a5778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056001a226e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056001a226b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe061432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0614330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0614330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056001a226a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (742 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svminnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svminnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svminnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563238360eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056323835de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056323836162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6865133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f686518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6865133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f686511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632382f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632382f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632382db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563237f8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563237f8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f686511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f686511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f686511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563237f8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (743 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/51751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae15b8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae15b89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae15b8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa51cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa51cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa51cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa51cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae15b22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae15b22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae15b078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae157b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae157b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa51cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa51cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa51cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae157b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (744 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055654d946eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055654d943e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055654d94762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaeab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaeab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaeab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaeab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055654d8dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055654d8dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055654d8c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055654d570e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055654d570b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faaeab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaeab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaeab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055654d570a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (745 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b7ecefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b7ecece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b7ecf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd82c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd82ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd82c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd82c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b7ec85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b7ec85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b7ec6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b7e919e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b7e919b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd82c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd82c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd82c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b7e919a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (746 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_u8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_u16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_u32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_u64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_s8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_s16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_s32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_s64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbxq_f16(<vscale x 8 x half> %passthru, <vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbxq_f32(<vscale x 4 x float> %passthru, <vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.tbxq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/14102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556a45db8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a45db5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a45db962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dd4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dd4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dd4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dd4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a45d4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a45d4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a45d338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a459e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a459e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dd4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dd4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dd4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a459e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/aapcs-bitfield.c (747 of 27910)
******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-eabi"
# | 
# | %struct.st6 = type { i16, i8, i8 }
# | %struct.st7b = type { i8, [3 x i8], %struct.st7a }
# | %struct.st7a = type { i8, i8, [2 x i8] }
# | %struct.st11 = type <{ i8, i16, i8 }>
# | %struct.st13 = type <{ i8, i32 }>
# | %struct.st16 = type { i32, i16, i32, i16 }
# | %struct.st17 = type <{ i32, i8 }>
# | %struct.zero_bitfield = type { i8, i8, [2 x i8] }
# | %struct.zero_bitfield_ok = type { i16, i32 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st0_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st0_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st1_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.ashr = ashr i16 %bf.load, 10
# |   %conv = sext i16 %bf.ashr to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st1_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, 1023
# |   %bf.set = or i16 %bf.clear, 1024
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st2_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 9
# |   %bf.ashr = ashr i32 %bf.shl, 25
# |   %bf.cast = trunc i32 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st2_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -8323073
# |   %bf.set = or i32 %bf.clear, 65536
# |   store i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st3_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st3_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store volatile i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st4_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 2
# |   %bf.ashr = ashr i16 %bf.shl, 11
# |   %bf.cast = trunc i16 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -15873
# |   %bf.set = or i16 %bf.clear, 512
# |   store volatile i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -512
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st5_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 11
# |   %bf.ashr = ashr i32 %bf.shl, 27
# |   %bf.cast = trunc i32 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st5_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -2031617
# |   %bf.set = or i32 %bf.clear, 65536
# |   store volatile i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st6_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %x = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 4
# |   %bf.ashr = ashr i16 %bf.shl, 4
# |   %bf.cast = sext i16 %bf.ashr to i32
# |   store i32 %bf.cast, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   %2 = load volatile i8, ptr %b, align 2
# |   %conv = sext i8 %2 to i32
# |   %3 = load i32, ptr %x, align 4
# |   %add = add nsw i32 %3, %conv
# |   store i32 %add, ptr %x, align 4
# |   %4 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2
# |   %bf.load1 = load volatile i8, ptr %c, align 1
# |   %bf.shl2 = shl i8 %bf.load1, 3
# |   %bf.ashr3 = ashr i8 %bf.shl2, 3
# |   %bf.cast4 = sext i8 %bf.ashr3 to i32
# |   %5 = load i32, ptr %x, align 4
# |   %add5 = add nsw i32 %5, %bf.cast4
# |   store i32 %add5, ptr %x, align 4
# |   %6 = load i32, ptr %x, align 4
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st6_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -4096
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   store i8 2, ptr %b, align 2
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2
# |   %bf.load1 = load i8, ptr %c, align 1
# |   %bf.clear2 = and i8 %bf.load1, -32
# |   %bf.set3 = or i8 %bf.clear2, 3
# |   store i8 %bf.set3, ptr %c, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st7_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %r = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   %1 = load i8, ptr %x, align 4
# |   %conv = sext i8 %1 to i32
# |   store i32 %conv, ptr %r, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   %3 = load volatile i8, ptr %a, align 4
# |   %conv1 = sext i8 %3 to i32
# |   %4 = load i32, ptr %r, align 4
# |   %add = add nsw i32 %4, %conv1
# |   store i32 %add, ptr %r, align 4
# |   %5 = load ptr, ptr %m.addr, align 4
# |   %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.shl = shl i8 %bf.load, 3
# |   %bf.ashr = ashr i8 %bf.shl, 3
# |   %bf.cast = sext i8 %bf.ashr to i32
# |   %6 = load i32, ptr %r, align 4
# |   %add3 = add nsw i32 %6, %bf.cast
# |   store i32 %add3, ptr %r, align 4
# |   %7 = load i32, ptr %r, align 4
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st7_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   store i8 1, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   store volatile i8 2, ptr %a, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.clear = and i8 %bf.load, -32
# |   %bf.set = or i8 %bf.clear, 3
# |   store volatile i8 %bf.set, ptr %b, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   store i16 -1, ptr %0, align 4
# |   ret i32 65535
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @read_st9(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 4
# |   %bf.cast = sext i8 %bf.load to i32
# |   r
# | ...
# `---data was truncated (10240/24998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c19125ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c191259e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c19125d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85f0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85f038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85f0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85f031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1911f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1911f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1911d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c190e86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c190e86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85f031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85f031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85f031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c190e86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (748 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bf91b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bf91b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bf91b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9f9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9f90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9f9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9f9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bf914abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bf914aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bf912f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bf8ddee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bf8ddeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9f9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9f90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9f90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bf8ddea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (749 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648ce79feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648ce79ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648ce7a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f274f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f274f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f274f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f274f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648ce735bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648ce735a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648ce71a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648ce3c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648ce3c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f274f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f274f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f274f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648ce3c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (750 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055784ad24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055784ad21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055784ad2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a40333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a4038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a40333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a4031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055784acbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055784acbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055784ac9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055784a94ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055784a94eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a4031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a4031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a4031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055784a94ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (751 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556497714eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556497711e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055649771562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cd0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cd06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cd0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cd0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564976aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564976aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055649768f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055649733ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055649733eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cd0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cd06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cd06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055649733ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (752 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c296000eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c295ffde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c29600162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1d9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1d9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1d9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1d9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c295f96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c295f96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c295f7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c295c2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c295c2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1d9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1d9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1d9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c295c2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (753 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ecd275eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ecd272e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ecd27662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b24d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b24d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b24d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b24d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ecd20bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ecd20ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ecd1f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ecce9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ecce9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b24d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b24d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b24d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ecce9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (754 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d36e719eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d36e716e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d36e71a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22ea133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22ea18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22ea133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22ea11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d36e6afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d36e6afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d36e6948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d36e343e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d36e343b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22ea11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22ea11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22ea11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d36e343a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (755 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e52a23feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e52a23ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e52a24062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f143ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f143aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f143ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f143ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e52a1d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e52a1d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e52a1ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e529e69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e529e69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f143ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f143ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f143ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e529e69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (756 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f37454eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f37451e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f3745562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38e9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38e90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38e9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38e9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f373eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f373eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f373cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f3707ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f3707eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38e9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38e90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38e90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f3707ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (757 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, half noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca half, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store half %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load half, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync no
# | ...
# `---data was truncated (10240/10512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562532133eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562532130e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056253213462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd028a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd028aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd028a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd028a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625320c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625320c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625320ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562531d5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562531d5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd028a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd028a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd028a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562531d5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (758 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/67006) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560431813eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560431810e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056043181462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b3aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b3aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b3aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b3aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604317a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604317a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056043178e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056043143de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056043143db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b3aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b3aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b3aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056043143da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (759 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cdde7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cdde7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cdde8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcdb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcdb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcdb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcdb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cdde15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cdde15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cdddfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cddaa9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cddaa9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcdb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcdb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcdb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cddaa9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (760 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fd0024eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fd0021e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fd002562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e7bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e7bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e7bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e7bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fcffbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fcffbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fcff9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fcfc4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fcfc4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e7bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e7bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e7bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fcfc4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (761 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5fe8efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5fe8ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5fe8f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ecd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ecd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ecd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ecd6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5fe885bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5fe885a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5fe86a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5fe519e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5fe519b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ecd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ecd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ecd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5fe519a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (762 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba0f778eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba0f775e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba0f77962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effd9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effd96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effd9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effd9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba0f70ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba0f70ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba0f6f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba0f3a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba0f3a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effd9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effd96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effd96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba0f3a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (763 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be7b09ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be7b099e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be7b09d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e08849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e088a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e08849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e08831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be7b032bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be7b032a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be7b0178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be7acc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be7acc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e08832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e088330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e088330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be7acc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (764 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589b94fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589b94fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589b94fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fd8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fd8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fd8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fd8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589b9493bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589b9493a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589b94788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589b9127e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589b9127b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fd8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fd8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fd8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589b9127a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (765 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cb7c46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cb7c43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cb7c4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f8b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f8b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f8b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f8b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cb7bdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cb7bdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cb7bc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cb7870e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cb7870b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f8b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f8b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f8b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cb7870a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (766 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <4 x half>, align 8
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6)
# |   store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %9 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %9, ptr %__ret, align 8
# |   %10 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %10, ptr %tmp, align 8
# |   %11 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <16 x i8>, align 16
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   store <16 x i8> %2, ptr %__s2, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <16 x i8>, ptr %__s2, align 16
# |   %7 = load i64, ptr %__s4, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %8, ptr %__ret, align 8
# |   %9 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %9, ptr %tmp, align 8
# |   %10 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <16 x i8>, ptr %__s0, align 16
# |   %5 = load <16 x i8>, ptr %__s1, align 16
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3)
# |   store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16
# |   %9 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <
# | ...
# `---data was truncated (10240/24508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055e87c1feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e87c1fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e87c1ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa48f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa48f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa48f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa48f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e87c194bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e87c194a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e87c1798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e87be28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e87be28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa48f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa48f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa48f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e87be28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (767 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.
# | ...
# `---data was truncated (10240/11504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614bf924eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614bf921e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614bf92562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1542333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f154238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1542333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f154231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614bf8babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614bf8baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614bf89f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614bf54ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614bf54eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f154231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f154231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f154231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614bf54ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/72135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e1eb6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e1eb67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e1eb6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e8e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e8e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e8e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e8e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e1eb00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e1eb00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e1eae58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e1e794e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e1e794b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e8e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e8e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e8e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e1e794a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (769 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564989a40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564989a3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564989a4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe738733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe73878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe738733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe73871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649899d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649899d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649899bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056498966ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056498966ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe73871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe73871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe73871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056498966aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (770 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebbc30aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebbc307e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebbc30b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8eb4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8eb478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8eb4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8eb471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebbc2a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebbc2a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebbc2858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebbbf34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebbbf34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8eb471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8eb471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8eb471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebbbf34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (771 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/26520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9c8f2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9c8f27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9c8f2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac2d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac2d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac2d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac2d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9c8ec0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9c8ec0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9c8ea58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9c8b54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9c8b54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac2d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac2d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac2d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9c8b54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (772 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e028f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e028f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e028f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ba8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ba818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ba8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ba811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e0288bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e0288ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e028708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e0251fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e0251fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ba811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ba811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ba811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e0251fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (773 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d959dd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d959dcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d959dd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec27049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec270a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec27049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec27031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d959d67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d959d67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d959d4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9599fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9599fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec27032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec270330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec270330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9599fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (774 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %
# | ...
# `---data was truncated (10240/67150) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c2e7afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c2e7ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c2e7b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2112105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f211215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2112105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21120ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c2e745bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c2e745a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c2e72a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c2e3d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c2e3d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21120eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21120ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21120ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c2e3d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (775 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 
# | ...
# `---data was truncated (10240/12465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ba8e28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ba8e25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ba8e2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb13ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb13ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb13ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb13ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ba8dbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ba8dbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ba8da38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ba8a52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ba8a52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb13ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb13ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb13ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ba8a52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (776 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bee8faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bee8f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bee8fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd95c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd95c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd95c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd95c003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bee890bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bee890a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bee8758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bee524e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bee524b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd95c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd95c0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd95c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bee524a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (777 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563969bd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563969bd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563969bd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb10d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563969b6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563969b6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563969b508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639697ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639697ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639697ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (778 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d909377eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d909374e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d90937862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03fbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03fbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03fbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03fbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d90930dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d90930da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9092f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d908fa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d908fa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03fbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03fbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03fbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d908fa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (779 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg             | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vaddh = fadd half %2, %3
# |   store half %vaddh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vsubh = fsub half %2, %3
# |   store half %vsubh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmulh = fmul half %2, %3
# |   store half %vmulh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vdivh = fdiv half %2, %3
# |   store half %vdivh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3)
# |   store half %vmax, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3)
# |   store half %vmaxnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3)
# |   store half %vmin, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3)
# |   store half %vminnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabsh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vabs = call half @llvm.fabs.f16(half %1)
# |   store half %vabs, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.fabs.f16(half) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = all
# | ...
# `---data was truncated (10240/27802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a15a65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a15a62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a15a6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bd4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bd418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bd4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bd411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a159fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a159fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a159e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a1568fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a1568fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bd411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bd411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bd411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a1568fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (780 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055874e7c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055874e7c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055874e7c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe228849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2288a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe228849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe228831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055874e75cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055874e75ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055874e7418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055874e3f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055874e3f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe228832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2288330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2288330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055874e3f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (781 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055779648deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055779648ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055779648e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd718049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7180a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd718049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd718031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557796423bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557796423a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577964088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577960b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577960b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd718032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7180330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7180330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577960b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (782 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vas
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bfdc8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bfdc87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bfdc8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0153333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f015338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0153333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f015331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bfdc20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bfdc20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bfdc058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bfd8b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bfd8b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f015331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f015331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f015331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bfd8b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (783 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# | 
# | ...
# `---data was truncated (10240/31781) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c1b9392eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1b938fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1b939362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6679d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6679d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6679d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6679d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1b9328bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1b9328a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1b930d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1b8fbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1b8fbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6679d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6679d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6679d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1b8fbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (784 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559db188aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559db1887e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559db188b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa73db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa73db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa73db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa73db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559db1820bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559db1820a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559db18058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559db14b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559db14b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa73db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa73db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa73db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559db14b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (785 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/21295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c25bf5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c25bf5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c25bf6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc2a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc2a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc2a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc2a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c25bef5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c25bef5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c25beda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c25bb89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c25bb89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc2a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc2a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc2a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c25bb89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (786 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdcfc2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdcfc28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdcfc2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7db361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7db36725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7db361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7db3603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdcfbc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdcfbc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdcfba68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdcf855e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdcf855b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7db3604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7db36050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7db36050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdcf855a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (787 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005575a8a7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575a8a79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575a8a7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f842b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f842b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f842b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f842b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575a8a12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575a8a12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575a89f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575a86a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575a86a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f842b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f842b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f842b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575a86a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (788 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622f2522eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622f251fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622f252362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8fa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8fa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8fa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8fa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622f24b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622f24b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622f249d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622f214ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622f214cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8fa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8fa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8fa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622f214ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (789 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f29a33deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f29a33ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f29a33e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd3f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd3f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd3f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd3f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f29a2d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f29a2d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f29a2b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f299f67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f299f67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd3f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd3f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd3f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f299f67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (790 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055741b666eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055741b663e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055741b66762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7120a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7120aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7120a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7120a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055741b5fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055741b5fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055741b5e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055741b290e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055741b290b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7120a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7120a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7120a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055741b290a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (791 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056514cbd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056514cbcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056514cbd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98e1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98e138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98e1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98e131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056514cb68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056514cb68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056514cb4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056514c7fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056514c7fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98e131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98e131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98e131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056514c7fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (792 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639fcfafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639fcface85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639fcfb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7e2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7e235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7e2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7e22ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639fcf45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639fcf45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639fcf2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639fcbd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639fcbd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7e22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7e22ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7e22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639fcbd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (793 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566d9d3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566d9d37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566d9d3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64f481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64f48725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64f481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64f4803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566d9cd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566d9cd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566d9cb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566d9964e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566d9964b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64f4804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64f48050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64f48050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566d9964a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (794 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aface99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aface96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aface9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cf1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cf118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cf1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cf111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aface2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aface2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aface148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afacac3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afacac3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cf111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cf111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cf111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afacac3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (795 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c04db0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c04db09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c04db0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c37049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c37049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c37031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c04daa2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c04daa2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c04da878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c04d736e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c04d736b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c37032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c04d736a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (796 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d97c63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d97c60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d97c6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc79d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc79d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc79d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc79d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d97bf9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d97bf9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d97bde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d9788de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d9788db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc79d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc79d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc79d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d9788da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (797 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bae20beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bae208e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bae20c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4184849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41848a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4184849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4184831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bae1a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bae1a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bae1868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bade35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bade35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4184832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41848330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41848330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bade35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (798 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1480cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1480c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1480cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8547533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f854758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8547533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f854751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a148062bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a148062a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1480478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a147cf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a147cf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f854751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f854751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f854751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a147cf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (799 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, pt
# | ...
# `---data was truncated (10240/174721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563faf5e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563faf5e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563faf5e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87d3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87d3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87d3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87d3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563faf57ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563faf57ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563faf5638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563faf212e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563faf212b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87d3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87d3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87d3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563faf212a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (800 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557336577eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557336574e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055733657862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43eb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43eb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43eb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43eb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055733650dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055733650da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573364f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573361a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573361a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43eb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43eb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43eb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573361a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/15203) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4132aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4132a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4132ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fbee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fbee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fbee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fbee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f413242bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f413242a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4132278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f412ed6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f412ed6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fbee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fbee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fbee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f412ed6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (802 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9d7acceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9d7ac9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9d7acd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f298ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f298ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f298ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f298ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9d7a62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9d7a62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9d7a478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9d76f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9d76f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f298ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f298ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f298ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9d76f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (803 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562aba23eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562aba23be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562aba23f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff758f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff758f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff758f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff758f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aba1d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562aba1d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562aba1b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ab9e68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ab9e68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff758f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff758f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff758f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ab9e68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (804 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/28559) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055704504ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557045049e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055704504d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8584a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8584aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8584a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8584a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557044fe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557044fe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557044fc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557044c76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557044c76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8584a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8584a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8584a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557044c76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (805 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2f56cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2f56cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2f56ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb99d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb99d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb99d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb99d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2f5663bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2f5663a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2f56488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2f52f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2f52f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb99d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb99d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb99d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2f52f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (806 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc9c828eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc9c825e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc9c82962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39a9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39a978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39a9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39a971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc9c7bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc9c7bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc9c7a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc9c452e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc9c452b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39a971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39a971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39a971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc9c452a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (807 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <v
# | ...
# `---data was truncated (10240/157467) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cd9f47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cd9f44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cd9f4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed6d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed6d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed6d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed6d0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cd9eddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cd9edda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cd9ec28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cd9b71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cd9b71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed6d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed6d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed6d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cd9b71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (808 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563886be2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563886bdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563886be362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6eda533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6eda58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6eda533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6eda51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563886b78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563886b78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563886b5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056388680ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056388680cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6eda51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6eda51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6eda51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056388680ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (809 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647b179ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647b1799e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647b179d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22a441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22a44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22a441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22a4403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647b1732bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647b1732a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647b17178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647b13c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647b13c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22a4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22a44050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22a44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647b13c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-neon-vld.c (810 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float16x4x3_t, ptr %retval, align 8
# |   ret %struct.float16x4x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float16x4x4_t, ptr %retval, align 8
# |   ret %struct.float16x4x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float32x2x2_t, ptr %retval, align 8
# |   ret %struct.float32x2x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float32x2x3_t, ptr %retval, align 8
# |   ret %struct.float32x2x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float32x2x4_t, ptr %retval, align 8
# |   ret %struct.float32x2x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0)
# |   store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.poly16x4x2_t, ptr %retval, align 8
# |   ret %struct.poly16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16
# | ...
# `---data was truncated (10240/109928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609ed5efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609ed5ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609ed5f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb288f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb288f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb288f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb288f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609ed585bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609ed585a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609ed56a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609ed219e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609ed219b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb288f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb288f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb288f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609ed219a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (811 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b677c73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b677c70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b677c7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f83a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f83aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f83a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f83a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b677c09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b677c09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b677bee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b67789de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b67789db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f83a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f83a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f83a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b67789da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (812 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056313936deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056313936ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056313936e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ba649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ba6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ba649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ba631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563139303bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563139303a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631392e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563138f97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563138f97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23ba632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ba6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ba6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563138f97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (813 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_s8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_s16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_s32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_s64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_u8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_u16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_u32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_u64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svundef_f16() #0 {
# | entry:
# |   ret <vscale x 8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svundef_f32() #0 {
# | entry:
# |   ret <vscale x 4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svundef_f64() #0 {
# | entry:
# |   ret <vscale x 2 x double> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_mf8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svundef_bf16() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> undef
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005642b8629eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642b8626e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642b862a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5594f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5594f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5594f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5594eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642b85bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642b85bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642b85a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642b8253e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642b8253b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5594eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5594eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5594eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642b8253a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (814 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559032e5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559032e57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559032e5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67bb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67bb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67bb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67bb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559032df0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559032df0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559032dd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559032a84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559032a84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67bb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67bb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67bb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559032a84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (815 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608b6574eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608b6571e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608b657562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9da2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9da258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9da2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9da251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608b650abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608b650aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608b64ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608b619ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608b619eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9da251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9da251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9da251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608b619ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (816 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558ebb07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558ebb04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558ebb0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b92049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b92049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b92031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558eba9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558eba9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558eba828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558eb731e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558eb731b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b92032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b920330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558eb731a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (817 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d323fa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d323f9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d323fa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febb4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febb498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febb4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febb491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d323f36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d323f36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d323f1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d323bcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d323bcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febb491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febb491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febb491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d323bcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (818 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5a9f82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5a9f7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5a9f8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f682e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f682e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f682e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f682e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5a9f18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5a9f18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5a9efd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5a9bace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5a9bacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f682e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f682e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f682e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5a9baca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (819 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.add
# | ...
# `---data was truncated (10240/153913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f60ef0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f60eede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f60ef162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa995933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa99598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa995933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa99591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f60e86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f60e86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f60e6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f60b1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f60b1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa99591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa99591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa99591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f60b1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (820 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650c9f82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650c9f7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650c9f8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39bd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39bd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39bd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39bd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650c9f18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650c9f18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650c9efd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650c9bace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650c9bacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39bd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39bd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39bd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650c9baca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (821 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005587dd28eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587dd28be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587dd28f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77b4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77b48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77b4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77b4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587dd224bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587dd224a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587dd2098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587dceb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587dceb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77b4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77b48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77b48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587dceb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (822 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d83d83ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d83d839e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d83d83d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f2d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f2d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f2d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f2d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d83d7d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d83d7d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d83d7b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d83d466e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d83d466b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f2d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f2d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f2d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d83d466a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (823 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/424049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d81edd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d81edcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d81edd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5900e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5900ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5900e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5900e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d81ed68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d81ed68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d81ed4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d81e9fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d81e9fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5900e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5900e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5900e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d81e9fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (824 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ab5f21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ab5f1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ab5f2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feee4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feee44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feee4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feee4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ab5eb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ab5eb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ab5e9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ab5b4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ab5b4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feee4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feee44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feee44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ab5b4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (825 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558db9314eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558db9311e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558db931562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed3a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed3a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed3a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed3a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558db92aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558db92aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558db928f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558db8f3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558db8f3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed3a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed3a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed3a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558db8f3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (826 of 27910)
******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x half> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x float> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x double> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x bfloat> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005565502b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565502ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565502b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1dc105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1dc15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1dc105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1dc0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556550246bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556550246a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055655022b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055654fedae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055654fedab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1dc0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1dc0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1dc0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055654fedaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (827 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.abs.i32(i32 %0, i1 true)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.abs.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp sle i32 %0, %1
# |   %sle = zext i1 %2 to i32
# |   ret i32 %sle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp ule i32 %0, %1
# |   %sleu = zext i1 %2 to i32
# |   ret i32 %sleu
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = sext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exths = sext i16 %1 to i32
# |   ret i32 %exths
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = zext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exthz = zext i16 %1 to i32
# |   ret i32 %exthz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = sext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbs = sext i8 %1 to i32
# |   ret i32 %extbs
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = zext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbz = zext i8 %1 to i32
# |   ret i32 %extbz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xcvalu1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f027f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f027f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f027f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecb8e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecb8e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecb8e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecb8e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f0278cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f0278ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f027718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f02420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f02420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecb8e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecb8e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecb8e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f02420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (828 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3ccc14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3ccc11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3ccc1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa634305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa63435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa634305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6342ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3ccbaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3ccbaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3ccb8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3cc83ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3cc83eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6342eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6342ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6342ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3cc83ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (829 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 =
# | ...
# `---data was truncated (10240/10936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556840c8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556840c8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556840c8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a5ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a5ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a5ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a5ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556840c23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556840c23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556840c088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568408b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568408b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a5ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a5ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a5ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568408b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (830 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.add
# | ...
# `---data was truncated (10240/86739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055769f4f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055769f4f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055769f4f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99e001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99e00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99e001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99e0003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055769f48dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055769f48da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055769f4728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055769f121e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055769f121b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99e0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99e00050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99e00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055769f121a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (831 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056266cb10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056266cb0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056266cb1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7ba249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7ba2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7ba249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7ba231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056266caa6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056266caa6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056266ca8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056266c73ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056266c73ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7ba232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7ba2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7ba2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056266c73aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (832 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055711786eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055711786be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055711786f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2ce649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2ce6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2ce649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2ce631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557117804bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557117804a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571177e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557117498e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557117498b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2ce632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2ce6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2ce6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557117498a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (833 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056260f610eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056260f60de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056260f61162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb008533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb00858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb008533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb00851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056260f5a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056260f5a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056260f58b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056260f23ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056260f23ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb00851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb00851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb00851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056260f23aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (834 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2c34f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2c34efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2c34f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77bb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77bb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77bb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77bb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2c3488bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2c3488a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2c346d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2c311ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2c311cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77bb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77bb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77bb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2c311ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (835 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe601e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe601e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe601e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f0f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f0f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f0f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f0f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe6017ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe6017ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe601638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe5fe12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe5fe12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f0f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f0f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f0f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe5fe12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (836 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f14e11eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f14e11be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f14e11f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c4e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c4e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c4e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c4e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f14e0b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f14e0b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f14e0998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f14dd48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f14dd48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c4e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c4e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c4e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f14dd48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (837 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649705d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649705d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649705d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2254333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f225438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2254333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f225431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056497056ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056497056ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649705538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564970202e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564970202b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f225431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f225431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f225431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564970202a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (838 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cc5ccbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cc5cc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cc5ccc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f651c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f651c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f651c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f651c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cc5c61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cc5c61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cc5c468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cc58f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cc58f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f651c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f651c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f651c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cc58f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (839 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ee499a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee4999de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee499a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ba8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ba8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ba8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ba8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee49936bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee49936a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee4991b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee495cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee495cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ba8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ba8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ba8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee495caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (840 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c53ef62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c53ef5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c53ef6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57d2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c53eef8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c53eef8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c53eedd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c53eb8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c53eb8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c53eb8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (841 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4e4ecdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4e4ecae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4e4ece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd053733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd05378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd053733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd05371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4e4e63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4e4e63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4e4e488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4e4af7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4e4af7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd05371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd05371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd05371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4e4af7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/nor.c (842 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnor_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055defc773eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055defc770e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055defc77462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd59533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd59533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055defc709bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055defc709a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055defc6ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055defc39de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055defc39db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd5951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055defc39da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (843 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ce6f7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ce6f77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ce6f7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd72133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd7218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd72133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd7211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ce6f10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ce6f10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ce6ef58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ce6ba4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ce6ba4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd7211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd7211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd7211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ce6ba4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595e4a10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595e4a0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595e4a1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4ff41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4ff4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4ff41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4ff403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e49a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595e49a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595e498b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595e463ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595e463ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4ff404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4ff4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4ff4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e463aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (845 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df934ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df934e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df934ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb331133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb33118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb331133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb33111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df93481bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df93481a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df934668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df93115e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df93115b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb33111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb33111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb33111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df93115a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (846 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> 
# | ...
# `---data was truncated (10240/16951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591264d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591264cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591264d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0103e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0103e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0103e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0103e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559126466bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559126466a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055912644b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591260fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591260fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0103e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0103e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0103e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591260faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (847 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e45dd50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e45dd4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e45dd5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf8421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf842725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf8421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf84203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e45dce6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e45dce6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e45dccb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e45d97ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e45d97ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf84204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf842050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf842050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e45d97aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (848 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560207a44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560207a41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560207a4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa72cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa72cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa72cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa72cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602079dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602079daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602079bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056020766ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056020766eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa72cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa72cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa72cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056020766ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (849 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1
# |   store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %5, ptr %__ret, align 16
# |   %6 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %6, ptr %tmp, align 16
# |   %7 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0
# |   store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %5, ptr %__ret, align 8
# |   %6 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %6, ptr %tmp, align 8
# |   %7 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca 
# | ...
# `---data was truncated (10240/14230) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005560134d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560134d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560134da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd787333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd78738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd787333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd78731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055601346fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055601346fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560134548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556013103e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556013103b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd78731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd78731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd78731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556013103a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (850 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8
# | ...
# `---data was truncated (10240/24320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604fefd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604fefd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604fefd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0515933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f051598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0515933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f051591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604fef6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604fef6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604fef528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604fec01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604fec01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f051591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f051591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f051591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604fec01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (851 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556df3e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556df3e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556df3ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fc0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fc06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fc0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fc0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556df37fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556df37fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556df3648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556df013e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556df013b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fc0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fc06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fc06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556df013a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (852 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbf1d49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbf1d46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbf1d4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc84449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc844a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc84449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc84431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbf1cdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbf1cdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbf1cc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbf1973e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbf1973b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc84432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc844330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc844330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbf1973a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (853 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561291b1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561291b17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561291b1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb37c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb37c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb37c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb37c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561291ab0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561291ab0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561291a958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561291744e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561291744b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb37c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb37c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb37c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561291744a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (854 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec72b0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec72b0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec72b1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0354649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03546a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0354649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0354631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec72aa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec72aa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec72a8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec72739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec72739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0354632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03546330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03546330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec72739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (855 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 5)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 5)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 18)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 3)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 11)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 7)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 4)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 19)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 7)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 15)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 31)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = lshr <16 x i8> %0, splat (i8 1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = lshr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = lshr <4 x i32> %0, splat (i32 10)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   ret <16 x i8> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   ret <4 x i32> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinlin
# | ...
# `---data was truncated (10240/66359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f5e92ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f5e929e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f5e92d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc303d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc303d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc303d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc303ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f5e8c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f5e8c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f5e8a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f5e556e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f5e556b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc303ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc303cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc303cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f5e556a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (856 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/151253) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c89e980eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c89e97de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c89e98162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd70241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7024725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd70241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd702403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c89e916bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c89e916a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c89e8fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c89e5aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c89e5aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd702404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7024050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7024050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c89e5aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (857 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ececbc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ececbc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ececbca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ad3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ad32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ad3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ad3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ececb5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ececb5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ececb448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecec7f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecec7f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ad3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ad32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ad32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecec7f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (858 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556564d58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556564d55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556564d5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e08533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e0858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e08533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e0851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556564ceebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556564ceea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556564cd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556564982e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556564982b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e0851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e0851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e0851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556564982a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (859 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613859b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613859b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613859b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0931b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0931b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0931b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0931b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056138594abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056138594aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056138592f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613855dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613855deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0931b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0931b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0931b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613855dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (860 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559337c02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559337bffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559337c0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2095f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2095f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2095f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2095f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559337b98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559337b98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559337b7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055933782ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055933782cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2095f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2095f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2095f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055933782ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (861 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x 
# | ...
# `---data was truncated (10240/70013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603fc277eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603fc274e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603fc27862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06d3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06d3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06d3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06d3c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603fc20dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603fc20da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603fc1f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603fbea1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603fbea1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06d3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06d3c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06d3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603fbea1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (862 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16270deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c16270ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c16270e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe49fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe49fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe49fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe49fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1626a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1626a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1626888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c162337e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c162337b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe49fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe49fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe49fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c162337a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (863 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f81bd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f81bd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f81bd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f676e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f676e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f676e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f676e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f81b6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f81b6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f81b508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f817ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f817ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f676e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f676e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f676e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f817ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (864 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617f33ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617f33fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617f340062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e8161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e816725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e8161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e81603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617f3395bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617f3395a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617f337a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617f3029e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617f3029b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e81604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e816050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e816050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617f3029a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (865 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056309ca1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056309ca18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056309ca1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0820133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f082018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0820133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f082011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056309c9b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056309c9b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056309c9968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056309c645e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056309c645b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f082011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f082011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f082011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056309c645a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (866 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7ce281eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7ce27ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7ce28262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcba0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcba058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcba0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcba051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7ce217bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7ce217a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7ce1fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7cdeabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7cdeabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcba051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcba051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcba051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7cdeaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (867 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad6e04beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad6e048e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad6e04c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbc2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbc258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbc2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbc251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad6dfe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad6dfe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad6dfc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad6dc75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad6dc75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbc251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbc251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbc251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad6dc75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (868 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a35ad0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a35ad09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a35ad0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a35aca2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a35aca2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a35ac878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a35a936e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a35a936b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87c6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a35a936a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (869 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b19064eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b19061e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b1906562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6273533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f627358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6273533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f627351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b18ffabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b18ffaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b18fdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b18c8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b18c8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f627351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f627351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f627351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b18c8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (870 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bc0915eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bc0912e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bc091662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc61333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc6138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc61333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc6131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bc08abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bc08aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bc08908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bc053fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bc053fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc6131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc6131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc6131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bc053fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (871 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad9bba0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad9bb9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad9bba162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f330ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f330aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f330ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f330ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad9bb36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad9bb36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad9bb1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad9b7cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad9b7cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f330ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f330ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f330ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad9b7caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (872 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cfe0fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cfe0f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cfe0fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90dca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90dca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90dca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90dca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cfe092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cfe092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cfe0778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cfdd26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cfdd26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90dca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90dca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90dca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cfdd26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (873 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/205805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f66940deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f66940ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f66940e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb83a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb83a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb83a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb83a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6693a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6693a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6693888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f669037e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f669037b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb83a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb83a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb83a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f669037a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (874 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055899e2f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055899e2ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055899e2f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab6a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab6a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab6a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab6a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055899e286bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055899e286a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055899e26b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055899df1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055899df1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab6a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab6a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab6a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055899df1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (875 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e58b67beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e58b678e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e58b67c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28d1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28d118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28d1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28d111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e58b611bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e58b611a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e58b5f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e58b2a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e58b2a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28d111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28d111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28d111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e58b2a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (876 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f290d8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f290d8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f290d8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f364ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f364eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f364ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f364ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f290d23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f290d23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f290d088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2909b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2909b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f364ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f364ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f364ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2909b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (877 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e36fa74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e36fa71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e36fa7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f56c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f56ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f56c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f56c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e36fa0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e36fa0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e36f9ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e36f69ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e36f69eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f56c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f56c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f56c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e36f69ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (878 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed79875eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed79872e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed7987662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a5c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a5c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a5c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a5c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed7980bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed7980ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed797f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed7949fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed7949fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a5c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a5c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a5c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed7949fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (879 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_scatter_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16> %3, <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) #
# | ...
# `---data was truncated (10240/43213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005564ab5d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564ab5cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564ab5d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0013849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00138a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0013849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0013831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564ab568bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564ab568a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564ab54d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564ab1fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564ab1fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0013832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00138330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00138330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564ab1fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (880 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628c2faaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628c2fa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628c2fab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe422c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe422ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe422c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe422c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628c2f40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628c2f40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628c2f258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628c2bd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628c2bd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe422c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe422c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe422c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628c2bd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (881 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/246606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590e3f52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590e3f4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590e3f5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bb9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bb94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bb9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bb9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590e3ee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590e3ee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590e3ecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590e3b7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590e3b7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bb9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bb94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bb94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590e3b7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (882 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652c45c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652c45c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652c45c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cbdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cbdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cbdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cbdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652c455bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652c455ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652c45408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652c41efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652c41efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cbdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cbdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cbdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652c41efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (883 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloc
# | ...
# `---data was truncated (10240/27533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560331584eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560331581e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056033158562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f636fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f636fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f636fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f636fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056033151abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056033151aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603314ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603311aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603311aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f636fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f636fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f636fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603311aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (884 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c55b66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c55b63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c55b6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e18d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e18d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e18d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e18d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c55afcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c55afca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c55ae18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c55790e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c55790b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e18d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e18d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e18d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c55790a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (885 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/71947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da35a68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da35a65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da35a6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f942a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f942a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f942a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f942a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da359febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da359fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da359e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da35692e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da35692b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f942a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f942a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f942a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da35692a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (886 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/135111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8e12c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8e12c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8e12c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe464649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4646a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe464649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe464631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8e1259bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8e1259a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8e123e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8e0eede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8e0eedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe464632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4646330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4646330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8e0eeda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (887 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c5f34beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c5f348e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c5f34c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e00249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e002a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e00249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e00231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c5f2e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c5f2e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c5f2c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c5ef75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c5ef75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e00232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e002330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e002330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c5ef75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (888 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557151c86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557151c83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557151c8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7fcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7fcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7fcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7fcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557151c1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557151c1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557151c018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571518b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571518b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7fcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7fcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7fcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571518b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (889 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588ee1e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588ee1dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588ee1e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaade49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaadea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaade49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaade31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588ee176bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588ee176a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588ee15b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588ede0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588ede0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaade32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaade330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaade330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588ede0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (890 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc    -triple aarch64 -target-feature +neon -target-feature +bf16    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0_824.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8
# |   store <4 x i16> %1, ptr %__s0.i, align 8
# |   %2 = load <8 x i8>, ptr %__s0.i, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   %4 = zext <4 x i16> %3 to <4 x i32>
# |   %vshll_n.i = shl <4 x i32> %4, splat (i32 16)
# |   store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16
# |   %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %6, ptr %tmp.i, align 16
# |   %7 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret_824.i, align 16
# |   %9 = load <4 x float>, ptr %__ret_824.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   store <4 x bfloat> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8
# |   store <4 x bfloat> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %4, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %inactive.addr = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <4 x float>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = fptrunc <4 x float> %6 to <4 x bfloat>
# |   %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %8, ptr %ref.tmp.i, align 16
# |   %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca bfloat, align 2
# |   %ref.tmp.i = alloca bfloat, align 2
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   store bfloat %2, ptr %ref.tmp.i, align 2
# |   %3 = load bfloat, ptr %ref.tmp.i, align 2
# |   store bfloat %3, ptr %__ret.i, align 2
# |   %4 = load bfloat, ptr %__ret.i, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load 
# | ...
# `---data was truncated (10240/10974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c953668eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c953665e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c95366962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6da4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6da40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6da4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6da4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9535febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9535fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9535e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c953292e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c953292b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6da4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6da40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6da40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c953292a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (891 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b497121eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b49711ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b49712262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13bb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13bb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13bb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13bb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4970b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4970b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b49709c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b496d4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b496d4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13bb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13bb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13bb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b496d4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (892 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d8913deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d8913ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d8913e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedd4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedd44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedd4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedd4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d890d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d890d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d890b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d88d67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d88d67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedd4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedd44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedd44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d88d67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (893 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa8b206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa8b203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa8b20762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f5ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f5eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f5ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f5ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa8b19cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa8b19ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa8b1818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa8ae30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa8ae30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f5ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f5ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f5ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa8ae30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (894 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cefcc3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cefcc3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cefcc4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f91333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f9138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f91333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f9131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cefcbd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cefcbd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cefcbba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cefc869e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cefc869b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f9131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f9131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f9131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cefc869a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (895 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c0d041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c0d03ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c0d04262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8798d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8798d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8798d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8798ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c0cfd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c0cfd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c0cfbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c0cc6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c0cc6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8798ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8798cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8798cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c0cc6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (896 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f051721eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f05171ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f05172262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e5d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e5d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e5d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e5d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0516b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0516b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f05169c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f05134be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f05134bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e5d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e5d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e5d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f05134ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (897 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecc5140eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecc513de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecc514162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04ac449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04ac4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04ac449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04ac431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecc50d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecc50d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecc50bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecc4d6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecc4d6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04ac432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04ac4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04ac4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecc4d6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (898 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559a1b1a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a1b1a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a1b1a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8258849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82588a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8258849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8258831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a1b13cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a1b13ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a1b1218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a1add0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a1add0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8258832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82588330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82588330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a1add0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (899 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590f4014eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590f4011e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590f401562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20a0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20a02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20a0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20a0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590f3faabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590f3faaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590f3f8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590f3c3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590f3c3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20a0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20a02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20a02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590f3c3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (900 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558e931aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558e9317e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558e931b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb5d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb5d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb5d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb5d203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558e92b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558e92b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558e92958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558e8f44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558e8f44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb5d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb5d2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb5d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558e8f44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (901 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2d2b91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2d2b8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2d2b9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c00249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c002a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c00249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c00231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2d2b27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2d2b27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2d2b0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2d27bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2d27bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c00232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c002330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c002330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2d27bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (902 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/134744) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558233598eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558233595e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055823359962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e6581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e658725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e6581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e65803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055823352ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055823352ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582335138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582331c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582331c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e65804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e658050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e658050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582331c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (903 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615c3a89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615c3a86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615c3a8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb754533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb75458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb754533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb75451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615c3a1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615c3a1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615c3a048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615c36b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615c36b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb75451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb75451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb75451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615c36b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (904 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd95c6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd95c69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd95c6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9625049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96250a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9625049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9625031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd95c02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd95c02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd95be78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd95896e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd95896b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9625032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96250330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96250330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd95896a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (905 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055793939eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055793939be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055793939f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faafa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faafa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faafa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faafa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557939334bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557939334a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579393198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557938fc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557938fc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faafa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faafa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faafa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557938fc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (906 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i6
# | ...
# `---data was truncated (10240/182165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9db2d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9db2d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9db2d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5588d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5588d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5588d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5588ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9db26ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9db26ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9db2538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9daf02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9daf02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5588ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5588cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5588cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9daf02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (907 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056156fdd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056156fdd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056156fdd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f596ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f596aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f596ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f596ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056156fd6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056156fd6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056156fd528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056156fa01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056156fa01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f596ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f596ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f596ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056156fa01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (908 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e53cc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e53cc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e53cc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f553a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f553a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f553a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f553a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e53c5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e53c5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e53c3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e538eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e538eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f553a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f553a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f553a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e538eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (909 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x
# | ...
# `---data was truncated (10240/514173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558016be1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558016bdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558016be262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a69449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a694a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a69449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a69431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558016b77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558016b77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558016b5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055801680be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055801680bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a69432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a694330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a694330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055801680ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (910 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>
# | ...
# `---data was truncated (10240/22898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee1637aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee16377e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee1637b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67b4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67b458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67b4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67b451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee16310bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee16310a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee162f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee15fa4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee15fa4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67b451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67b451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67b451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee15fa4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/63169) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055938d32aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055938d327e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055938d32b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b10049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b100a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b10049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b10031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055938d2c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055938d2c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055938d2a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055938cf54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055938cf54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b10032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b100330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b100330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055938cf54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (912 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055690acfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055690acf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055690acfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd25e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd25e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd25e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd25e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055690ac91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055690ac91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055690ac768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055690a925e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055690a925b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd25e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd25e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd25e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055690a925a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (913 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, 
# | ...
# `---data was truncated (10240/26468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d45db95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d45db92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d45db9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cd0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cd0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cd0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cd0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d45db2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d45db2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d45db108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d45d7bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d45d7bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cd0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cd0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cd0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d45d7bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (914 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559518ab3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559518ab0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559518ab462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf44b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf44b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf44b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf44b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559518a49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559518a49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559518a2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595186dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595186ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf44b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf44b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf44b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595186dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (915 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005584b13f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584b13f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584b13f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbf2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbf295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbf2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbf28ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584b138dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584b138da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584b13728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584b1021e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584b1021b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbf28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbf28ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbf28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584b1021a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (916 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x h
# | ...
# `---data was truncated (10240/69487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562aac58aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562aac587e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562aac58b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa137049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa137049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa137031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aac520bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562aac520a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562aac5058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562aac1b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562aac1b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa137032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562aac1b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (917 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x 
# | ...
# `---data was truncated (10240/12463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb878ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb878dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb878de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e80b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e80b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e80b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e80b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb87873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb87873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb878588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb87507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb87507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e80b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e80b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e80b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb87507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (918 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso
# | ...
# `---data was truncated (10240/148012) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8cfb23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8cfb20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8cfb2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc061a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc061aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc061a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc061a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8cfab9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8cfab9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8cfa9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8cf74de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8cf74db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc061a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc061a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc061a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8cf74da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (919 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ed3a2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ed3a27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ed3a2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cd2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cd2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cd2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cd2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ed39c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ed39c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ed39a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ed3654e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ed3654b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cd2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cd2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cd2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ed3654a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (920 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# |  #0 0x0000560b58112eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b5810fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b5811362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b54533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b5458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b54533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b5451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b580a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b580a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b5808d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b57d3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b57d3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b5451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b5451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b5451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b57d3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (921 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1,
# | ...
# `---data was truncated (10240/223801) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560472200eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604721fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056047220162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58cdf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58cdf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58cdf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58cdeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560472196bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560472196a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056047217b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560471e2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560471e2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58cdeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58cdeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58cdeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560471e2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (922 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d8c8a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d8c89de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d8c8a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b17649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b176a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b17649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b17631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d8c836bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d8c836a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d8c81b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d8c4cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d8c4cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b17632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b176330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b176330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d8c4caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (923 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563aa8b54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563aa8b51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563aa8b5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b1dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b1dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b1dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b1dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563aa8aeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563aa8aeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563aa8acf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563aa877ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563aa877eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b1dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b1dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b1dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563aa877ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (924 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <2 x float>, align 8
# |   store <2 x float> %x, ptr %x.addr, align 8
# |   %0 = load <2 x float>, ptr %x.addr, align 8
# |   %1 = bitcast <2 x float> %0 to <8 x i8>
# |   ret <8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <8 x i8> %0 to <2 x float>
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <4 x float>, align 16
# |   store <4 x float> %x, ptr %x.addr, align 16
# |   %0 = load <4 x float>, ptr %x.addr, align 16
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i128, align 16
# |   store i128 %x, ptr %x.addr, align 16
# |   %0 = load i128, ptr %x.addr, align 16
# |   %1 = bitcast i128 %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to i128
# |   ret i128 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x0000556e3b350eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e3b34de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e3b35162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12e5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12e56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12e5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12e5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e3b2e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e3b2e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e3b2cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e3af7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e3af7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12e5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12e56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12e56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e3af7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (925 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c983862eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c98385fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c98386362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81fdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81fdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81fdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81fdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9837f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9837f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9837dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c98348ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c98348cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81fdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81fdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81fdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c98348ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (926 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d521b5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d521b5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d521b5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dc5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dc518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dc5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dc511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d521af4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d521af4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d521ad98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d521788e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d521788b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9dc511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dc511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dc511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d521788a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (927 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c778bf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c778bf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c778bf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50a3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50a3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50a3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50a3aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c778b89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c778b89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c778b6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c77881de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c77881db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50a3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50a3aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50a3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c77881da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (928 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055990c246eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055990c243e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055990c24762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43a8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43a8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43a8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43a8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055990c1dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055990c1dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055990c1c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055990be70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055990be70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43a8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43a8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43a8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055990be70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (929 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056045c9a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056045c99fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056045c9a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec97733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec9778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec97733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec9771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056045c938bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056045c938a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056045c91d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056045c5cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056045c5ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec9771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec9771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec9771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056045c5cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (930 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055556b740eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055556b73de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055556b74162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd48c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd48c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd48c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd48c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055556b6d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055556b6d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055556b6bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055556b36ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055556b36ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd48c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd48c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd48c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055556b36aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (931 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <4 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <4 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <4 x i16> %vbsl5.i to <4 x half>
# |   store <4 x half> %7, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbsl.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <8 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <8 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <8 x i16> %vbsl5.i to <8 x half>
# |   store <8 x half> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x half> %vzip.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x half> %vzip1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x half> %vzip.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x half> %vzip1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   store <4 x half> %vuzp.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   store <4 x half> %vuzp1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   store <8 x half> %vuzp.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   store <8 x half> %vuzp1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef 
# | ...
# `---data was truncated (10240/31986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f25778eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f25778be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f25778f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e36933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e3698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e36933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e3691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f257724bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f257724a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2577098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2573b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2573b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e3691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e3691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e3691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2573b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (932 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>
# | ...
# `---data was truncated (10240/43625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aac4ce8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aac4ce5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aac4ce962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6792133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f679218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6792133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f679211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aac4c7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aac4c7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aac4c638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aac4912e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aac4912b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f679211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f679211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f679211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aac4912a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (933 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x
# | ...
# `---data was truncated (10240/164783) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055998502feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055998502ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055998503062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48b1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48b10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48b1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48b1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559984fc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559984fc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559984faa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559984c59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559984c59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48b1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48b10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48b10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559984c59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (934 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559f7868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559f7865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559f786962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbee249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbee2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbee249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbee231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559f77febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559f77fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559f77e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559f7492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559f7492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbee232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbee2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbee2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559f7492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (935 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac6fca2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac6fc9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac6fca362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cba933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cba98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cba933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cba91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac6fc38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac6fc38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac6fc1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac6f8cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac6f8ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cba91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cba91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cba91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac6f8cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm64_vcopy.c (936 of 27910)
******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_336 = alloca <16 x i8>, align 16
# |   %__s0_336 = alloca <16 x i8>, align 16
# |   %__s2_336 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_336, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_336, align 16
# |   %2 = load <16 x i8>, ptr %__s2_336, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_336, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_336, align 16
# |   %13 = load <16 x i8>, ptr %__ret_336, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_328 = alloca <16 x i8>, align 16
# |   %__s0_328 = alloca <16 x i8>, align 16
# |   %__s2_328 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_328, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_328, align 16
# |   %2 = load <16 x i8>, ptr %__s2_328, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_328, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_328, align 16
# |   %13 = load <16 x i8>, ptr %__ret_328, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_346 = alloca <8 x i16>, align 16
# |   %__s0_346 = alloca <8 x i16>, align 16
# |   %__s2_346 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_346, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_346, align 16
# |   %2 = load <8 x i16>, ptr %__s2_346, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_346, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_346, align 16
# |   %13 = load <8 x i16>, ptr %__ret_346, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_334 = alloca <8 x i16>, align 16
# |   %__s0_334 = alloca <8 x i16>, align 16
# |   %__s2_334 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_334, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_334, align 16
# |   %2 = load <8 x i16>, ptr %__s2_334, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_334, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_334, align 16
# |   %13 = load <8 x i16>, ptr %__ret_334, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <4 x i32>, align 16
# |   %a2.addr = alloca <4 x i32>, align 16
# |   %__ret_340 = alloca <4 x i32>, align 16
# |   %__s0_340 = alloca <4 x i32>, align 16
# |   %__s2_340 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca i32, align 4
# |   %__ret1 = alloca i32, align 4
# |   %__s02 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp3 = alloca <4 x i32>, align 16
# |   %tmp4 = alloca <4 x i32>, align 16
# |   %tmp5 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a1, ptr %a1.addr, align 16
# |   store <4 x i32> %a2, ptr %a2.addr, align 16
# |   %0 = load <4 x i32>, ptr %a1.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_340, align 16
# |   %1 = load <4 x i32>, ptr %a2.addr, align 16
# |   store <4 x i32> %1, ptr %__s2_340, align 16
# |   %2 = load <4 x i32>, ptr %__s2_340, align 16
# |   store <4 x i32> %2, ptr %__s02, align 16
# |   %3 = load <4 x i32>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <4 x i32> %3, i32 3
# |   store i32 %vgetq_lane, ptr %ref.tmp, align 4
# |   %4 = load i32, ptr %ref.tmp, align 4
# |   store i32 %4, ptr %__ret1, align 4
# |   %5 = load i32, ptr %__ret1, align 4
# |   store i32 %5, ptr %tmp, align 4
# |   %6 = load i32, ptr %tmp, align 4
# |   store i32 %6, ptr %__s0, align 4
# |   %7 = load <4 x i32>
# | ...
# `---data was truncated (10240/22011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bd2bc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bd2bc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bd2bc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8278449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8278449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8278431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bd2b5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bd2b5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bd2b408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bd27efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bd27efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8278432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82784330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bd27efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffc4ba5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffc4ba2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffc4ba662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b1db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b1db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b1db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b1daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffc4b3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffc4b3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffc4b208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffc47cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffc47cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b1daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b1daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b1daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffc47cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (938 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_3_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e16f36eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e16f36be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e16f36f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb320249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3202a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb320249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb320231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e16f304bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e16f304a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e16f2e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e16ef98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e16ef98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb320232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3202330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3202330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e16ef98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (939 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619a1c44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619a1c41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619a1c4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05f4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05f40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05f4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05f4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619a1bdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619a1bdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619a1bbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619a186ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619a186eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05f4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05f40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05f40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619a186ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (940 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055634b051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055634b04ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055634b05262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9114d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9114d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9114d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9114d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055634afe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055634afe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055634afcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055634ac7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055634ac7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9114d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9114d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9114d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055634ac7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (941 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5480b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5480b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5480b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b86431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d548049bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d548049a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d54802e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d547cdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d547cddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b864330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d547cdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (942 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056452dfb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056452dfb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056452dfb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefabe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefabe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefabe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefabe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056452df4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056452df4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056452df328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056452dbe1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056452dbe1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefabe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefabe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefabe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056452dbe1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (943 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f8cdfaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8cdfa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8cdfab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb693d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb693d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb693d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb693d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8cdf40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8cdf40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8cdf258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8cdbd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8cdbd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb693d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb693d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb693d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8cdbd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (944 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564625a3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564625a38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564625a3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14c7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14c7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14c7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14c7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646259d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646259d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646259b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564625665e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564625665b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14c7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14c7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14c7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564625665a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (945 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %v
# | ...
# `---data was truncated (10240/110062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0c2c18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0c2c15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0c2c1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f750f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f750f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f750f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f750f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0c2baebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0c2baea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0c2b938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0c2842e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0c2842b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f750f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f750f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f750f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0c2842a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (946 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, al
# | ...
# `---data was truncated (10240/223137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563388c23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563388c20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563388c2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07f1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07f1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07f1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07f1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563388bb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563388bb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563388b9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056338884de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056338884db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07f1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07f1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07f1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056338884da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (947 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db3f8d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db3f8d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db3f8d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe768c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe768ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe768c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe768c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db3f86cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db3f86ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db3f8518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db3f500e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db3f500b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe768c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe768c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe768c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db3f500a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (948 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055725b99feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055725b99ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055725b9a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84b841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84b84725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84b841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84b8403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055725b935bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055725b935a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055725b91a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055725b5c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055725b5c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84b8404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84b84050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84b84050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055725b5c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (949 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c325ce0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c325cdde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c325ce162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc129933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc12998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc129933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc12991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c325c76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c325c76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c325c5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c32590ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c32590ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc12991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc12991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc12991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c32590aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (950 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64 immar
# | ...
# `---data was truncated (10240/14780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ef2d3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ef2d3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ef2d3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe44d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe44d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe44d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe44d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ef2cd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ef2cd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ef2cb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ef2967e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ef2967b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe44d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe44d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe44d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ef2967a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (951 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056376b101eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056376b0fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056376b10262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff593933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff59398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff593933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff59391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056376b097bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056376b097a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056376b07c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056376ad2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056376ad2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff59391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff59391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff59391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056376ad2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (952 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vsca
# | ...
# `---data was truncated (10240/14360) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588de0fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588de0fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588de0fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588de093bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588de093a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588de0788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588ddd27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588ddd27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42e2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588ddd27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (953 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645c638aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645c6387e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645c638b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6c7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6c7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6c7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6c7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645c6320bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645c6320a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645c63058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645c5fb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645c5fb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6c7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6c7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6c7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645c5fb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (954 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561066bf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561066befe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561066bf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58d6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58d60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58d6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58d6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561066b88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561066b88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561066b6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056106681ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056106681cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58d6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58d60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58d60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056106681ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (955 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e430dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e430dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e430e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe481d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe481d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe481d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe481d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e43075bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e43075a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e4305a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e42d09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e42d09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe481d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe481d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe481d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e42d09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (956 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc  -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <8 x i8>, ptr %__promote, align 8
# |   store <8 x i8> %1, ptr %__ret, align 8
# |   %2 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %2, ptr %tmp, align 8
# |   %3 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %.compoundliteral.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8>
# |   store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8
# |   store <8 x i8> %9, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %.compoundliteral.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> <i32 0, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> <i32 0, i32 1, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> <i32 0, i32 1, i32 2, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %9 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison
# | ...
# `---data was truncated (10240/101594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000564d61be4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d61be1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d61be562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f614b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f614b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f614b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f614b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d61b7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d61b7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d61b5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d6180ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d6180eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f614b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f614b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f614b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d6180ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (957 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557eaff3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557eaff3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557eaff3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f053d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f053d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f053d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f053d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557eafed4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557eafed4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557eafeb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557eafb68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557eafb68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f053d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f053d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f053d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557eafb68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (958 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align
# | ...
# `---data was truncated (10240/39627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9b8a02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9b89ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9b8a0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89dd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89dd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89dd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89dd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9b8998bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9b8998a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9b897d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9b862ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9b862cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89dd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89dd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89dd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9b862ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (959 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vf
# | ...
# `---data was truncated (10240/117019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db87760eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db8775de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db8776162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb480649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb480649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb480631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db876f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db876f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db876db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db8738ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db8738ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb480632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4806330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db8738aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (960 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %
# | ...
# `---data was truncated (10240/66087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597e3c27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597e3c24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597e3c2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a07533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a0758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a07533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a0751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597e3bbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597e3bbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597e3ba28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597e3851e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597e3851b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a0751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a0751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a0751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597e3851a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (961 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653c881eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653c881be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653c881f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecabe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecabe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecabe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecabe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653c87b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653c87b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653c87998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653c8448e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653c8448b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecabe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecabe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecabe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653c8448a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (962 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x
# | ...
# `---data was truncated (10240/84802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056430cc40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056430cc3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056430cc4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0565133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f056518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0565133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f056511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056430cbd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056430cbd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056430cbbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056430c86ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056430c86ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f056511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f056511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f056511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056430c86aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (963 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.ris
# | ...
# `---data was truncated (10240/18562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e1d0cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e1d0cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e1d0d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa79fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa79fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa79fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa79fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e1d065bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e1d065a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e1d04a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e1ccf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e1ccf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa79fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa79fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa79fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e1ccf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (964 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578a54feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578a54fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578a54ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0093333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f009338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0093333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f009331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578a5494bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578a5494a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578a54798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578a5128e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578a5128b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f009331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f009331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f009331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578a5128a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (965 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605cf999eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605cf996e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605cf99a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff320449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff320449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff320431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605cf92fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605cf92fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605cf9148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605cf5c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605cf5c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff320432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605cf5c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (966 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056537081aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565370817e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056537081b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f560b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f560b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f560b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f560b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653707b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653707b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653707958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565370444e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565370444b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f560b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f560b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f560b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565370444a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (967 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16
# | ...
# `---data was truncated (10240/93458) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6eb629eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6eb626e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6eb62a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b61333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b6138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b61333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b6131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6eb5bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6eb5bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6eb5a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6eb253e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6eb253b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b6131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b6131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b6131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6eb253a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (968 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eafe06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563eafe03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563eafe0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa85b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa85b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa85b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa85b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eafd9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563eafd9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563eafd818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563eafa30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563eafa30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa85b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa85b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa85b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eafa30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (969 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e8c369eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e8c366e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e8c36a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6896d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6896d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6896d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6896d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e8c2ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e8c2ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e8c2e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e8bf93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e8bf93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6896d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6896d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6896d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e8bf93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm64_vcreate.c (970 of 27910)
******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca i64, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store i64 %a1, ptr %a1.addr, align 8
# |   %0 = load i64, ptr %a1.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <2 x float>, ptr %__promote, align 8
# |   store <2 x float> %1, ptr %__ret, align 8
# |   %2 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %2, ptr %tmp, align 8
# |   %3 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606cbb81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606cbb7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606cbb8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febff431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606cbb17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606cbb17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606cbafc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606cb7abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606cb7abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febff4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606cb7aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (971 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f034783eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f034780e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f03478462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4311533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f431158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4311533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f431151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f034719bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f034719a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0346fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0343ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0343adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f431151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f431151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f431151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0343ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (972 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec0f585eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec0f582e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec0f58662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec30d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec30d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec30d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec30d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec0f51bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec0f51ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec0f5008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec0f1afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec0f1afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec30d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec30d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec30d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec0f1afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (973 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056516cb30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056516cb2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056516cb3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1b3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1b36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1b3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1b3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056516cac6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056516cac6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056516caab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056516c75ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056516c75ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1b3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1b36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1b36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056516c75aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-neon-fma.c (974 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf    -target-abi aapcs    -target-cpu cortex-a7    -mfloat-abi hard    -ffreestanding    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-none-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %accum.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %accum, ptr %accum.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %accum.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %accum.addr = alloca <4 x float>, align 8
# |   %lhs.addr = alloca <4 x float>, align 8
# |   %rhs.addr = alloca <4 x float>, align 8
# |   store <4 x float> %accum, ptr %accum.addr, align 8
# |   store <4 x float> %lhs, ptr %lhs.addr, align 8
# |   store <4 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x float>, ptr %accum.addr, align 8
# |   %1 = load <4 x float>, ptr %lhs.addr, align 8
# |   %2 = load <4 x float>, ptr %rhs.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store <4 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <2 x float>, align 8
# |   %__p1.addr.i.i = alloca <2 x float>, align 8
# |   %__p2.addr.i.i = alloca <2 x float>, align 8
# |   %__ret.i.i = alloca <2 x float>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <2 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <2 x float> %7, ptr %__p2.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %11 = bitcast <8 x i8> %8 to <2 x float>
# |   %12 = bitcast <8 x i8> %9 to <2 x float>
# |   %13 = bitcast <8 x i8> %10 to <2 x float>
# |   %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11)
# |   store <2 x float> %14, ptr %ref.tmp.i.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8
# |   store <2 x float> %15, ptr %__ret.i.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i.i, align 8
# |   store <2 x float> %16, ptr %__ret.i, align 8
# |   %17 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x float>, align 8
# |   %__p1.addr.i.i = alloca <4 x float>, align 8
# |   %__p2.addr.i.i = alloca <4 x float>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 8
# |   %ref.tmp.i.i = alloca <16 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 8
# |   %.compoundliteral.i = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <4 x float> %9, ptr %__p2.addr.i.i, align 8
# |   %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8
# |   %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8
# |   %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8
# |   %13 = bitcast <16 x i8> %10 to <4 x float>
# |   %14 = bitcast <16 x i8> %11 to <4 x float>
# |   %15 = bitcast <16 x i8> %12 to <4 x float>
# |   %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13)
# |   store <4 x float> %16, ptr %ref.tmp.i.i, align 8
# |   %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8
# |   store <4 x float> %17, ptr %__ret.i.i, align 8
# |   %18 = load <4 x float>, ptr %__ret.i.i, align 8
# |   store <4 x float> %18, ptr %__ret.i, align 8
# |   %19 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %19
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d78d847eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d78d844e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d78d84862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5a0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5a0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5a0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5a0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d78d7ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d78d7dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d78d7c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d78d471e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d78d471b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5a0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5a0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5a0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d78d471a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (975 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a00c00aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a00c007e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a00c00b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa668449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6684a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa668449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa668431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a00bfa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a00bfa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a00bf858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a00bc34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a00bc34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa668432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6684330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6684330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a00bc34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (976 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576fdb4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576fdb49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576fdb4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff22f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff22f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff22f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff22f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576fdae2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576fdae2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576fdac78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576fd776e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576fd776b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff22f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff22f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff22f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576fd776a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (977 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c  -check-prefix=RV32ZBKB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.brev8.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @zip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.zip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @unzip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.unzip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.brev8.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.zip.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.unzip.i32(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a5127feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a5127ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a5128062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa119133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa11918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa119133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa11911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a51215bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a51215a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a511fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a50ea9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a50ea9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa11911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa11911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa11911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a50ea9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (978 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562690bcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562690bc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562690bcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64cfe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64cfe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64cfe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64cfe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562690b62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562690b62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562690b478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626907f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626907f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64cfe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64cfe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64cfe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626907f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (979 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d911203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d911200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d91120462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6872249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68722a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6872249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6872231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d911199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d911199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d91117e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d910e2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d910e2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6872232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68722330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68722330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d910e2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (980 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | ...
# `---data was truncated (10240/12958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2d1162eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2d115fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2d116362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e7d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e7d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e7d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e7d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2d10f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2d10f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2d10dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2d0d8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2d0d8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e7d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e7d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e7d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2d0d8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (981 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfdd114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfdd111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfdd11562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43ec505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43ec55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43ec505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43ec4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfdd0aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfdd0aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfdd08f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfdcd3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfdcd3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43ec4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43ec4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43ec4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfdcd3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (982 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x bfloat> %1, i32 1
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x bfloat> %1, i32 7
# |   store bfloat %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_48 = alloca <4 x bfloat>, align 8
# |   %__s0_48 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_48, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_48, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_48, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_48, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_46 = alloca <8 x bfloat>, align 16
# |   %__s0_46 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_46, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_46, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_46, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_46, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_52 = alloca <4 x bfloat>, align 8
# |   %__s0_52 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_52, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_52, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_52, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_52, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_50 = alloca <8 x bfloat>, align 16
# |   %__s0_50 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_50, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_50, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_50, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_50, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %.compoundliteral.i = alloca <4 x bfloat>, align 8
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8
# |   store <4 x bfloat> %5, ptr %__ret.i, align 8
# |   %6 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %.compoundliteral.i = alloca <8 x bfloat>, align 16
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   %5 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4
# |   %6 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5
# |   %7 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6
# |   %8 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7
# |   store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/13833) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b4e10e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4e10e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4e10e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5bf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5bf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5bf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5bf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4e1079bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4e1079a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4e105e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4e0d0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4e0d0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5bf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5bf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5bf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4e0d0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (983 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/424041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce1d1d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce1d1d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce1d1d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f32533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f3258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f32533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f3251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce1d16bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce1d16ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce1d1508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce1cdffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce1cdffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f3251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f3251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f3251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce1cdffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (984 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612e4665eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612e4662e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612e466662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa16b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa16b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa16b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa16b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612e45fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612e45fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612e45e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612e428fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612e428fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa16b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa16b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa16b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612e428fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (985 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4dc6c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4dc6c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4dc6c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1705c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1705ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1705c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1705c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4dc65ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4dc65ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4dc6438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4dc2f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4dc2f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1705c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1705c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1705c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4dc2f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (986 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/33198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557305b8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557305b8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557305b8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59cce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59cce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59cce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59cce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557305b24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557305b24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557305b098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573057b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573057b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59cce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59cce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59cce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573057b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (987 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056551a2ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056551a2e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056551a2ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f316501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31650725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f316501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3165003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056551a281bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056551a281a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056551a2668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565519f15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565519f15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3165004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31650050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31650050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565519f15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (988 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056086e985eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056086e982e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056086e98662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6348133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f634818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6348133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f634811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056086e91bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056086e91ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056086e9008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056086e5afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056086e5afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f634811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f634811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f634811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056086e5afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (989 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <
# | ...
# `---data was truncated (10240/66998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628ecebceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628eceb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628ecebd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb61c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb61ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb61c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb61c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628ece52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628ece52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628ece378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628ecae6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628ecae6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb61c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb61c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb61c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628ecae6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (990 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/81507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c17fdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c17fd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c17fdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0a671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c17f70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c17f70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c17f558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c17c04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c17c04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0a671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c17c04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (991 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564456e78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564456e75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564456e7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd400a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd400aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd400a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd400a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564456e0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564456e0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564456df38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564456aa2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564456aa2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd400a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd400a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd400a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564456aa2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (992 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7de20eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7de20be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7de20f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa062f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa062f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa062f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa062f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7de1a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7de1a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7de1898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7dde38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7dde38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa062f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa062f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa062f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7dde38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (993 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e711fc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e711fc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e711fc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd2781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd278725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd2781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd27803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e711f5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e711f5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e711f438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e711bf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e711bf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd27804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd278050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd278050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e711bf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (994 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee87366eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee87363e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee8736762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb7b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb7b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb7b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb7b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee872fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee872fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee872e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee86f90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee86f90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb7b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb7b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb7b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee86f90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (995 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f1d052eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f1d04fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f1d05362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2558b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2558b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2558b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2558b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f1cfe8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f1cfe8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f1cfcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f1cc7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f1cc7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2558b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2558b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2558b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f1cc7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (996 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056542b1dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056542b1dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056542b1e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70bcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70bcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70bcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70bcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056542b175bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056542b175a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056542b15a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056542ae09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056542ae09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70bcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70bcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70bcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056542ae09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (997 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5f322ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5f3229e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5f322d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5f31c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5f31c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5f31a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5f2e56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5f2e56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5f2e56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (998 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsm
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a977114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a977111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a97711562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52e5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52e52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52e5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52e5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9770aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9770aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a97708f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a976d3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a976d3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52e5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52e52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52e52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a976d3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (999 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f9df2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f9df2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f9df2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f223a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f223a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f223a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f223a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f9dec3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f9dec3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f9dea88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f9db57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f9db57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f223a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f223a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f223a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f9db57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (1000 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a27aad5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a27aad2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a27aad662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8e541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8e54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8e541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8e5403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a27aa6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a27aa6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a27aa508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a27a6ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a27a6ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8e5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8e54050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8e54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a27a6ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (1001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055575c7c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055575c7c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055575c7c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a86333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a8638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a86333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a8631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055575c75bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055575c75ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055575c7408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055575c3efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055575c3efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a8631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a8631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a8631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055575c3efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (1002 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %isneg.i = icmp slt i32 %1, 0
# |   %not.i = xor i32 %1, -1
# |   %2 = select i1 %isneg.i, i32 %not.i, i32 %1
# |   %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false)
# |   %4 = sub nuw i32 %3, 1
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rev_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %2 = call i32 @llvm.bitreverse.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rd.addr.i, align 4
# |   %4 = load i32, ptr %__rs1.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rs1.addr.i, align 4
# |   %4 = load i32, ptr %__rd.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false)
# |   ret i32 %elt.abs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function At
# | ...
# `---data was truncated (10240/1228637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x000055f29c98eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f29c98be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f29c98f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5c8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5c8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5c8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5c8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f29c924bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f29c924a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f29c9098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f29c5b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f29c5b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5c8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5c8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5c8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f29c5b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/getset.c (1003 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <1 x i8>, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <1 x i8>, align 1
# |   %tmp = alloca <1 x i8>, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load <1 x i8>, ptr %ref.tmp, align 1
# |   store <1 x i8> %2, ptr %__ret, align 1
# |   %3 = load <1 x i8>, ptr %__ret, align 1
# |   store <1 x i8> %3, ptr %tmp, align 1
# |   %4 = load <1 x i8>, ptr %tmp, align 1
# |   ret <1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_847 = alloca half, align 2
# |   %__s0_847 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp1 = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %tmp2 = alloca half, align 2
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_847, align 8
# |   %1 = load <4 x i16>, ptr %__s0_847, align 8
# |   store <4 x i16> %1, ptr %__s0, align 8
# |   %2 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %2, i32 1
# |   store i16 %vget_lane, ptr %ref.tmp1, align 2
# |   %3 = load i16, ptr %ref.tmp1, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   store i16 %5, ptr %ref.tmp, align 2
# |   %6 = load half, ptr %ref.tmp, align 2
# |   store half %6, ptr %__ret_847, align 2
# |   %7 = load half, ptr %__ret_847, align 2
# |   store half %7, ptr %tmp2, align 2
# |   %8 = load half, ptr %tmp2, align 2
# |   %conv = fpext half %8 to float
# |   ret float %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %1, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %1, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align
# | ...
# `---data was truncated (10240/76998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055af2c657eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af2c654e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af2c65862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe82e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe82e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe82e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe82e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af2c5edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af2c5eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af2c5d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af2c281e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af2c281b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe82e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe82e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe82e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af2c281a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (1004 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> <i32 1>
# |   store <1 x double> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/20383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604db1e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604db1e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604db1e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe05ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe05eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe05ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe05ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604db17ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604db17ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604db1638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604dae12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604dae12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe05ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe05ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe05ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604dae12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (1005 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/176543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e96befeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e96bece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e96bf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f427c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f427c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f427c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f427c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e96b85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e96b85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e96b6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e96819e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e96819b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f427c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f427c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f427c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e96819a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (1006 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056335c906eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056335c903e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056335c90762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ead41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ead4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ead41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ead403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056335c89cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056335c89ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056335c8818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056335c530e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056335c530b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ead404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ead4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ead4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056335c530a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (1007 of 27910)
******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %class.Foo = type { i8 }
# | %class.HasTrivialDestructor = type { i8 }
# | %struct.Data = type { ptr }
# | %struct.HasNonTrivialCopyConstructor = type { i8 }
# | %struct.HasNonTrivialCopyConstructor2 = type { i8 }
# | %struct.LargeWithCopyConstructor = type { [32 x i8] }
# | %class.anon = type { i8 }
# | 
# | $_Z12TemplateFuncIiET_S0_ = comdat any
# | 
# | $_Z6Func10IiEii = comdat any
# | 
# | $_Z6Func12IiET_S0_ = comdat any
# | 
# | @pmf = global { i64, i64 } zeroinitializer, align 8
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %entry
# |   %1 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1)
# |   ret i32 %call
# | 
# | 2:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | if.else:                                          ; preds = %entry
# |   %3 = load i32, ptr %x.addr, align 4
# |   %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3)
# |   ret i32 %call1
# | 
# | 4:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %4, %2
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | declare noundef i32 @_Z3Bari(i32 noundef) #1
# | 
# | declare noundef i32 @_Z3Bazi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z3Bari(i32 noundef %0)
# |   %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call)
# |   ret i32 %call1
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.Foo, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local void @_Z5Func5v() #0 {
# | entry:
# |   musttail call void @_Z11ReturnsVoidv()
# |   ret void
# | 
# | 0:                                                ; No predecessors!
# |   ret void
# | }
# | 
# | declare void @_Z11ReturnsVoidv() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.HasTrivialDestructor, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 {
# | entry:
# |   %data.addr = alloca ptr, align 8
# |   store ptr %data, ptr %data.addr, align 8
# |   %0 = load ptr, ptr %data.addr, align 8
# |   %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %fptr, align 8
# |   %2 = load ptr, ptr %data.addr, align 8
# |   %call = musttail call noundef i32 %1(ptr noundef %2)
# |   ret i32 %call
# | 
# | 3:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat {
# | entry:
# |   %.addr = alloca i32, align 4
# |   store i32 %0, ptr %.addr, align 4
# |   ret i32 5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %t = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 {
# | entry:
# |   %x.ad
# | ...
# `---data was truncated (10240/18685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# |  #0 0x000055d8153b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8153aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8153b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33d7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33d7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33d7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33d7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d815347bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d815347a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d81532c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d814fdbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d814fdbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33d7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33d7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33d7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d814fdba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (1008 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557874faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557874f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557874fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbacf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbacf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbacf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbacf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555787490bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555787490a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557874758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555787124e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555787124b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbacf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbacf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbacf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555787124a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (1009 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, a
# | ...
# `---data was truncated (10240/98149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c504c49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c504c46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c504c4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76fcb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76fcb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76fcb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76fcaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c504bdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c504bdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c504bc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c504873e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c504873b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76fcaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76fcaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76fcaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c504873a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (1010 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a43e14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a43e11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a43e1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dbf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dbf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dbf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dbf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a43daabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a43daaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a43d8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a43a3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a43a3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dbf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dbf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dbf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a43a3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (1011 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577e5852eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577e584fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577e585362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6a1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6a118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6a1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6a111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577e57e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577e57e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577e57cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577e547ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577e547cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6a111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6a111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6a111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577e547ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (1012 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577ddd6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577ddd6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577ddd7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e42049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e42049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e42031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577ddd05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577ddd05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577ddcea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577dd999e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577dd999b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e42032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577dd999a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (1013 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fe5c64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fe5c61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fe5c6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa69f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa69f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa69f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa69f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fe5bfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fe5bfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fe5bdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fe588ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fe588eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa69f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa69f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa69f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fe588ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (1014 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f8fbc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f8fbc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f8fbc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3cea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3ceaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3cea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3cea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f8fb5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f8fb5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f8fb438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f8f7f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f8f7f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3cea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3cea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3cea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f8f7f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (1015 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7aba83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7aba80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7aba8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3265a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3265aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3265a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3265a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7aba19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7aba19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7ab9fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7ab6ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7ab6adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3265a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3265a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3265a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7ab6ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (1016 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562788b46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562788b43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562788b4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73a581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73a58725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73a581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73a5803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562788adcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562788adca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562788ac18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562788770e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562788770b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73a5804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73a58050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73a58050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562788770a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (1017 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb64cf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb64cede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb64cf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef88533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef8858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef88533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef8851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb64c86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb64c86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb64c6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb6491ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb6491ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef8851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef8851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef8851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb6491aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (1018 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef2_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef2_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef2_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef2_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ab28b4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab28b4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab28b5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2207d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2207d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2207d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2207d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab28ae5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab28ae5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab28aca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab28779e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab28779b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2207d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2207d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2207d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab28779a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (1019 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.
# | ...
# `---data was truncated (10240/164791) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564140884eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564140881e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056414088562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f884e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f884e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f884e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f884e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056414081abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056414081aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641407ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641404aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641404aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f884e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f884e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f884e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641404aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (1020 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b60bfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b60bfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b60bff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb44b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb44b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb44b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb44b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b60b94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b60b94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b60b798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b60828e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b60828b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb44b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb44b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb44b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b60828a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (1021 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e72238eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e72235e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e7223962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6bee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6beea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6bee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6bee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e721cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e721cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e721b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e71e62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e71e62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6bee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6bee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6bee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e71e62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (1022 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cea828ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cea8289e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cea828d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2953733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f295378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2953733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f295371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cea8222bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cea8222a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cea82078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cea7eb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cea7eb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f295371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f295371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f295371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cea7eb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (1023 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca68281eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca6827ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca6828262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46dda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca68217bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca68217a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca681fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca67eabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca67eabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46dda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca67eaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (1024 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f49912aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f499127e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f49912b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe487449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe487449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe487431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4990c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4990c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4990a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f498d54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f498d54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe487432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4874330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f498d54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (1025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056149a501eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056149a4fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056149a50262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2901933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f290198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2901933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f290191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056149a497bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056149a497a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056149a47c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056149a12be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056149a12bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f290191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f290191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f290191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056149a12ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (1026 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056054b850eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056054b84de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056054b85162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0899f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0899f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0899f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0899f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056054b7e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056054b7e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056054b7cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056054b47ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056054b47ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0899f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0899f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0899f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056054b47aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (1027 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d950c84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d950c81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d950c8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbeea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbeeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbeea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbeea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d950c1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d950c1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d950bff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9508aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9508aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbeea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbeea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbeea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9508aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (1028 of 27910)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1
# | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e32450eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e3244de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e3245162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f63e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f63ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f63e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f63e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e323e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e323e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e323cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e3207ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e3207ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f63e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f63e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f63e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e3207aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (1029 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563db9721eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563db971ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563db972262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb423333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb42338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb423333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb42331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563db96b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563db96b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563db969c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563db934be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563db934bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb42331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb42331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb42331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563db934ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (1030 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562003c39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562003c36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562003c3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1da533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1da58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1da533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1da51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562003bcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562003bcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562003bb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562003863e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562003863b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1da51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1da51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1da51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562003863a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (1031 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__p2.addr.i3 = alloca <4 x half>, align 8
# |   %__ret.i4 = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i3, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %13, ptr %__ret.i4, align 8
# |   %14 = load <4 x half>, ptr %__ret.i4, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__p1.addr.i2 = alloca <8 x half>, align 16
# |   %__p2.addr.i3 = alloca <8 x half>, align 16
# |   %__ret.i4 = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i1, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i3, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %13, ptr %__ret.i4, align 16
# |   %14 = load <8 x half>, ptr %__ret.i4, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <4 x half>, ptr %__s0, align 8
# |   %4 = load <4 x half>, ptr %__s1, align 8
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <4 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %9 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i, align 8
# |   store <4 x half> %4, ptr %__p1.addr.i, align 8
# |   store <4 x half> %9, ptr %__p2.addr.i, align 8
# |   %10 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %13 = bitcast <8 x i8> %10 to <4 x half>
# |   %14 = bitcast <8 x i8> %11 to <4 x half>
# |   %15 = bitcast <8 x i8> %12 to <4 x half>
# |   %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13)
# |   store <4 x half> %16, ptr %ref.tmp.i, align 8
# |   %17 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %17, ptr %__ret.i, align 8
# |   %18 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %18, ptr %__ret, align 8
# |   %19 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %19, ptr %tmp, align 8
# |   %20 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %20
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <8 x half>, ptr %__s0, align 16
# |   %4 = load <8 x half>, ptr %__s1, align 16
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <8 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3
# |   %9 = load half, ptr %__s2, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4
# |   %10 = load half, ptr %__s2, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5
# |   %11 = load half, ptr %__s2, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6
# |   %12 = load half, ptr %__s2, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %13 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i, align 16
# |   store <8 x half> %4, ptr %__p1.addr.i, align 16
# |   store <8 x half> %13, ptr %__p2.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %15 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %16 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %17 = bitcast <16 x i8> %14 to <8 x half>
# |   %18 = bitcast <16 x i8> %15 to <8 x half>
# |   %19 = bitcast <16 x i8> %16 to <8 x half>
# |   %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17)
# |   store <8 x half> %20, ptr %ref.tmp.i, align 16
# |   %21 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %21, ptr %__ret.i, align 16
# |   %22 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %22, ptr %__ret, align 16
# |   %23 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %23, ptr %tmp, align 16
# |   %24 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half
# | ...
# `---data was truncated (10240/31903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c7933d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7933d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7933d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47e7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47e7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47e7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47e7eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c79336bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c79336ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7933508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c792fffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c792fffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47e7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47e7eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47e7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c792fffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (1032 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <v
# | ...
# `---data was truncated (10240/98125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f81405deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f81405ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f81405e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab10849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab108a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab10849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab10831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f813ff3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f813ff3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f813fd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f813c87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f813c87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab10832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab108330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab108330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f813c87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (1033 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596cc3ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596cc3e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596cc3ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9273e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9273ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9273e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9273e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596cc381bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596cc381a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596cc3668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596cc015e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596cc015b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9273e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9273e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9273e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596cc015a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (1034 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66314) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587fe93eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587fe93be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587fe93f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4848d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4848d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4848d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4848d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587fe8d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587fe8d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587fe8b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587fe568e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587fe568b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4848d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4848d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4848d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587fe568a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (1035 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.a
# | ...
# `---data was truncated (10240/73947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594578fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594578f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594578fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95cfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95cfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95cfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95cfe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559457892bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559457892a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594578778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559457526e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559457526b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95cfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95cfe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95cfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559457526a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (1036 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x
# | ...
# `---data was truncated (10240/112817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c29d914eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c29d911e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c29d91562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe025933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe02598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe025933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe02591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c29d8aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c29d8aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c29d88f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c29d53ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c29d53eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe02591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe02591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe02591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c29d53ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (1037 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8d3551eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8d354ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8d355262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadb3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadb36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadb3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadb3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8d34e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8d34e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8d34cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8d317be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8d317bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadb3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadb36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadb36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8d317ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (1038 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b5b759eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b5b756e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b5b75a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdda61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdda6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdda61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdda603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b5b6efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b5b6efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b5b6d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b5b383e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b5b383b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdda604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdda6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdda6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b5b383a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (1039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6db306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6db303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6db30762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd6df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd6df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd6df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd6df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6db29cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6db29ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6db2818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6daf30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6daf30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd6df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd6df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd6df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6daf30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (1040 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570cb9e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570cb9e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570cb9e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66fbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66fbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66fbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66fbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570cb97dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570cb97da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570cb9628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570cb611e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570cb611b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66fbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66fbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66fbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570cb611a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (1041 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559817ca3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559817ca0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559817ca462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdadff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdadff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdadff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdadff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559817c39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559817c39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559817c1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598178cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598178cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdadff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdadff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdadff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598178cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (1042 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c550cd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c550ccfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c550cd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9410b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9410b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9410b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9410aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c550c68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c550c68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c550c4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5508fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5508fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9410aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9410aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9410aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5508fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (1043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560495cb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560495cb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560495cb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dd341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dd34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dd341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dd3403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560495c4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560495c4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560495c308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604958dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604958dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dd3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dd34050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dd34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604958dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (1044 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562738957eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562738954e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056273895862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9836b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9836b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9836b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9836aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627388edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627388eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627388d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562738581e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562738581b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9836aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9836aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9836aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562738581a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (1045 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fe5496eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fe5493e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fe549762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d3a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d3a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d3a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d3a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fe542cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fe542ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fe54118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fe50c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fe50c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d3a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d3a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d3a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fe50c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (1046 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a55de2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a55ddfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a55de362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f872f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f872f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f872f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f872f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a55d78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a55d78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a55d5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a55a0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a55a0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f872f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f872f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f872f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a55a0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (1047 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f07b95aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f07b957e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f07b95b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a0bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a0bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a0bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a0bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f07b8f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f07b8f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f07b8d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f07b584e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f07b584b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a0bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a0bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a0bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f07b584a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (1048 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5d2571eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5d256ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5d257262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5dac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5daca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5dac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5dac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5d2507bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5d2507a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5d24ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5d219be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5d219bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5dac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5dac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5dac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5d219ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (1049 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624b5604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624b5601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624b560562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce96d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce96d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce96d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce96d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624b559abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624b559aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624b557f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624b522ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624b522eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce96d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce96d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce96d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624b522ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (1050 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, a
# | ...
# `---data was truncated (10240/81515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056035d260eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056035d25de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056035d26162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8635f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8635f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8635f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8635f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056035d1f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056035d1f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056035d1db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056035ce8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056035ce8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8635f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8635f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8635f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056035ce8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (1051 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555ca24deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555ca24ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555ca24e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb62241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6224725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb62241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb622403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555ca1e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555ca1e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555ca1c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555c9e77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555c9e77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb622404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6224050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6224050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555c9e77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (1052 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5923cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5923cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5923ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa89121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8912725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa89121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa891203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b592363bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b592363a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5923488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b591ff7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b591ff7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa891204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8912050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8912050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b591ff7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (1053 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c698b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c698b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c698b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e42049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e42049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e42031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c6984abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c6984aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c6982f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c694dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c694deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e42032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c694dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (1054 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055744359eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055744359be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055744359f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcb8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcb8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcb8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcb8eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557443534bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557443534a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574435198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574431c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574431c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcb8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcb8eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcb8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574431c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (1055 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c043610eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c04360de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c04361162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f6621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f662725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f6621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f66203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0435a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0435a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c04358b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c04323ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c04323ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f66204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f662050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f662050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c04323aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (1056 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5bcaf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5bcaf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5bcaf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d1f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d1f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d1f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d1f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5bca8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5bca8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5bca718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5bc720e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5bc720b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d1f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d1f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d1f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5bc720a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (1057 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | ...
# `---data was truncated (10240/78234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579d2f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579d2f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579d2f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab05705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab0575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab05705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab056ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579d2f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579d2f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579d2ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579d2ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579d2ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab056eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab056ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab056ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579d2ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (1058 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0abfe1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0abfdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0abfe262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80f3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80f3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80f3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80f3c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0abf77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0abf77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0abf5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0abc0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0abc0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80f3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80f3c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80f3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0abc0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (1059 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i
# | ...
# `---data was truncated (10240/51295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4ff573eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4ff570e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4ff57462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9823733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f982378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9823733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f982371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4ff509bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4ff509a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4ff4ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4ff19de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4ff19db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f982371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f982371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f982371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4ff19da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (1060 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a7095eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a7095be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a7095f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd038d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd038d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd038d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd038d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a708f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a708f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a708d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a70588e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a70588b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd038d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd038d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd038d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a70588a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (1061 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cf95e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cf95e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cf95e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4e0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4e0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4e0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4e0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cf957bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cf957ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cf95608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cf920fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cf920fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4e0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4e0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4e0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cf920fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (1062 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ade1f7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ade1f79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ade1f7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35a7a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35a7a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35a7a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35a7a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ade1f12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ade1f12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ade1ef78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ade1ba6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ade1ba6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35a7a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35a7a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35a7a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ade1ba6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (1063 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561685f97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561685f94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561685f9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9670e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9670ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9670e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9670e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561685f2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561685f2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561685f128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561685bc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561685bc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9670e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9670e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9670e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561685bc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (1064 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd3e7c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd3e7bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd3e7c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb7c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb7c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb7c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb7c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd3e758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd3e758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd3e73d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd3e3ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd3e3ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb7c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb7c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb7c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd3e3eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (1065 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600ca55eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600ca55be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600ca55f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadaaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadaaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadaaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadaaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600ca4f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600ca4f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600ca4d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600ca188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600ca188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadaaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadaaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadaaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600ca188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (1066 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1abf99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1abf96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1abf9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c9a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c9a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c9a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c9a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1abf2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1abf2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1abf148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1abbc3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1abbc3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c9a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c9a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c9a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1abbc3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (1067 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056134daefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056134daece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056134daf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feff0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feff098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feff0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feff091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056134da85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056134da85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056134da6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056134d719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056134d719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feff091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feff091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feff091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056134d719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (1068 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/63749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055bfa67efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfa67ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfa67f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c3c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c3c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c3c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c3c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfa6785bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfa6785a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfa676a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfa6419e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfa6419b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c3c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c3c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c3c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfa6419a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (1069 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556385b1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556385b18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556385b1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52bd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52bd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52bd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52bd8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556385ab1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556385ab1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556385a968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556385745e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556385745b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52bd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52bd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52bd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556385745a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (1070 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/87191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ced1253eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ced1250e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ced125462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe42881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4288725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe42881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe428803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ced11e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ced11e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ced11ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ced0e7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ced0e7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe428804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4288050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4288050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ced0e7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (1071 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe57134eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe57131e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe5713562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2df2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2df258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2df2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2df251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe570cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe570caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe570af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe56d5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe56d5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2df251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2df251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2df251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe56d5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (1072 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x half> %0, i32 2
# |   ret half %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x float> %0, i32 3
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 4
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 0
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 10
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 3
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 3
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 1
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 1
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca <8 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load half, ptr %a.addr, align 2
# |   %2 = insertelement <8 x half> %0, half %1, i32 4
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load float, ptr %a.addr, align 4
# |   %2 = insertelement <4 x float> %0, float %1, i32 2
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 12
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 6
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 2
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 0
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 2
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 7
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 1
# |   ret <2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x00005628c6e67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628c6e64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628c6e6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7abd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7abd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7abd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7abced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628c6dfdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628c6dfda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628c6de28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628c6a91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628c6a91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7abceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7abcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7abcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628c6a91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (1073 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ffa327eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ffa324e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ffa32862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08da849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08da8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08da849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08da831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ffa2bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ffa2bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ffa2a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ff9f51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ff9f51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08da832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08da8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08da8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ff9f51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (1074 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cb9a6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cb9a67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cb9a6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d18d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d18d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d18d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d18d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cb9a00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cb9a00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cb99e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cb9694e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cb9694b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d18d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d18d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d18d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cb9694a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (1075 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %p0.addr = alloca <8 x half>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <8 x half> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <8 x half>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ccae0f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccae0ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccae0f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36c5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36c56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36c5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36c5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccae086bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccae086a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccae06b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccadd1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccadd1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36c5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36c56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36c56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccadd1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (1076 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e2c0abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e2c0a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e2c0ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86b3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86b3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86b3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86b3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e2c041bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e2c041a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e2c0268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e2bcd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e2bcd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86b3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86b3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86b3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e2bcd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (1077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056367529eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056367529be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056367529f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15cb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15cb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15cb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15cb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563675234bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563675234a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636752198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563674ec8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563674ec8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15cb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15cb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15cb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563674ec8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (1078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558181c37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558181c34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558181c3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8a8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8a86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8a8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8a8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558181bcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558181bcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558181bb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558181861e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558181861b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8a8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8a86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8a86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558181861a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (1079 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load
# | ...
# `---data was truncated (10240/410391) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c33b2a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c33b2a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c33b2a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5070c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5070ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5070c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5070c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c33b23bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c33b23ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c33b2208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c33aecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c33aecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5070c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5070c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5070c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c33aecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (1080 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc3cf2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc3cf28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc3cf2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a1d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a1d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a1d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a1d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc3cec1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc3cec1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc3cea68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc3cb55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc3cb55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a1d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a1d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a1d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc3cb55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (1081 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/116949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572319e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572319dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572319e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f495f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f495f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f495f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f495f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557231978bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557231978a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055723195d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055723160ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055723160cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f495f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f495f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f495f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055723160ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (1082 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f48de3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f48de38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f48de3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6511e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6511ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6511e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6511e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f48ddd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f48ddd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f48ddb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f48da65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f48da65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6511e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6511e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6511e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f48da65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (1083 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056188deb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056188deb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056188deba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ce721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ce72725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ce721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ce7203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056188de4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056188de4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056188de348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056188dae3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056188dae3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ce7204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ce72050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ce72050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056188dae3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (1084 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/427575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556b912ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556b9129e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556b912d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5637b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5637b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5637b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5637aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556b90c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556b90c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556b90a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556b8d56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556b8d56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5637aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5637aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5637aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556b8d56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (1085 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9d4a6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9d4a6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9d4a6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9098a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9098aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9098a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9098a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9d4a03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9d4a03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9d49e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9d4697e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9d4697b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9098a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9098a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9098a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9d4697a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (1086 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634d4ce9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634d4ce6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634d4cea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6473249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6473249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6473231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634d4c7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634d4c7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634d4c648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634d4913e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634d4913b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6473232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634d4913a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (1087 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d287eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d287e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d287ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f13933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f1398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f13933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f1391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d28782bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d28782a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d287678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d28416e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d28416b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f1391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f1391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f1391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d28416a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (1088 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 
# | ...
# `---data was truncated (10240/14429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562be8b18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562be8b15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562be8b1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7501733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f750178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7501733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f750171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562be8aaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562be8aaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562be8a938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562be8742e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562be8742b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f750171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f750171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f750171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562be8742a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (1089 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f79f9c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f79f9c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f79f9c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4aa905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4aa95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4aa905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4aa8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f79f959bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f79f959a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f79f93e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f79f5ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f79f5edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4aa8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4aa8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4aa8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f79f5eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (1090 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bc24a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bc249ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bc24a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5565a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5565a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5565a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5565a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bc2437bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bc2437a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bc241c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bc20cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bc20cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5565a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5565a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5565a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bc20cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (1091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f305fbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f305fb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f305fbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f56105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f5615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f56105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f560ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f305f52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f305f52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f305f378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f305be6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f305be6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f560eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f560ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f560ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f305be6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (1092 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/13617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f386ae8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f386ae5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f386ae962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb50449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb50449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb50431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f386a7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f386a7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f386a638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f386712e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f386712b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb50432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f386712a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (1093 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x h
# | ...
# `---data was truncated (10240/619135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615b1b82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615b1b7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615b1b8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddc6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddc6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddc6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddc6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615b1b18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615b1b18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615b1afd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615b17ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615b17acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddc6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddc6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddc6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615b17aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (1094 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fac302eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fac2ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fac30362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94abf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94abf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94abf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94abf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fac298bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fac298a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fac27d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fabf2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fabf2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94abf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94abf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94abf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fabf2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (1095 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afa9db2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afa9dafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afa9db362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff338533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff33858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff338533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff33851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afa9d48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afa9d48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afa9d2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afa99dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afa99dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff33851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff33851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff33851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afa99dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (1096 of 27910)
******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc    -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | $__profc__Z6helperi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6helperi = comdat any
# | 
# | $__profc__Z6kernelPi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6kernelPi = comdat any
# | 
# | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0
# | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8
# | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8
# | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1
# | @__start___llvm_prf_names = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_names = external hidden addrspace(1) global i8
# | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__start___llvm_prf_data = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_data = external hidden addrspace(1) global i8
# | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__llvm_profile_raw_version = external addrspace(1) constant i64
# | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version }
# | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %x.addr = alloca i32, align 4, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store i32 %x, ptr %x.addr.ascast, align 4
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load i32, ptr %x.addr.ascast, align 4
# |   %add = add nsw i32 %1, 1
# |   ret i32 %add
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
# | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %p = alloca ptr, align 8, addrspace(5)
# |   %p.addr = alloca ptr, align 8, addrspace(5)
# |   %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr
# |   store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8
# |   %p1 = load ptr, ptr addrspace(5) %p, align 8
# |   store ptr %p1, ptr %p.addr.ascast, align 8
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load ptr, ptr %p.addr.ascast, align 8
# |   %2 = load i32, ptr %1, align 4
# |   %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4
# |   %3 = load ptr, ptr %p.addr.ascast, align 8
# |   store i32 %call, ptr %3, align 4
# |   ret void
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | declare i32 @__llvm_profile_sampling_gpu(i32)
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3
# | 
# | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64)
# | 
# | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { nounwind }
# | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #4 = { convergent nounwind "uniform-work-group-size" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 2, !"EnableValueProfiling", i32 0}
# | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# |  #0 0x000055b87aef4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b87aef1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b87aef562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddce133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddce18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddce133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddce11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b87ae8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b87ae8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b87ae6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b87ab1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b87ab1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddce11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddce11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddce11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b87ab1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (1097 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c0f281eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c0f27ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c0f28262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3feb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3feb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3feb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3feaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c0f217bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c0f217a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c0f1fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c0eeabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c0eeabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3feaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3feaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3feaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c0eeaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (1098 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define d
# | ...
# `---data was truncated (10240/25350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e2edc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e2edc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e2edc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab8e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab8e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab8e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab8e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e2ed5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e2ed5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e2ed408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e2e9efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e2e9efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab8e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab8e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab8e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e2e9efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (1099 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d5f184eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d5f181e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d5f18562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaefa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaefaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaefa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaefa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d5f11abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d5f11aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d5f0ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d5edaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d5edaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faaefa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaefa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaefa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d5edaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (1100 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640f93f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640f93f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640f93f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00ea305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00ea35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00ea305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00ea2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640f938bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640f938ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640f93708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640f901fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640f901fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00ea2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00ea2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00ea2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640f901fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (1101 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555aa2e2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555aa2e2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555aa2e2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5a3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5a315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5a3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5a30ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555aa2dc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555aa2dc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555aa2da88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555aa2a57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555aa2a57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5a30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5a30ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5a30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aa2a57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (1102 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fe78fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fe78fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fe78fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c79b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c79b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c79b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c79aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fe7893bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fe7893a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fe78788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fe7527e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fe7527b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c79aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c79aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c79aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fe7527a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (1103 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e22dafdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e22dafae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e22dafe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fded3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fded318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fded3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fded311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e22da93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e22da93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e22da788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e22d727e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e22d727b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fded311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fded311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fded311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e22d727a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (1104 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056429c9d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056429c9d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056429c9d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9d761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9d76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9d761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9d7603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056429c96abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056429c96aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056429c94f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056429c5fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056429c5feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9d7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9d76050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9d76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056429c5fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (1105 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653d53b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653d53b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653d53b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6fea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6feaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6fea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6fea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653d5349bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653d5349a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653d532e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653d4fdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653d4fddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6fea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6fea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6fea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653d4fdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (1106 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056179f73feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056179f73ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056179f74062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf8f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf8f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf8f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf8f603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056179f6d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056179f6d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056179f6ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056179f369e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056179f369b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf8f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf8f6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf8f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056179f369a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (1107 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load 
# | ...
# `---data was truncated (10240/31171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561df48f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561df48eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561df48f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cdbf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cdbf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cdbf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cdbeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561df4887bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561df4887a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561df486c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561df451be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561df451bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cdbeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cdbeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cdbeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561df451ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (1108 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4
# | ...
# `---data was truncated (10240/96257) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b28da4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b28da1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b28da562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc484c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc484ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc484c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc484c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b28d3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b28d3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b28d1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b289cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b289ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc484c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc484c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc484c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b289cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (1109 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/72143) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609da37deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609da37ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609da37e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0806d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0806d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0806d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0806d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609da313bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609da313a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609da2f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609d9fa7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609d9fa7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0806d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0806d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0806d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609d9fa7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (1110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdd9f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bdd9f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bdd9f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe543905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe54395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe543905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5438ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdd98abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bdd98aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bdd96f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bdd61ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bdd61eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5438eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5438ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5438ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bdd61ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (1111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565344760eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056534475de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056534476162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefdf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefdf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefdf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefdf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653446f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653446f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653446db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056534438ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056534438ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefdf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefdf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefdf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056534438aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (1112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca6db16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca6db13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca6db1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8236449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8236449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8236431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca6daacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca6daaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca6da918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca6d740e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca6d740b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8236432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82364330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca6d740a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (1113 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606fefcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606fefc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606fefcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46a8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46a818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46a8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46a811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606fef62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606fef62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606fef478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606febf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606febf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46a811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46a811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46a811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606febf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (1114 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b7d2c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b7d2bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b7d2c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2b5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2b598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2b5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2b591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b7d256bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b7d256a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b7d23b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b7ceeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b7ceeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2b591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2b591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2b591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7ceeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (1115 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a71a127eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a71a124e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a71a12862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6de8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6de8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6de8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6de8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a71a0bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a71a0bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a71a0a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a719d51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a719d51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6de8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6de8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6de8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a719d51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (1116 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd1240aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd12407e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd1240b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefdc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefdc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefdc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefdc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd123a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd123a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd123858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd12034e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd12034b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefdc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefdc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefdc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd12034a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (1117 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652a923deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652a923ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652a923e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fb8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fb8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fb8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fb8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652a91d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652a91d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652a91b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652a8e67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652a8e67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fb8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fb8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fb8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652a8e67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (1118 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbe648eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbe648be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbe648f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95e1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95e1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95e1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95e1c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbe6424bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbe6424a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbe64098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbe60b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbe60b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95e1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95e1c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95e1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbe60b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (1119 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652f3068eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652f3065e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652f306962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f08449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f084a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f08449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f08431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652f2ffebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652f2ffea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652f2fe38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652f2c92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652f2c92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f08432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f084330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f084330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652f2c92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (1120 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/54480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f60ad1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f60ad1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f60ad1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88a8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88a80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88a8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88a8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f60acb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f60acb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f60ac998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f60a948e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f60a948b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88a8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88a80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88a80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f60a948a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (1121 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056031dc2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056031dc29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056031dc2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cdfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cdfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cdfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cdfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056031dbc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056031dbc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056031dba78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056031d856e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056031d856b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5cdfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cdfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cdfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056031d856a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (1122 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7a8ac3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7a8ac0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7a8ac462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facaf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facaf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facaf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facaf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7a8a59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7a8a59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7a8a3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7a86ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7a86edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facaf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facaf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facaf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7a86eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (1123 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563755fcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563755fc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563755fcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ddf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ddf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ddf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ddf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563755f62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563755f62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563755f478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563755bf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563755bf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ddf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ddf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ddf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563755bf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (1124 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d65ca7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d65ca78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d65ca7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d06449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d06449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d06431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d65ca11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d65ca11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d65c9f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d65c6a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d65c6a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d06432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d65c6a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (1125 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10878) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647a4d3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647a4d39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647a4d3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd10d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647a4cd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647a4cd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647a4cb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647a4966e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647a4966b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647a4966a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (1126 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64.p0(<vscale x 8 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale 
# | ...
# `---data was truncated (10240/39900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561374951eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056137494ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056137495262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6c2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6c2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6c2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6c2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613748e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613748e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613748cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056137457be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056137457bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6c2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6c2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6c2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056137457ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (1127 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632162cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632162c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632162cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2607733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f260778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2607733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f260771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563216262bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563216262a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632162478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563215ef6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563215ef6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f260771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f260771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f260771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563215ef6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (1128 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, alig
# | ...
# `---data was truncated (10240/150641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c70f6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c70f6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c70f7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc39e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc39ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc39e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc39e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c70f05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c70f05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c70eea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c70b99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c70b99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc39e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc39e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc39e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c70b99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (1129 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/26748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7993dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7993d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7993dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe91f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe91f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe91f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe91f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d799371bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d799371a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7993568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d799005e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d799005b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe91f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe91f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe91f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d799005a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (1130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558201be6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558201be3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558201be762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb288e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb288e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb288e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb288e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558201b7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558201b7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558201b618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558201810e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558201810b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb288e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb288e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb288e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558201810a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (1131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056167758aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561677587e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056167758b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81e6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81e695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81e6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81e68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561677520bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561677520a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616775058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616771b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616771b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81e68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81e68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81e68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616771b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (1132 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load 
# | ...
# `---data was truncated (10240/29128) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559604fd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559604fd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559604fd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff237649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff237649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff237631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559604f6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559604f6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559604f518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559604c00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559604c00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff237632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2376330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559604c00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (1133 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d799cfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d799cf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d799cfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa031449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0314a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa031449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa031431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d799c91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d799c91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d799c768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d799925e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d799925b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa031432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0314330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0314330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d799925a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (1134 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fdf6d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fdf6d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fdf6d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f245b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f245b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f245b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f245b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fdf66abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fdf66aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fdf64f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fdf2fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fdf2feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f245b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f245b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f245b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fdf2fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (1135 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e03f94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e03f91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e03f9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d3a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d3a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d3a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d3a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e03f2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e03f2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e03f0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e03bbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e03bbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d3a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d3a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d3a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e03bbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (1136 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon         -target-feature +v8.3a         -target-feature +fullfp16         -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i)
# |   %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8>
# |   store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %acc.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float>
# |   %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float>
# |   %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i)
# |   %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8>
# |   store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %lhs.addr = alloca <8 x half>, align 16
# |   %rhs.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %lhs, ptr %lhs.addr, align 16
# |   store <8 x half> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %lhs.addr, align 16
# |   %2 = load <8 x half>, ptr %rhs.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i)
# |   %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %lhs.addr = alloca <4 x float>, align 16
# |   %rhs.addr = alloca <4 x float>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <4 x float> %lhs, ptr %lhs.addr, align 16
# |   store <4 x float> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <4 x float>, ptr %lhs.addr, align 16
# |   %2 = load <4 x float>, ptr %rhs.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float>
# |   %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float>
# |   %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i)
# |   %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <2 x double>, align 16
# |   %lhs.addr = alloca <2 x double>, align 16
# |   %rhs.addr = alloca <2 x double>, align 16
# |   store <2 x double> %acc, ptr %acc.addr, align 16
# |   store <2 x double> %lhs, ptr %lhs.addr, align 16
# |   store <2 x double> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <2 x double>, ptr %acc.addr, align 16
# |   %1 = load <2 x double>, ptr %lhs.addr, align 16
# |   %2 = load <2 x double>, ptr %rhs.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double>
# |   %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double>
# |   %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double>
# |   %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i)
# |   %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16
# |   %6 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %6, ptr %__ret.i, align 16
# |   %7 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v
# | ...
# `---data was truncated (10240/166298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# |  #0 0x0000556287f08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556287f05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556287f0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3195105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f319515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3195105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31950ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556287e9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556287e9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556287e838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556287b32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556287b32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31950eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31950ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31950ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556287b32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (1137 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a96be9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a96be98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a96be9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe018049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0180a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe018049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe018031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a96be31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a96be31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a96be168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a96bac5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a96bac5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe018032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0180330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0180330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a96bac5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (1138 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f7fb35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f7fb32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f7fb3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe557505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe55755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe557505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5574ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f7facbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f7facba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f7fab08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f7f75fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f7f75fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5574eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5574ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5574ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f7f75fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (1139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale
# | ...
# `---data was truncated (10240/410383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e7e953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e7e950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e7e95462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00d6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00d6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00d6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00d6a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e7e8e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e7e8e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e7e8ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e7e57de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e7e57db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00d6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00d6a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00d6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e7e57da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (1140 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbd4541eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbd453ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbd454262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faba7505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faba755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faba7505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faba74ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbd44d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbd44d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbd44bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbd416be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbd416bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faba74eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faba74ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faba74ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbd416ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (1141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e8f3eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e8f3e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e8f3ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4db6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4db66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4db6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4db6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e8f382bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e8f382a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e8f3678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e8f016e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e8f016b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4db6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4db66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4db66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e8f016a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (1142 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/22367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a6a979eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a6a976e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a6a97a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6dd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6dd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6dd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6dd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a6a90fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a6a90fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a6a8f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a6a5a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a6a5a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6dd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6dd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6dd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a6a5a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (1143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626da48eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626da48be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626da48f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8de1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8de1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8de1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8de1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626da424bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626da424a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626da4098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626da0b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626da0b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8de1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8de1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8de1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626da0b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (1144 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | ...
# `---data was truncated (10240/66298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055952e3d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055952e3d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055952e3da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93c9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93c9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93c9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93c9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055952e36fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055952e36fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055952e3548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055952e003e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055952e003b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93c9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93c9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93c9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055952e003a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (1145 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055d923573eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d923570e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d92357462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a79533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a7958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a79533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a7951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d923509bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d923509a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9234ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d92319de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d92319db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a7951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a7951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a7951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d92319da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-fma.c (1146 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %sub.i = fsub <4 x float> %3, %mul.i
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %sub.i = fsub <2 x float> %3, %mul.i
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_68 = alloca <2 x float>, align 8
# |   %__s0_68 = alloca <2 x float>, align 8
# |   %__s1_68 = alloca <2 x float>, align 8
# |   %__s2_68 = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp1 = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0_68, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_68, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_68, align 8
# |   %3 = load <2 x float>, ptr %__s0_68, align 8
# |   %4 = load <2 x float>, ptr %__s1_68, align 8
# |   %5 = load <2 x float>, ptr %__s2_68, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   %mul = fmul <2 x float> %4, %10
# |   %add = fadd <2 x float> %3, %mul
# |   store <2 x float> %add, ptr %__ret_68, align 8
# |   %11 = load <2 x float>, ptr %__ret_68, align 8
# |   store <2 x float> %11, ptr %tmp1, align 8
# |   %12 = load <2 x float>, ptr %tmp1, align 8
# |   ret <2 x float> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_58 = alloca <4 x float>, align 16
# |   %__s0_58 = alloca <4 x float>, align 16
# |   %__s1_58 = alloca <4 x float>, align 16
# |   %__s2_58 = alloca <2 x float>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp1 = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__s0_58, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_58, align 16
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_58, align 8
# |   %3 = load <4 x float>, ptr %__s0_58, align 16
# |   %4 = load <4 x float>, ptr %__s1_58, align 16
# |   %5 = load <2 x float>, ptr %__s2_58, align 8
# |   store <2 x f
# | ...
# `---data was truncated (10240/44730) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d2708f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2708f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2708f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2806533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f280658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2806533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f280651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d270889bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d270889a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d27086e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d27051de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d27051db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f280651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f280651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f280651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d27051da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (1147 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e85221feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e85221ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e85222062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffba0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffba018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffba0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffba011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8521b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8521b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e85219a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e851e49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e851e49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffba011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffba011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffba011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e851e49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (1148 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563073b02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563073affe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563073b0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fff249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fff2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fff249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fff231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563073a98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563073a98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563073a7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056307372ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056307372cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fff232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fff2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fff2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056307372ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (1149 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556300619eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556300616e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055630061a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6366849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63668a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6366849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6366831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563005afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563005afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563005948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556300243e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556300243b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6366832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63668330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63668330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556300243a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (1150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603c35a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603c35a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603c35aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b19a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b19a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b19a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b19a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603c353fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603c353fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603c35248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603c31d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603c31d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b19a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b19a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b19a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603c31d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (1151 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/51759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560719a95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560719a92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560719a9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9285105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f928515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9285105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92850ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560719a2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560719a2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560719a108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607196bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607196bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92850eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92850ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92850ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607196bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (1152 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c2e35ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c2e359e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c2e35d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefd5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefd5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefd5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefd5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c2e2f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c2e2f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c2e2d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c2df86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c2df86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefd5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefd5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefd5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c2df86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (1153 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562089118eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562089115e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056208911962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0f1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0f198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0f1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0f191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620890aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620890aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620890938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562088d42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562088d42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0f191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0f191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0f191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562088d42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-neon-vcadd.c (1154 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic  -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.3a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i)
# |   %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i)
# |   %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i)
# |   %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %result = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i)
# |   %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i)
# |   %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i)
# |   %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i)
# |   %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 
# | ...
# `---data was truncated (10240/13572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# |  #0 0x000055ed6d14feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed6d14ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed6d15062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d33f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d33f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d33f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d33f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed6d0e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed6d0e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed6d0ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed6cd79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed6cd79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d33f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d33f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d33f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed6cd79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (1155 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__ret.i, align 8
# |   %2 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 {
# | entry:
# |   
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000557f9ac44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f9ac41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f9ac4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc353d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc353d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc353d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc353ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f9abdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f9abdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f9abbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f9a86ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f9a86eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc353ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc353cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc353cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f9a86ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (1156 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562684c4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562684c4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562684c4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5286333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f528638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5286333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f528631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562684be4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562684be4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562684bc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562684878e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562684878b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f528631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f528631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f528631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562684878a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (1157 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571f0fbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571f0fb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571f0fbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe567e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe567e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe567e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe567e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571f0f51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571f0f51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571f0f368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571f0be5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571f0be5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe567e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe567e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe567e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571f0be5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (1158 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i6
# | ...
# `---data was truncated (10240/35605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056353d6b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056353d6afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056353d6b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43d5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43d518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43d5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43d511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056353d648bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056353d648a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056353d62d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056353d2dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056353d2dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43d511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43d511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43d511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056353d2dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (1159 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d20e64eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d20e64be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d20e64f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1137e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1137ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1137e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1137e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d20e5e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d20e5e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d20e5c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d20e278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d20e278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1137e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1137e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1137e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d20e278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (1160 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16
# | ...
# `---data was truncated (10240/338692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a86bdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a86bdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a86be062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f626ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f626ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f626ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f626ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a86b75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a86b75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a86b5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a86809e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a86809b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f626ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f626ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f626ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a86809a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (1161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056396b577eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056396b574e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056396b57862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f403fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f403faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f403fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f403fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056396b50dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056396b50da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056396b4f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056396b1a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056396b1a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f403fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f403fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f403fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056396b1a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (1162 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005610ed185eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610ed182e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610ed18662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff5df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610ed11bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610ed11ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610ed1008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610ecdafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610ecdafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610ecdafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (1163 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align
# | ...
# `---data was truncated (10240/30281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000559b19c14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b19c11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b19c1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01b7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01b7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01b7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01b7e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b19baabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b19baaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b19b8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b1983ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b1983eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01b7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01b7e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01b7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b1983ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (1164 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055652d603eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055652d600e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055652d60462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8dbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8dbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8dbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8dbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055652d599bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055652d599a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055652d57e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055652d22de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055652d22db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8dbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8dbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8dbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055652d22da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (1165 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055731f347eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055731f344e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055731f34862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8da7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8da7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8da7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8da7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055731f2ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055731f2dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055731f2c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055731ef71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055731ef71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8da7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8da7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8da7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055731ef71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (1166 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055add076beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055add0768e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055add076c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1ab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1ab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1ab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1ab231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055add0701bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055add0701a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055add06e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055add0395e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055add0395b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1ab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1ab2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1ab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055add0395a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (1167 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.
# | ...
# `---data was truncated (10240/30759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647c9c84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647c9c81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647c9c8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa13e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa13e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa13e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa13e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647c9c1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647c9c1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647c9bff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647c98aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647c98aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa13e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa13e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa13e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647c98aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (1168 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b066c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b066c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b066c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75da533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75da58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75da533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75da51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b0665cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b0665ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b066418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b062f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b062f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75da51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75da51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75da51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b062f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (1169 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565230f87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565230f84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565230f8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8440e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8440ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8440e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8440e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565230f1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565230f1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565230f028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565230bb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565230bb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8440e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8440e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8440e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565230bb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (1170 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055858befeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055858befbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055858beff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5c4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5c46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5c4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5c4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055858be94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055858be94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055858be798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055858bb28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055858bb28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5c4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5c46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5c46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055858bb28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (1171 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e90ecd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e90eccfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e90ecd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5e3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5e3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5e3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5e3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e90ec68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e90ec68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e90ec4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e90e8fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e90e8fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5e3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5e3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5e3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e90e8fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (1172 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d890285eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d890282e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d89028662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9815b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9815b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9815b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9815b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d89021bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d89021ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8902008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d88feafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d88feafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9815b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9815b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9815b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d88feafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (1173 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entr
# | ...
# `---data was truncated (10240/18361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd945cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd945cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd945d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3c4b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3c4b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3c4b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3c4aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd94565bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd94565a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd9454a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd941f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd941f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3c4aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3c4aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3c4aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd941f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (1174 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bee3a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bee39ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bee3a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef4821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef482725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef4821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef48203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bee337bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bee337a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bee31c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bedfcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bedfcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef48204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef482050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef482050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bedfcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (1175 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 =
# | ...
# `---data was truncated (10240/26564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fd14ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fd14dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fd14de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80dc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80dc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80dc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80dc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fd1473bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fd1473a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fd14588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fd1107e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fd1107b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80dc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80dc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80dc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fd1107a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (1176 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloc
# | ...
# `---data was truncated (10240/122004) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005649a78cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649a78c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649a78cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c94b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c94b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c94b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c94b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649a7861bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649a7861a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649a78468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649a74f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649a74f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c94b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c94b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c94b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649a74f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (1177 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c58975eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c58972e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c5897662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e18e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e18ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e18e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e18e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c5890bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c5890ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c588f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c5859fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c5859fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e18e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e18e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e18e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c5859fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (1178 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dee5f4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dee5f47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dee5f4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8925449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89254a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8925449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8925431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dee5ee0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dee5ee0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dee5ec58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dee5b74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dee5b74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8925432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89254330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89254330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dee5b74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (1179 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a71454feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a71454ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a71455062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2377733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f237778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2377733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f237771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7144e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7144e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7144ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a714179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a714179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f237771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f237771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f237771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a714179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (1180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/78328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562642412eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056264240fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056264241362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dad733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dad78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dad733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dad71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626423a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626423a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056264238d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056264203ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056264203cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dad71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dad71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dad71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056264203ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (1181 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055decccfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055decccf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055decccfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc10e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc10ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc10e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc10e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055deccc90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055deccc90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055deccc758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055decc924e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055decc924b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc10e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc10e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc10e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055decc924a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (1182 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b31126eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b31123e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b3112762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83e681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83e68725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83e681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83e6803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b310bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b310bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b310a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b30d50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b30d50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83e6804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83e68050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83e68050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b30d50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (1183 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de09f31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de09f2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de09f3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff72d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff72d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff72d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff72d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de09ec7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de09ec7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de09eac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de09b5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de09b5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff72d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff72d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff72d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de09b5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (1184 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056096da36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056096da33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056096da3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b56f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b56f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b56f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b56f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056096d9ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056096d9cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056096d9b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056096d660e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056096d660b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b56f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b56f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b56f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056096d660a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (1185 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64)
# | ...
# `---data was truncated (10240/34765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555883359eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555883356e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055588335a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3700333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f370038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3700333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f370031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558832efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558832efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558832d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555882f83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555882f83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f370031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f370031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f370031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555882f83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (1186 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, <vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, <vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/200802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628c0569eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628c0566e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628c056a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8992333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f899238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8992333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f899231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628c04ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628c04ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628c04e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628c0193e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628c0193b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f899231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f899231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f899231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628c0193a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (1187 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c9cc40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c9cc3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c9cc4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bd0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bd018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bd0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bd011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c9cbd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c9cbd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c9cbbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c9c86ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c9c86ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bd011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bd011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bd011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c9c86aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (1188 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bded4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bded4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bded4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f785e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f785e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f785e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f785e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bdece3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bdece3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bdecc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bde977e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bde977b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f785e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f785e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f785e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bde977a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (1189 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563967f4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563967f47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563967f4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4adf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4adf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4adf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4adf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563967ee0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563967ee0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563967ec58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563967b74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563967b74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4adf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4adf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4adf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563967b74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (1190 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2, align 8
# |   %extract = extractelement <1 x double> %5, i32 0
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.fma.f64(double, double, double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <2 x double>, ptr %__s2, align 16
# |   %extract = extractelement <2 x double> %5, i32 1
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret_443 = alloca float, align 4
# |   %__s0_443 = alloca float, align 4
# |   %__s1_443 = alloca float, align 4
# |   %__s2_443 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_443, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1_443, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2_443, align 8
# |   %3 = load float, ptr %__s0_443, align 4
# |   store float %3, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1_443, align 4
# |   %fneg = fneg float %4
# |   store float %fneg, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2_443, align 8
# |   store <2 x float> %5, ptr %__s2, align 8
# |   %6 = load float, ptr %__s0, align 4
# |   %7 = load float, ptr %__s1, align 4
# |   %8 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %8, i32 1
# |   %9 = call float @llvm.fma.f32(float %7, float %extract, float %6)
# |   store float %9, ptr %ref.tmp, align 4
# |   %10 = load float, ptr %ref.tmp, align 4
# |   store float %10, ptr %__ret, align 4
# |   %11 = load float, ptr %__ret, align 4
# |   store float %11, ptr %tmp, align 4
# |   %12 = load float, ptr %tmp, align 4
# |   store float %12, ptr %__ret_443, align 4
# |   %13 = load float, ptr %__ret_443, align 4
# |   store float %13, ptr %tmp1, align 4
# |   %14 = load float, ptr %tmp1, align 4
# |   ret float %14
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.fma.f32(float, float, float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret_449 = alloca <1 x double>, align 8
# |   %__s0_449 = alloca <1 x double>, align 8
# |   %__s1_449 = alloca <1 x double>, align 8
# |   %__s2_449 = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   %tmp3 = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0_449, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_449, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2_449, align 8
# |   %3 = load <1 x double>, ptr %__s0_449, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s1_449, align 8
# |   %fneg = fneg <1 x double> %4
# |   store <1 x double> %fneg, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2_449, align 8
# |   store <1 x double> %5, ptr %__s2, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = load <8 x i8>, ptr %__s1, align 8
# |   %8 = load <8 x i8>, ptr %__s2, align 8
# |   %9 = bitcast <8 x i8> %8 to <1 x double>
# |   %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %7 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %6 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %10, ptr %__ret, align 8
# |   %11 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %11, ptr %tmp, align 8
# |   %12 = load <1 x double>, ptr %tmp, align 8
# |   store <1 x double> %12, ptr %__ret_449, align 8
# |   %13 = load <1 x double>, ptr %__ret_449, align 8
# |   store <1 x double> %13, ptr %tmp3, align 8
# |   %14 = load <1 x double>, ptr %tmp3, align 8
# |   ret <1 x double> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret_460 = alloca <1 x double>, align 8
# |   %__s0_460 = alloca <1 x double>, align 8
# |   %__s1_460 = alloca <1 x double>, align 8
# |   %__s2_460 = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %_
# | ...
# `---data was truncated (10240/12799) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055cfd9ee8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfd9ee5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfd9ee962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc369333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc36938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc369333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc36931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd9e7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfd9e7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfd9e638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfd9b12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfd9b12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc36931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc36931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc36931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd9b12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (1191 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056301c674eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056301c671e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056301c67562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48ae249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48ae2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48ae249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48ae231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056301c60abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056301c60aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056301c5ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056301c29ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056301c29eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48ae232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48ae2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48ae2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056301c29ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (1192 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3c4e83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3c4e80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3c4e8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f0ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f0ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f0ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f0aced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3c4e19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3c4e19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3c4dfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3c4aade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3c4aadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f0aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f0acef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f0acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3c4aada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (1193 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562767cd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562767cd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562767cd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5959649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59596a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5959649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5959631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562767c69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562767c69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562767c4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627678fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627678fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5959632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59596330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59596330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627678fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (1194 of 27910)
******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }>
# | %struct.A.base = type <{ ptr, i32 }>
# | 
# | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8
# | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x000055ea8c142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea8c13fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea8c14362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff81a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff81a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff81a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff81a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea8c0d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea8c0d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea8c0bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea8bd6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea8bd6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff81a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff81a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff81a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea8bd6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (1195 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f1ed12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f1ed0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f1ed1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59fed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59fed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59fed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59fed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f1eca8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f1eca8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f1ec8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f1e93ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f1e93cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59fed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59fed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59fed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f1e93ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (1196 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5aa0d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5aa0d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5aa0d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc470c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc470ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc470c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc470c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5aa06cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5aa06ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5aa0518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5a9d00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5a9d00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc470c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc470c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc470c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5a9d00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (1197 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/150951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056246bdf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056246bdf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056246bdf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f366a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f366a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f366a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f366a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056246bd8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056246bd8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056246bd738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056246ba22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056246ba22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f366a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f366a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f366a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056246ba22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (1198 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b39774eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b39771e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b3977562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f046a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f046a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f046a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f046a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b3970abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b3970aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b396ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b3939ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b3939eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f046a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f046a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f046a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b3939ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (1199 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c82e556eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c82e553e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c82e55762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e09733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e0978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e09733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e0971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c82e4ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c82e4eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c82e4d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c82e180e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c82e180b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e0971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e0971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e0971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c82e180a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (1200 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b9050aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b90507e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b9050b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7864705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f786475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7864705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78646ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b904a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b904a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b904858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b90134e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b90134b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78646eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78646ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78646ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b90134a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (1201 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570e72c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570e72c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570e72c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9669933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f966998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9669933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f966991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570e725dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570e725da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570e72428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570e6ef1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570e6ef1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f966991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f966991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f966991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570e6ef1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (1202 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   
# | ...
# `---data was truncated (10240/12381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9d783aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9d7837e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9d783b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad2a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad2a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad2a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad2a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9d77d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9d77d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9d77b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9d7464e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9d7464b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad2a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad2a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad2a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9d7464a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (1203 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/68133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055631b7deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055631b7dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055631b7df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7136849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71368a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7136849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7136831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055631b774bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055631b774a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055631b7598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055631b408e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055631b408b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7136832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71368330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71368330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055631b408a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (1204 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056498db6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056498db6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056498db6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f119ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f119eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f119ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f119ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056498db04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056498db04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056498dae98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056498d798e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056498d798b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f119ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f119ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f119ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056498d798a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (1205 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a74076eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a74073e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a7407762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd47c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd47c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd47c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd47c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a7400cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a7400ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a73ff18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a73ca0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a73ca0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd47c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd47c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd47c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a73ca0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (1206 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vs
# | ...
# `---data was truncated (10240/210427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588b7af8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588b7af5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588b7af962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3283d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3283d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3283d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3283d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588b7a8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588b7a8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588b7a738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588b7722e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588b7722b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3283d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3283d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3283d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588b7722a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (1207 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nof
# | ...
# `---data was truncated (10240/11966) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e8ca6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e8ca6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e8ca6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68c3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68c378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68c3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68c371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e8ca03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e8ca03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e8c9e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e8c697e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e8c697b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68c371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68c371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68c371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e8c697a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (1208 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563aacb70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563aacb6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563aacb7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f760ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f760caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f760ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f760ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563aacb06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563aacb06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563aacaeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563aac79ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563aac79ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f760ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f760ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f760ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563aac79aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (1209 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b12a89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b12a86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b12a8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57dfb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57dfb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57dfb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57dfaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b12a1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b12a1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b12a048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b126b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b126b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57dfaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57dfaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57dfaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b126b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (1210 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.
# | ...
# `---data was truncated (10240/28427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d04dab8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d04dab5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d04dab962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fa7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fa758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fa7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fa751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d04da4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d04da4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d04da338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d04d6e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d04d6e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fa751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fa751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fa751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d04d6e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (1211 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eabcdebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eabcde8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eabcdec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79b7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79b7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79b7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79b7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eabcd81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eabcd81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eabcd668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eabca15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eabca15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79b7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79b7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79b7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eabca15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (1212 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558110b30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558110b2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558110b3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31a321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31a32725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31a321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31a3203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558110ac6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558110ac6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558110aab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055811075ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055811075ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31a3204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31a32050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31a32050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055811075aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (1213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa279c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa279bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa279c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92d8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92d80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92d8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92d8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa27956bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa27956a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa2793b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa275eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa275eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92d8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92d80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92d80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa275eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (1214 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# | 
# | ...
# `---data was truncated (10240/211223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa3583feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa3583ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa3584062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf1de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf1dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf1de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf1de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa357d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa357d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa357ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa35469e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa35469b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf1de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf1de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf1de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa35469a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (1215 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4c2dd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4c2dd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4c2dd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff94f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff94f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff94f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff94f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4c2d6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4c2d6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4c2d508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4c29ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4c29ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff94f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff94f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff94f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4c29ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (1216 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055963b15deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055963b15ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055963b15e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb326733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb32678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb326733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb32671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055963b0f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055963b0f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055963b0d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055963ad87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055963ad87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb32671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb32671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb32671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055963ad87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (1217 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc5e378eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc5e375e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc5e37962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5f6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5f698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5f6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5f691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc5e30ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc5e30ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc5e2f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc5dfa2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc5dfa2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5f691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5f691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5f691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc5dfa2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (1218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/150943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dfbc59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dfbc56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dfbc5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fa3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fa318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fa3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fa311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dfbbefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dfbbefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dfbbd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dfb883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dfb883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fa311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fa311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fa311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dfb883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (1219 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.a
# | ...
# `---data was truncated (10240/63518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a2dfb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a2dfb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a2dfb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f301a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f301a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f301a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f301a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a2df49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a2df49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a2df2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a2dbdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a2dbddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f301a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f301a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f301a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a2dbdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (1220 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/68247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2bcd3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2bcd37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2bcd3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20f5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20f52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20f5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20f5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2bccd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2bccd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2bccb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2bc964e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2bc964b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20f5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20f52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20f52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2bc964a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (1221 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558477ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558477fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055584780062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0a3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0a398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0a3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0a391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555847795bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555847795a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055584777a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555847429e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555847429b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0a391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0a391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0a391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555847429a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (1222 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602f888aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602f8887e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602f888b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff83cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff83cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff83cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff83cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602f8820bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602f8820a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602f88058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602f84b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602f84b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff83cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff83cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff83cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602f84b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (1223 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055715a2cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055715a2c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055715a2cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65de533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65de58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65de533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65de51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055715a262bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055715a262a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055715a2478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557159ef6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557159ef6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65de51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65de51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65de51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557159ef6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (1224 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a6454eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a6454be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a6454f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88a6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88a698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88a6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88a691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a644e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a644e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a644c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a64178e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a64178b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88a691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88a691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88a691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a64178a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (1225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cd20a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cd20a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cd20a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fede1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fede198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fede1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fede191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cd203bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cd203ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cd20208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cd1ccfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cd1ccfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fede191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fede191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fede191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cd1ccfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (1226 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dcd507eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dcd504e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dcd50862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f458bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f458bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f458bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f458baed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dcd49dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dcd49da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dcd4828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dcd131e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dcd131b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f458baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f458baef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f458baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dcd131a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (1227 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565516e28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565516e25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565516e2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8eb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8eb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8eb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8eb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565516dbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565516dbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565516da38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565516a52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565516a52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8eb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8eb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8eb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565516a52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (1228 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603395e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603395e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603395ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8ed133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8ed18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8ed133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8ed11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056033957fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056033957fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603395648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560339213e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560339213b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8ed11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8ed11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8ed11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560339213a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (1229 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4f4b4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4f4b4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4f4b5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f204b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f204b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f204b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f204b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4f4ae5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4f4ae5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4f4aca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4f4779e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4f4779b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f204b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f204b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f204b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4f4779a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (1230 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4252e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4252e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4252e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb322649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3226a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb322649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb322631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f425279bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f425279a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f42525e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f424f0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f424f0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb322632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3226330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3226330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f424f0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (1231 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8229c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8229bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8229c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36c3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36c398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36c3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36c391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c822957bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c822957a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c82293c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8225ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8225ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36c391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36c391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36c391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8225eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (1232 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654a02f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654a02f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654a02f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94c3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94c338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94c3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94c331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654a028abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654a028aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654a026f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056549ff1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056549ff1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94c331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94c331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94c331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056549ff1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (1233 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055772e239eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055772e236e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055772e23a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa07fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa07fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa07fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa07fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772e1cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055772e1cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055772e1b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055772de63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055772de63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa07fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa07fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa07fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055772de63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (1234 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055717f965eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055717f962e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055717f96662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55abd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55abd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55abd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55abd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055717f8fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055717f8fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055717f8e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055717f58fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055717f58fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55abd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55abd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55abd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055717f58fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (1235 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592bc0deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592bc0dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592bc0df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5c4c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5c4c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5c4c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5c4c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592bc074bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592bc074a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592bc0598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592bbd08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592bbd08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5c4c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5c4c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5c4c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592bbd08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (1236 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i16>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i32>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, <vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void
# | ...
# `---data was truncated (10240/179328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625509d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625509d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625509d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f2ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f2ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f2ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f2ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056255096ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056255096ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625509538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562550602e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562550602b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f2ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f2ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f2ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562550602a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (1237 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %class.anon = type { i8 }
# | 
# | $_Z15template_functyIiET_S0_ = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_caller() #0 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | declare i32 @normal_callee() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_callee() #0 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_decl() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_caller() #3 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_callee() #3 {
# | entry:
# |   %call = call i32 @streaming_compatible_decl() #16
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_compatible_decl() #4
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_caller() #5 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_callee() #5 {
# | entry:
# |   %call = call i32 @locally_streaming_caller() #17
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_caller() #6 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_callee() #6 {
# | entry:
# |   %call = call i32 @shared_za_decl() #18
# |   ret i32 %call
# | }
# | 
# | declare i32 @shared_za_decl() #7
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_caller() #8 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_callee() #8 {
# | entry:
# |   %call = call i32 @preserves_za_decl() #19
# |   ret i32 %call
# | }
# | 
# | declare i32 @preserves_za_decl() #9
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_caller() #10 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_callee() #10 {
# | entry:
# |   %call = call i32 @private_za_decl()
# |   ret i32 %call
# | }
# | 
# | declare i32 @private_za_decl() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_caller() #11 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee() #12 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | declare i32 @agnostic_za_decl() #13
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee_live_za() #6 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #16
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #18
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #19
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %fptr.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %fptr, ptr %fptr.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %fptr.addr, align 8
# |   %1 = load ptr, ptr %0, align 8
# |   %2 = load ptr, ptr %1, align 8
# |   %3 = load i32, ptr %x.addr, align 4
# |   %4 = load i32, ptr %y.addr, align 4
# |   call void %2(i32 noundef %3, i32 noundef %4) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @_Z24test_same_type_streamingv() #12 {
# | entry:
# |   call void @_Z10streaming1v() #15
# |   call void @_Z10streaming2v() #15
# |   call void @_Z20same_type_streaming1v() #15
# |   call void @_Z20same_type_streaming2v() #15
# |   ret void
# | }
# | 
# | declare void @_Z10streaming1v() #2
# | 
# | declare void @_Z10streaming2v() #2
# | 
# | declare void @_Z20same_type_streaming1v() #2
# | 
# | declare void @_Z20same_type_streaming2v() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   ret float %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   %call = call noundef float @_Z12overloadedfnf(float noundef %0)
# |   ret float %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %F = alloca %class.anon, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 {
# | entry:
# |   %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z25locally_streaming_inheritv() #5 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret void
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define dso_local noundef i32 @_Z4callv() #14 {
# | entry:
# |   ret i32 0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 {
# | entry:
# |   %f.addr.i16 = alloca ptr, align 8
# |   %f.addr.i12 = alloca ptr, align 8
# |   %other.addr.i13 = alloca ptr, align 8
# |   %f.addr.i7 = alloca ptr, align 8
# |   %other.addr.i8 = alloca ptr, align 8
# |   %other.addr2.i9 = alloca ptr, align 8
# |   %f.addr.i1 = alloca ptr, align 8
# |   %other.addr.i2 = alloca ptr, align 8
# |   %other.addr2.i3 = alloca ptr, align 8
# |   %other.addr4.i4 = alloca ptr, align 8
# |   %f.addr.i = alloca ptr, align 8
# |   %other.addr.i = alloca ptr, align 8
# |   %other.addr2.i = alloca ptr, align 8
# |   %other.addr4.i = alloca ptr, align 8
# |   %other.addr6.i = alloca ptr, align 8
# |   store ptr @normal_callee, ptr %f.addr.i, align 8
# |   store ptr @streaming_decl, ptr %other.addr.i, align 8
# |   store ptr @streaming_compatible_decl
# | ...
# `---data was truncated (10240/15241) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056279f3abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056279f3a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056279f3ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef84733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef8478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef84733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef8471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056279f341bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056279f341a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056279f3268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056279efd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056279efd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef8471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef8471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef8471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056279efd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x000055cfe8167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfe8164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfe816862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a4ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a4eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a4ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a4ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfe80fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfe80fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfe80e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfe7d91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfe7d91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a4ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a4ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a4ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfe7d91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (1238 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.n
# | ...
# `---data was truncated (10240/33624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be55e0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be55e0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be55e0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d11a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d11aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d11a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d11a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be55da4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be55da4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be55d898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be55a38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be55a38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d11a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d11a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d11a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be55a38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (1239 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b26beddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b26bedae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b26bede62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5b6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5b638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5b6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5b631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b26be73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b26be73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b26be588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b26bb07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b26bb07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5b631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5b631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5b631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b26bb07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (1240 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556151d07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556151d04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556151d0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05a8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05a8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05a8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05a8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556151c9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556151c9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556151c828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556151931e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556151931b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05a8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05a8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05a8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556151931a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (1241 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3185cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3185cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3185ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ce8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ce84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ce8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ce8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e318563bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e318563a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3185488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3181f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3181f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ce8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ce84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ce84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3181f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (1242 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555aa67cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555aa67cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555aa67ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0f8e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0f8e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0f8e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0f8e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555aa6763bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555aa6763a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555aa67488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555aa63f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555aa63f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0f8e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0f8e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0f8e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aa63f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (1243 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056504edbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056504edb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056504edbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5787249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57872a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5787249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5787231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056504ed51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056504ed51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056504ed368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056504e9e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056504e9e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5787232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57872330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57872330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056504e9e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (1244 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffa7113eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffa7110e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffa711462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f375fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f375fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f375fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f375fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffa70a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffa70a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffa708e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffa6d3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffa6d3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f375fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f375fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f375fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffa6d3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (1245 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b07afeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b07afbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b07aff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb044c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb044ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb044c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb044c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b07a94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b07a94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b07a798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b07728e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b07728b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb044c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb044c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb044c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b07728a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (1246 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555daee7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555daee7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555daee7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ada249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ada2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ada249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ada231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555daee13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555daee13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555daedf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555daeaa7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555daeaa7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ada232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ada2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ada2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555daeaa7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/cx-complex-range-real.c (1247 of 27910)
******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %mul.rl = fmul float %a.real, %0
# |   %mul.il = fmul float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.il, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul.rl = fmul float %.real, %0
# |   %mul.il = fmul float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %mul.rl, ptr %.realp1, align 4
# |   store float %mul.il, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca float, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul.rl = fmul float %0, %b.real
# |   %mul.ir = fmul float %0, %b.imag
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.ir, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = fdiv float %a.real, %0
# |   %2 = fdiv float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %1, ptr %retval.realp, align 4
# |   store float %2, ptr %retval.imagp, align 4
# |   %3 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %2 = fdiv float %.real, %0
# |   %3 = fdiv float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %2, ptr %.realp1, align 4
# |   store float %3, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load double, ptr %a.imagp, align 8
# |   %2 = load double, ptr %b.addr, align 8
# |   %3 = fdiv double %a.real, %2
# |   %4 = fdiv double %a.imag, %2
# |   %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1
# |   store double %3, ptr %retval.realp, align 8
# |   store double %4, ptr %retval.imagp, align 8
# |   %5 = load { double, double }, ptr %retval, align 8
# |   ret { double, double } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { double, double }, align 8
# |   %a.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %1, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %2 = load double, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   %b.real = load double, ptr %b.realp, align 8
# |   %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   %b.imag = load double, ptr %b.imagp, align 8
# |   %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2
# |   %3 = extractvalue { double, double } %call, 0
# |   %4 = extractvalue { double, double } %call, 1
# |   %conv = fptrunc double %3 to float
# |   %conv1 = fptrunc double %4 to float
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %conv, ptr %retval.realp, align 4
# |   store float %conv1, ptr %retval.imagp, align 4
# |   %5 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %5
# | }
# | 
# | declare { double, double } @__divdc3(double, double, double, double)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca double, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.real = load double, ptr %.realp, align 8
# |   %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   %.imag = load double, ptr %.imagp, align 8
# |   %2 = fdiv double %.real, %0
# |   %3 = fdiv double %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   store double %2, ptr %.realp1, align 8
# |   store double %3, ptr %.imagp2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %retval = alloca { x86_fp80, x86_fp80 }, align 16
# |   %b.addr = alloca x86_fp80, align 16
# |   store x86_fp80 %b, ptr %b.addr, align 16
# |   %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0
# |   %a.real = load x86_fp80, ptr %a.realp, align 16
# |   %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1
# |   %a.imag = load x86_fp80, ptr %a.imagp, align 16
# |   %0 = load x86_fp80, ptr %b.addr, align 16
# |   %1 = fdiv x86_fp80 %a.real, %0
# |   %2 = fdiv x86_fp80 %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1
# |   store x86_fp80 %1, ptr %retval.realp, align 16
# |   store x86_fp80 %2, ptr %retval.imagp, align 16
# |   %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16
# |   ret { x86_fp80, x86_fp80 } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %a.addr 
# | ...
# `---data was truncated (10240/11567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000557ffa2b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ffa2b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ffa2b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe946733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe94678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe946733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe94671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ffa249bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ffa249a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ffa22e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ff9edde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ff9eddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe94671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe94671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe94671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ff9edda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (1248 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e9d0cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e9d0c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e9d0cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb36a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb36a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb36a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb36a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e9d061bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e9d061a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e9d0468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e9ccf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e9ccf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb36a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb36a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb36a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e9ccf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (1249 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.a
# | ...
# `---data was truncated (10240/174713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dd33d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556dd33d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556dd33da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4af9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4af918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4af9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4af911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dd336fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556dd336fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556dd33548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556dd3003e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556dd3003b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4af911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4af911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4af911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dd3003a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (1250 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5c6689eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5c6686e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5c668a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb95f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb95f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb95f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb95f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5c661fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5c661fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5c66048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5c62b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5c62b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb95f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb95f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb95f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5c62b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (1251 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load p
# | ...
# `---data was truncated (10240/28353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8f9964eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8f9961e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8f996562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed2f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed2f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed2f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed2f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f98fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8f98faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8f98df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8f958ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8f958eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed2f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed2f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed2f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f958ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (1252 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a06e3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a06e3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a06e3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe88f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe88f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe88f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe88f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a06dd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a06dd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a06db88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a06a67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a06a67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe88f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe88f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe88f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a06a67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (1253 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d52207beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d522078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d52207c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f432eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f432eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f432eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f432eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d522011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d522011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d521ff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d521ca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d521ca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f432eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f432eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f432eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d521ca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (1254 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.a
# | ...
# `---data was truncated (10240/32394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5b2c09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5b2c06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5b2c0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff80c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff80c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff80c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff80c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5b2b9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5b2b9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5b2b848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5b2833e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5b2833b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff80c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff80c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff80c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5b2833a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (1255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3107daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3107d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3107db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ae649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83ae6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ae649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ae631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f310770bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f310770a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3107558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f310404e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f310404b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83ae632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ae6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ae6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f310404a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (1256 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0d8af6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0d8af3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0d8af762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ff5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ff56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ff5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ff5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0d8a8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0d8a8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0d8a718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0d8720e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0d8720b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ff5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ff56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ff56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0d8720a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (1257 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bf2956eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bf2953e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bf295762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ebd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ebd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ebd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ebd803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bf28ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bf28eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bf28d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bf2580e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bf2580b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ebd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ebd8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ebd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bf2580a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (1258 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocall
# | ...
# `---data was truncated (10240/12425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d1d273eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d1d270e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d1d27462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89ef305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89ef35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89ef305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89ef2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d1d209bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d1d209a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d1d1ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d1ce9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d1ce9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89ef2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89ef2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89ef2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d1ce9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (1259 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055647dcc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055647dcc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055647dcc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7651849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76518a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7651849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7651831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055647dc59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055647dc59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055647dc3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055647d8ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055647d8edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7651832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76518330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76518330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055647d8eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (1260 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ea964eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ea964be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ea964f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e94e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e94ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e94e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e94e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ea95e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ea95e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ea95c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ea9278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ea9278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e94e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e94e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e94e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ea9278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (1261 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b19467eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b19464e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b1946862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1131049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11310a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1131049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1131031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b193fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b193fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b193e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b19091e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b19091b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1131032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11310330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11310330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b19091a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (1262 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559df4cadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559df4caae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559df4cae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a29e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a29ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a29e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a29e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559df4c43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559df4c43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559df4c288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559df48d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559df48d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a29e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a29e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a29e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559df48d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (1263 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9d2515eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9d2512e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9d251662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5041533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f504158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5041533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f504151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9d24abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9d24aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9d24908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9d213fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9d213fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f504151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f504151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f504151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9d213fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (1264 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vs
# | ...
# `---data was truncated (10240/23775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0ecb9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0ecb97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0ecb9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9062533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f906258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9062533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f906251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0ecb30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0ecb30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0ecb158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0ec7c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0ec7c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f906251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f906251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f906251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0ec7c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (1265 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a85a6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a85a6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a85a6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f051df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f051df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f051df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f051deed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a85a04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a85a04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a859e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a85698e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a85698b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f051deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f051deef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f051deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a85698a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (1266 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   s
# | ...
# `---data was truncated (10240/69534) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4ee43beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4ee438e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4ee43c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfb0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfb0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfb0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfb0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4ee3d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4ee3d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4ee3b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4ee065e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4ee065b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfb0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfb0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfb0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4ee065a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (1267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557512fcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557512fcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557512fd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9255c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9255ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9255c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9255c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557512f65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557512f65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557512f4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557512bf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557512bf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9255c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9255c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9255c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557512bf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (1268 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dd56a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560dd56a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560dd56a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff17c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff17c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff17c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff17c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dd563dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560dd563da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560dd56228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560dd52d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560dd52d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff17c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff17c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff17c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dd52d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (1269 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca08b95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca08b92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca08b9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cf5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cf56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cf5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cf5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca08b2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca08b2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca08b108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca087bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca087bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cf5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cf56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cf56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca087bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (1270 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e44d669eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e44d666e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e44d66a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bac049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bac0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bac049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bac031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e44d5ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e44d5ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e44d5e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e44d293e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e44d293b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0bac032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bac0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bac0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e44d293a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (1271 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592fab4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592fab4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592fab5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a33933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a3398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a33933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a3391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592faae5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592faae5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592faaca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592fa779e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592fa779b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a3391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a3391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a3391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592fa779a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (1272 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/31868) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f81c0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f81c09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f81c0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1bfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1bfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1bfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1bfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f81ba2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f81ba2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f81b878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f81836e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f81836b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1bfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1bfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1bfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f81836a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (1273 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b12ad9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b12ad9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b12ad9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f213fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f213fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f213fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f213fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b12ad34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b12ad34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b12ad198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b12a9c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b12a9c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f213fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f213fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f213fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b12a9c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (1274 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561156075eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561156072e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056115607662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa593049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5930a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa593049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa593031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056115600bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056115600ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561155ff08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561155c9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561155c9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa593032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5930330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5930330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561155c9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (1275 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0,
# | ...
# `---data was truncated (10240/69839) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650e3808eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650e3805e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650e380962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0871e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0871ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0871e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0871e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650e379ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650e379ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650e37838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650e3432e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650e3432b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0871e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0871e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0871e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650e3432a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (1276 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %o
# | ...
# `---data was truncated (10240/65883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055839ed6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055839ed6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055839ed6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd96133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd9618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd96133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd9611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055839ed03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055839ed03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055839ece88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055839e997e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055839e997b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd9611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd9611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd9611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055839e997a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (1277 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a35599eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a35596e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a3559a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2493733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f249378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2493733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f249371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a3552fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a3552fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a355148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a351c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a351c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f249371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f249371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f249371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a351c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (1278 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a644b24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a644b21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a644b2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9b5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9b50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9b5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9b5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a644ababbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a644abaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a644a9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a64474ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a64474eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9b5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9b50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9b50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a64474ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (1279 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1
# | ...
# `---data was truncated (10240/26772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622486e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622486e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622486e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f652bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f652bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f652bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f652bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056224867bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056224867ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622486608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056224830fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056224830fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f652bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f652bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f652bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056224830fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (1280 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/65072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564255c40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564255c3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564255c4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56b6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56b6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56b6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56b6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564255bd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564255bd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564255bbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056425586ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056425586ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56b6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56b6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56b6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056425586aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (1281 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bd89bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bd89b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bd89bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dee449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dee4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dee449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dee431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bd8951bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bd8951a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bd89368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bd85e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bd85e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dee432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dee4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dee4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bd85e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (1282 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563ffe32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563ffe2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563ffe3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c66f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c66f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c66f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c66f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563ffdc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563ffdc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563ffdad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563ffa5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563ffa5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c66f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c66f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c66f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563ffa5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (1283 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7a0c68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7a0c65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7a0c6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faeb0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faeb0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faeb0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faeb0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7a0bfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7a0bfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7a0be38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7a0892e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7a0892b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faeb0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faeb0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faeb0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7a0892a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (1284 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558386b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558386afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558386b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fc4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fc48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fc4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fc4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555838648bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555838648a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055583862d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558382dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558382dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5fc4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fc48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fc48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558382dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (1285 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627418c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627418c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627418c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35a0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35a078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35a0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35a071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056274185abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056274185aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056274183f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627414eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627414eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35a071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35a071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35a071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627414eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (1286 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649bcd67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649bcd64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649bcd6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2552b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2552b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2552b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2552b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649bccfdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649bccfda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649bcce28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649bc991e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649bc991b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2552b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2552b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2552b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649bc991a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (1287 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <v
# | ...
# `---data was truncated (10240/22290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623fccdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623fccd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623fccdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95d0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95d0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95d0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95d0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623fcc72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623fcc72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623fcc578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623fc906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623fc906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95d0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95d0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95d0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623fc906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (1288 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571c503deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571c503ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571c503e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad5ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad5ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad5ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad5ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571c4fd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571c4fd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571c4fb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571c4c67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571c4c67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad5ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad5ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad5ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571c4c67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (1289 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsc
# | ...
# `---data was truncated (10240/65905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a67d118eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a67d115e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a67d11962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ac6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ac6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ac6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ac6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a67d0aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a67d0aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a67d0938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a67cd42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a67cd42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ac6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ac6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ac6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a67cd42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (1290 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc8d2dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc8d2d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc8d2dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f08705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f0875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f08705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f086ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc8d271bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc8d271a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc8d2568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc8cf05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc8cf05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f086eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f086ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f086ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc8cf05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (1291 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055facb454eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055facb451e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055facb45562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbbe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbbe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbbe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbbe31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055facb3eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055facb3eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055facb3cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055facb07ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055facb07eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbbe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbbe31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbbe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055facb07ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (1292 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0)
# |   %2 = extractvalue { <8 x half>, <8 x half> } %1, 0
# |   %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0
# |   %4 = extractvalue { <8 x half>, <8 x half> } %1, 1
# |   %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1
# |   ret %struct.float16x8x2_t %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0)
# |   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
# |   %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0
# |   %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
# |   %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1
# |   %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
# |   %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2
# |   %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
# |   %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3
# |   ret %struct.uint8x16x4_t %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.uint32x4x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.uint32x4x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0
# |   store [2 x <4 x i32>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0
# |   %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.int8x16x4_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.int8x16x4_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0
# |   store [4 x <16 x i8>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false)
# |   %3 = load %struct.int8x16x4_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.int8x16x4_t %3, 0, 0
# |   %5 = extractvalue %struct.int8x16x4_t %3, 0, 1
# |   %6 = extractvalue %struct.int8x16x4_t %3, 0, 2
# |   %7 = extractvalue %struct.int8x16x4_t %3, 0, 3
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.float16x8x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.float16x8x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0
# |   store [2 x <8 x half>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.float16x8x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.float16x8x2_t %3, 0, 0
# |   %5 = extractvalue %struct.float16x8x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %values.addr = alloca ptr, align 4
# |   %v = alloca %struct.uint16x8x2_t, align 8
# |   %tmp = alloca %struct.uint16x8x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %values, ptr %values.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0)
# |   %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0
# |   %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0
# |   %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1
# |   %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1
# |   store %struct.uint16x8x2_t %5, ptr %tmp, align 8
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false)
# |   %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0
# |   %6 = load <8 x i16>, ptr %arrayidx, align 8
# |   %7 = load ptr, ptr %values.addr, align 4
# |   %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0
# |   store <8 x i16> %6, ptr %arrayidx1, align 8
# |   %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1
# |   %8 = load <8 x i16>, ptr %arrayidx3, align 8
# |   %9 = load ptr, ptr %values.addr, align 4
# |   %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1
# |   store <8 x i16> %8, ptr %arrayidx4, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %ref.tmp = alloca %struct.int32x4x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0)
# |   %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0
# |   %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1
# |   %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1
# |   store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8
# |   %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0
# |   %6 = load <4 x i32>, ptr %arrayidx, align 8
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000056550b845eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056550b842e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056550b84662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bf1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bf158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bf1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bf151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056550b7dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056550b7dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056550b7c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056550b46fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056550b46fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bf151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bf151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bf151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056550b46fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (1293 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a06ced8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a06ced5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a06ced962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f361781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36178725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f361781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3617803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a06ce6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a06ce6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a06ce538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a06cb02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a06cb02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3617804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36178050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36178050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a06cb02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (1294 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>,
# | ...
# `---data was truncated (10240/11969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643ad5bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643ad5bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643ad5be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ce533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ce58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ce533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ce51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643ad553bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643ad553a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643ad5388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643ad1e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643ad1e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18ce51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ce51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ce51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643ad1e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (1295 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 nou
# | ...
# `---data was truncated (10240/27442) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557848a24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557848a21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557848a2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe38533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe3858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe38533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe3851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578489babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578489baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055784899f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055784864ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055784864eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe3851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe3851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe3851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055784864ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (1296 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556e66fa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e66f9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e66fa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda6221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda622725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda6221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda62203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e66f36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e66f36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e66f1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e66bcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e66bcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda62204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda622050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda622050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e66bcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (1297 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/77054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d690b02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d690affe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d690b0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb71d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb71d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb71d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb71d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d690a98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d690a98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d690a7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d69072ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d69072cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb71d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb71d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb71d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d69072ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (1298 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loca
# | ...
# `---data was truncated (10240/18587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589653e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589653dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589653e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4780305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f478035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4780305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47802ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558965378bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558965378a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055896535d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055896500ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055896500cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47802eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47802ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47802ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055896500ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (1299 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca
# | ...
# `---data was truncated (10240/12137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589fe635eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589fe632e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589fe63662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff721f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff721f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff721f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff721f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589fe5cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589fe5cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589fe5b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589fe25fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589fe25fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff721f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff721f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff721f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589fe25fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (1300 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055605bf25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055605bf22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055605bf2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0fc81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0fc8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0fc81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0fc803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055605bebbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055605bebba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055605bea08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055605bb4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055605bb4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0fc804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0fc8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0fc8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055605bb4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (1301 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %value.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576)
# |   %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1
# |   store <2 x i64> %3, ptr %0, align 8
# |   %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = load <4 x i32>, ptr %value.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2)
# |   store <4 x i32> %3, ptr %0, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4
# | 
# | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591af352eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591af34fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591af35362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb696249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6962a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb696249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb696231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591af2e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591af2e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591af2cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591aef7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591aef7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb696232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6962330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6962330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591aef7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (1302 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx
# | ...
# `---data was truncated (10240/75125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ff3f4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ff3f4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ff3f4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56b9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56b938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56b9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56b931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ff3ee3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ff3ee3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ff3ec88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ff3b77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ff3b77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56b931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56b931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56b931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ff3b77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (1303 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d45a73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d45a70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d45a7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c92533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c9258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c92533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c9251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d45a09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d45a09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d459ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d4569de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d4569db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c9251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c9251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c9251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d4569da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (1304 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116957) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a33641beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a336418e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a33641c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8a2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8a218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8a2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8a211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3363b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3363b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3363968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a336045e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a336045b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8a211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8a211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8a211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a336045a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (1305 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl
# | ...
# `---data was truncated (10240/78896) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600eac46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600eac43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600eac4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5799449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57994a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5799449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5799431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600eabdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600eabdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600eabc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600ea870e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600ea870b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5799432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57994330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57994330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600ea870a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (1306 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627adfb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627adfb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627adfb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcf5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcf518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcf5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcf511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627adf4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627adf4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627adf2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627adbdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627adbdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcf511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcf511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcf511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627adbdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (1307 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590d15e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590d15e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590d15ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1edaa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1edaa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1edaa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1edaa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590d157fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590d157fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590d15648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590d1213e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590d1213b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1edaa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1edaa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1edaa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590d1213a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (1308 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/68255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056491b421eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056491b41ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056491b42262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3357333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f335738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3357333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f335731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056491b3b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056491b3b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056491b39c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056491b04be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056491b04bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f335731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f335731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f335731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056491b04ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (1309 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbcd4c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbcd4c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbcd4c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e95249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e952a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e95249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e95231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbcd45ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbcd45ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbcd4438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbcd0f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbcd0f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e95232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e952330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e952330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbcd0f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (1310 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f48adceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f48ad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f48add62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa167249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1672a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa167249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa167231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f48a72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f48a72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f48a578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f48706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f48706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa167232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1672330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1672330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f48706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (1311 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fff7e0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fff7e0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fff7e0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc226133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc226133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fff7da3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fff7da3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fff7d888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fff7a37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fff7a37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc22611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fff7a37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (1312 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op
# | ...
# `---data was truncated (10240/154517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555653e74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555653e71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555653e7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8670449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86704a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8670449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8670431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555653e0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555653e0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555653def8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555653a9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555653a9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8670432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86704330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86704330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555653a9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (1313 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585d1bb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585d1bb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585d1bb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f320a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f320a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f320a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f320a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585d1b4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585d1b4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585d1b338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585d17e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585d17e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f320a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f320a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f320a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585d17e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (1314 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df01455eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df01452e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df0145662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97fb705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97fb75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97fb705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97fb6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df013ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df013eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df013d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df0107fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df0107fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97fb6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97fb6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97fb6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df0107fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (1315 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccaf228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccaf225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccaf22962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3d6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccaf1bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccaf1bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccaf1a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccaee52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccaee52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccaee52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (1316 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1ec2d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1ec2d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1ec2d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f4bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f4bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f4bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f4beed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1ec26cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1ec26ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1ec2518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1ebf00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1ebf00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f4beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f4beef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f4beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1ebf00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (1317 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ef2ba0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ef2b9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ef2ba162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe0a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe0a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe0a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe0a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ef2b36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ef2b36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ef2b1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ef27cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ef27cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe0a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe0a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe0a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ef27caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (1318 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsa
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e109c1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e109c1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e109c1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f797e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f797e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f797e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f797e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e109bb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e109bb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e109b998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e109848e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e109848b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f797e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f797e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f797e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e109848a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (1319 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c4a3aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c4a3a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c4a3ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb501e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb501ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb501e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb501e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c4a342bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c4a342a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c4a3278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c49fd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c49fd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb501e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb501e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb501e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c49fd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-neon-vst.c (1320 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon      -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <4 x i16>
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x3_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0
# |   store [3 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %4 = bitcast <8 x i8> %1 to <4 x i16>
# |   %5 = bitcast <8 x i8> %2 to <4 x i16>
# |   %6 = bitcast <8 x i8> %3 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x4_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0
# |   store [4 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3
# |   %4 = load <8 x i8>, ptr %arrayidx6, align 8
# |   %5 = bitcast <8 x i8> %1 to <4 x i16>
# |   %6 = bitcast <8 x i8> %2 to <4 x i16>
# |   %7 = bitcast <8 x i8> %3 to <4 x i16>
# |   %8 = bitcast <8 x i8> %4 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float32x2x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <2 x float>
# |   %4 = bitcast <8 x i8> %2 to <2 x float>
# |   call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %s
# | ...
# `---data was truncated (10240/108866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557ba2feeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ba2febe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ba2fef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22b9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22b9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22b9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22b9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ba2f84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ba2f84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ba2f698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ba2c18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ba2c18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22b9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22b9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22b9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ba2c18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (1321 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cd4f00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cd4efde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cd4f0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0eb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0eb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0eb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0eb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cd4e96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cd4e96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cd4e7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cd4b2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cd4b2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0eb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0eb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0eb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cd4b2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (1322 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = and <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = and <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = and <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = and <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr
# | ...
# `---data was truncated (10240/11060) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605d8baeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605d8babe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605d8baf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe22af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe22af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe22af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe22aeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605d8b44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605d8b44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605d8b298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605d87d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605d87d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe22aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe22aeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe22aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605d87d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (1323 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7235fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7235f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7235fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04d1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04d138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04d1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04d131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e723591bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e723591a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7235768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e723225e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e723225b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04d131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04d131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04d131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e723225a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (1324 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1aaf58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1aaf55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1aaf5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bcbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bcbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bcbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bcbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1aaeeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1aaeeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1aaed38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1aab82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1aab82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bcbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bcbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bcbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1aab82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (1325 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab64e23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab64e20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab64e2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27c1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27c18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27c1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27c1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab64db9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab64db9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab64d9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab64a4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab64a4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27c1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27c18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27c18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab64a4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (1326 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bcb970eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bcb96de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bcb97162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe660533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe66058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe660533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe66051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bcb906bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bcb906a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bcb8eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bcb59ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bcb59ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe66051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe66051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe66051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bcb59aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (1327 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/134736) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7812adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7812aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7812ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb479533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb47958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb479533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb47951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a781243bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a781243a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7812288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a780ed7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a780ed7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb47951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb47951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb47951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a780ed7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (1328 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bc6637eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bc6634e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bc663862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4231933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f423198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4231933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f423191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bc65cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bc65cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bc65b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bc6261e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bc6261b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f423191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f423191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f423191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bc6261a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (1329 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561aff2e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561aff2e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561aff2e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb514133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb51418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb514133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb51411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aff27cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561aff27ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561aff2618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561afef10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561afef10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb51411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb51411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb51411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561afef10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (1330 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cae5f2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cae5f2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cae5f2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc15321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1532725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc15321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc153203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cae5ec4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cae5ec4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cae5ea98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cae5b58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cae5b58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc153204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1532050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1532050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cae5b58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (1331 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dda127eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dda124e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dda12862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b73249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b73249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b73231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dda0bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dda0bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dda0a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557dd9d51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557dd9d51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b73232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dd9d51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (1332 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ed0170eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ed016de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ed017162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6d4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6d46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6d4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6d4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ed0106bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ed0106a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ed00eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ecfd9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ecfd9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6d4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6d46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6d46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ecfd9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (1333 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ea5637eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ea5634e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ea563862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5130105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f513015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5130105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51300ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ea55cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ea55cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ea55b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ea5261e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ea5261b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51300eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51300ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51300ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ea5261a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (1334 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3a7032eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3a702fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3a703362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f065c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f065c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f065c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f065c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3a6fc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3a6fc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3a6fad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3a6c5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3a6c5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f065c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f065c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f065c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3a6c5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (1335 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560de93b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560de93b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560de93b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a24d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a24d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a24d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a24d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560de934bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560de934ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560de93308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560de8fdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560de8fdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a24d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a24d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a24d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560de8fdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (1336 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574895c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574895c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574895c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb85b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb85b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb85b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb85b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055748955ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055748955ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574895438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574891f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574891f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb85b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb85b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb85b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574891f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (1337 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562a2acbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562a2ac8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562a2acc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e4a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e4a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e4a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e4a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562a2a61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562a2a61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562a2a468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562a26f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562a26f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e4a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e4a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e4a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562a26f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (1338 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svzero_zt() #0 {
# | entry:
# |   call void @llvm.aarch64.sme.zero.zt(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bcf1068eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcf1065e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcf106962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4d2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4d26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4d2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4d2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcf0ffebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcf0ffea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcf0fe38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcf0c92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcf0c92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4d2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4d26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4d26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcf0c92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (1339 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d5610ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d56109e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d5610d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f6721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f672725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f6721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f67203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d560a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d560a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d560878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d55d36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d55d36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f67204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f672050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f672050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d55d36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (1340 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557be863feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557be863ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557be864062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdaa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdaa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdaa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdaa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557be85d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557be85d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557be85ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557be8269e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557be8269b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdaa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdaa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdaa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557be8269a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (1341 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba384d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba384cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba384d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f738df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f738df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f738df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f738df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba38468bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba38468a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba3844d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba380fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba380fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f738df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f738df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f738df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba380fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (1342 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.
# | ...
# `---data was truncated (10240/16654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569783f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569783f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569783f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe01ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe01ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe01ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe01eced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055697838bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055697838ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569783708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055697801fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055697801fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe01eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe01ecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe01ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055697801fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (1343 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d7d751eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d7d74ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d7d75262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5cf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5cf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5cf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5cf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d7d6e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d7d6e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d7d6cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d7d37be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d7d37bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5cf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5cf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5cf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d7d37ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (1344 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %
# | ...
# `---data was truncated (10240/13308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561be6295eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561be6292e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561be629662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d24b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d24b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d24b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d24b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561be622bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561be622ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561be62108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561be5ebfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561be5ebfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d24b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d24b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d24b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561be5ebfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (1345 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c99a72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c99a6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c99a7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f357b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f357b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f357b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f357b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c99a08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c99a08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c999ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c9969ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c9969cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f357b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f357b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f357b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c9969ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (1346 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr =
# | ...
# `---data was truncated (10240/124514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609e58a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609e58a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609e58a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb79ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb79aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb79ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb79ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609e583dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609e583da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609e58228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609e54d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609e54d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb79ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb79ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb79ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609e54d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (1347 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3,
# | ...
# `---data was truncated (10240/29443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634e504ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634e5049e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634e504d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a51a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a51aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a51a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a51a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634e4fe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634e4fe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634e4fc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634e4c76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634e4c76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a51a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a51a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a51a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634e4c76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (1348 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b37f570eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b37f56de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b37f57162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82c7d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82c7d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82c7d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82c7ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b37f506bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b37f506a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b37f4eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b37f19ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b37f19ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82c7ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82c7cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82c7cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b37f19aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (1349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604af29aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604af297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604af29b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44ced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44ced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44ced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44ced1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604af230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604af230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604af2158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604aeec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604aeec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44ced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44ced1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44ced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604aeec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (1350 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4f5eb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4f5eaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4f5eb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4564e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4564ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4564e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4564e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4f5e47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4f5e47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4f5e2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4f5adbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4f5adbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4564e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4564e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4564e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4f5adba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (1351 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056041a4a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056041a4a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056041a4a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0334905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f033495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0334905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03348ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056041a439bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056041a439a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056041a41e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056041a0cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056041a0cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03348eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03348ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03348ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056041a0cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (1352 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe29c02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe29bffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe29c0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41a2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41a2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41a2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41a2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe29b98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe29b98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe29b7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe2982ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe2982cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41a2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41a2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41a2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe2982ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (1353 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, 
# | ...
# `---data was truncated (10240/30635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055944049feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055944049ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594404a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd14a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd14a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd14a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd14a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559440435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559440435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055944041a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594400c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594400c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd14a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd14a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd14a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594400c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (1354 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dc22bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562dc22bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562dc22be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f349b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f349b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f349b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f349b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dc2253bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562dc2253a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562dc22388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562dc1ee7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562dc1ee7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f349b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f349b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f349b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dc1ee7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (1355 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 7)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x
# | ...
# `---data was truncated (10240/11356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562cfb798eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cfb795e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cfb79962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74aba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74abaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74aba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74aba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cfb72ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cfb72ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cfb7138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cfb3c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cfb3c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74aba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74aba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74aba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cfb3c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (1356 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055842e73deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055842e73ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055842e73e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bd3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bd3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bd3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bd3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055842e6d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055842e6d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055842e6b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055842e367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055842e367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0bd3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bd3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bd3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055842e367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (1357 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586984e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586984e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586984ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff516c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff516ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff516c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff516c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055869847fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055869847fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586984648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558698113e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558698113b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff516c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff516c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff516c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558698113a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (1358 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9a8346eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9a8343e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9a834762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d49b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d49b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d49b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d49b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9a82dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9a82dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9a82c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9a7f70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9a7f70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d49b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d49b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d49b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9a7f70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (1359 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f127399eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f127396e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f12739a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a52733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a5278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a52733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a5271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f12732fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f12732fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1273148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f126fc3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f126fc3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a5271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a5271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a5271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f126fc3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (1360 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <4 x float> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = fcmp oeq <4 x float> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = icmp eq <4 x i32> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = 
# | ...
# `---data was truncated (10240/125481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566157d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566157d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566157d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46c9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46c9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46c9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46c9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055661576cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055661576ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566157518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556615400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556615400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46c9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46c9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46c9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556615400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (1361 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae2c428eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae2c425e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae2c42962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71da133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71da18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71da133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71da11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae2c3bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae2c3bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae2c3a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae2c052e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae2c052b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71da11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71da11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71da11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae2c052a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (1362 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3
# | ...
# `---data was truncated (10240/14330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0616bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0616bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0616c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5330649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53306a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5330649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5330631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c061655bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c061655a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c06163a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0612e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0612e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5330632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53306330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53306330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0612e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (1363 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055603aa69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055603aa66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055603aa6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a51a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a51aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a51a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a51a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055603a9ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055603a9ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055603a9e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055603a693e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055603a693b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a51a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a51a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a51a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055603a693a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (1364 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559badceeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559badcebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559badcef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bbaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bbaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bbaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bbaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559badc84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559badc84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559badc698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bad918e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bad918b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bbaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bbaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bbaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bad918a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (1365 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb8726aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb87267e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb8726b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fded9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fded96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fded9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fded9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb87200bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb87200a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb871e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb86e94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb86e94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fded9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fded96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fded96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb86e94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (1366 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adecb68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055adecb65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055adecb6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b3aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b3aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b3aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b3aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adecafebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055adecafea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055adecae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055adec792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055adec792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b3aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b3aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b3aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adec792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (1367 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i1
# | ...
# `---data was truncated (10240/182173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bba167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bba164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bba16862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd230b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd230b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd230b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd230b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bba0fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bba0fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bba0e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bb9d91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bb9d91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd230b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd230b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd230b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bb9d91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (1368 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a635687eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a635684e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a63568862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb409933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb40998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb409933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb40991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a63561dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a63561da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6356028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6352b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6352b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb40991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb40991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb40991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6352b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (1369 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f08f71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f08f6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f08f7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7322649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73226a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7322649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7322631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f08f07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f08f07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f08eec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f08b9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f08b9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7322632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73226330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73226330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f08b9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (1370 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9a7b45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9a7b42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9a7b4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfd2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfd2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfd2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfd2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9a7adbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9a7adba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9a7ac08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9a776fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9a776fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfd2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfd2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfd2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9a776fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (1371 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/151245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d263919eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d263916e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d26391a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf52b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf52b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf52b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf52b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2638afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2638afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2638948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d263543e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d263543b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf52b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf52b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf52b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d263543a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (1372 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 nounde
# | ...
# `---data was truncated (10240/26592) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619b232aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619b2327e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619b232b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41cee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41cee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41cee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41cee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619b22c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619b22c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619b22a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619b1f54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619b1f54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41cee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41cee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41cee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619b1f54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (1373 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568003e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568003e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568003e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe8b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe8b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe8b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe8b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055680037bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055680037ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568003608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055680000fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055680000fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe8b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe8b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe8b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055680000fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (1374 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613fc87eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613fc87be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613fc87f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f418141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41814725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f418141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4181403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613fc814bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613fc814a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613fc7f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613fc4a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613fc4a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4181404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41814050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41814050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613fc4a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (1375 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c6041deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c6041ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c6041e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07aa649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07aa6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07aa649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07aa631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c603b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c603b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c603988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c60047e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c60047b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07aa632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07aa6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07aa6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c60047a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (1376 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b742f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b742f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b742f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc8c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc8c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc8c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc8c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b7428abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b7428aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b7426f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b73f1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b73f1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc8c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc8c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc8c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b73f1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (1377 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055842540aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558425407e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055842540b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa44d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa44d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa44d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa44d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584253a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584253a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584253858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558425034e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558425034b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa44d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa44d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa44d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558425034a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (1378 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c490999eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c490996e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c49099a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cb6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cb6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cb6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cb6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c49092fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c49092fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4909148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4905c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4905c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cb6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cb6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cb6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4905c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (1379 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557031de2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557031ddfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557031de362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc127933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc12798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc127933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc12791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557031d78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557031d78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557031d5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557031a0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557031a0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc12791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc12791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc12791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557031a0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (1380 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2q_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svld2q_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2q_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | d
# | ...
# `---data was truncated (10240/75038) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055df7071ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df70719e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df7071d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92ee249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92ee2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92ee249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92ee231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df706b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df706b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df706978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df70346e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df70346b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92ee232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92ee2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92ee2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df70346a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (1381 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a772e90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a772e8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a772e9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f775c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f775c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f775c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f775c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a772e26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a772e26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a772e0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a772abae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a772abab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f775c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f775c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f775c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a772abaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (1382 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/12050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb383f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb383f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb383f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b4dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b4dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b4dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b4dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb3838cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb3838ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb383718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb38020e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb38020b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b4dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b4dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b4dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb38020a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (1383 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561117e75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561117e72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561117e7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d24333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d2438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d24333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d2431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561117e0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561117e0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561117df08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561117a9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561117a9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d2431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d2431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d2431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561117a9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (1384 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556e0ec2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556e0ebfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556e0ec362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4c8c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4c8c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4c8c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4c8c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556e0e58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556e0e58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556e0e3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556e0aece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556e0aecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4c8c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4c8c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4c8c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556e0aeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (1385 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c67605eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c67605be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c67605f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9392049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9392049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9392031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c675ff4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c675ff4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c675fd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c675c88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c675c88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9392032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93920330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c675c88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (1386 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ca449feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ca449ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ca44a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2d5705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2d575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2d5705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2d56ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ca4435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ca4435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ca441a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ca40c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ca40c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2d56eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2d56ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2d56ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ca40c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (1387 of 27910)
******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# |  #0 0x0000558edd5b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558edd5aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558edd5b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85c3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85c3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85c3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85c3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558edd547bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558edd547a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558edd52c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558edd1dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558edd1dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85c3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85c3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85c3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558edd1dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (1388 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d625979eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d625976e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d62597a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b8c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b8c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b8c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b8c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d62590fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d62590fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6258f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6255a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6255a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b8c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b8c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b8c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6255a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (1389 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055820a6a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055820a69fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055820a6a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4521849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45218a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4521849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4521831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055820a638bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055820a638a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055820a61d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055820a2cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055820a2ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4521832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45218330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45218330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055820a2cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (1390 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,102
# | ...
# `---data was truncated (10240/10769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055619b7cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055619b7cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055619b7ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda65c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda65ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda65c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda65c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055619b763bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055619b763a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055619b7488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055619b3f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055619b3f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda65c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda65c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda65c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055619b3f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (1391 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   
# | ...
# `---data was truncated (10240/92362) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c2ac75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c2ac72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c2ac7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a01e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a01ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a01e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a01e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c2ac0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c2ac0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c2abf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c2a89fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c2a89fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a01e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a01e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a01e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c2a89fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (1392 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be8198eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be8198be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be8198f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f442a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f442a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f442a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f442a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be81924bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be81924a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be819098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be815b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be815b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f442a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f442a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f442a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be815b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (1393 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c24bcbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c24bcb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c24bcbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a41a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a41aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a41a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a41a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c24bc52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c24bc52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c24bc378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c24b8e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c24b8e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a41a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a41a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a41a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c24b8e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (1394 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr =
# | ...
# `---data was truncated (10240/154509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f8cf11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f8cf0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f8cf1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4c0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4c00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4c0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4c0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f8cea7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f8cea7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f8ce8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f8cb3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f8cb3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4c0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4c00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4c00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f8cb3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (1395 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055debfe73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055debfe70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055debfe7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13cb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13cb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13cb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13cb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055debfe09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055debfe09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055debfdee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055debfa9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055debfa9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13cb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13cb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13cb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055debfa9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (1396 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a50b74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a50b71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a50b7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74bd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a50b0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a50b0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a50aef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a5079ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a5079eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a5079ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (1397 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600819d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600819cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600819d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d55649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d55649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d55631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560081967bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560081967a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056008194c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600815fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600815fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d55632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d556330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600815fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (1398 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556418a73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556418a70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556418a7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa8db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa8db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa8db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa8db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556418a09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556418a09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564189ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055641869de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055641869db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa8db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa8db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa8db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055641869da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (1399 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %v
# | ...
# `---data was truncated (10240/23064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2e7359eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2e7356e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2e735a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7a0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7a04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7a0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7a0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2e72efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2e72efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2e72d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2e6f83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2e6f83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7a0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7a04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7a04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2e6f83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (1400 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %v
# | ...
# `---data was truncated (10240/142327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d35ef6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d35ef6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d35ef6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f935f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f935f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f935f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f935f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d35ef04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d35ef04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d35eee98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d35eb98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d35eb98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f935f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f935f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f935f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d35eb98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (1401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561df0168eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561df0165e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561df016962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37f5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37f58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37f5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37f5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561df00febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561df00fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561df00e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561defd92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561defd92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37f5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37f58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37f58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561defd92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (1402 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnda.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i)
# |   store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndp.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i)
# |   store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2)
# |   store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x half>
# |   store <4 x half> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__ret.i3 = alloca <8 x half>, align 16
# |   %__p0.addr.i.i = alloca <4 x float>, align 16
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 16
# |   %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   %6 = fptrunc <4 x float> %5 to <4 x half>
# |   store <4 x half> %6, ptr %ref.tmp.i.i, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %7, ptr %__ret.i.i, align 8
# |   %8 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %2, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %8, ptr %__p1.addr.i2, align 8
# |   %9 = load <4 x half>, ptr %__p0.addr.i1, align 8
# |   %10 = load <4 x half>, ptr %__p1.addr.i2, align 8
# |   %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i3, align 16
# |   %11 = load <8 x half>, ptr %__ret.i3, align 16
# |   store <8 x half> %11, ptr %__ret.i, align 16
# |   %12 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fpext <4 x half> %2 to <4 x float>
# |   store <4 x float> %3, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__ret.i2 = alloca <4 x half>, align 8
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x half>, ptr %__ret.i2, align 8
# |   store <4 x half> %4, ptr %__p0.addr.i.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %7 = fpext <4 x half> %6 to <4 x float>
# |   store <4 x float> %7, ptr %ref.tmp.i.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %8, ptr %__ret.i.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i.i, align 16
# |   store <4 x float> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005569afc59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569afc56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569afc5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc0c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc0c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc0c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc0c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569afbefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569afbefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569afbd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569af883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569af883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc0c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc0c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc0c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569af883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (1403 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608d2384eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608d2381e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608d238562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0e621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0e62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0e621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0e6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608d231abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608d231aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608d22ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608d1faee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608d1faeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0e6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0e62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0e62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608d1faea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (1404 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631fb9edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631fb9eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631fb9ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f651801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65180725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f651801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6518003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631fb983bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631fb983a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631fb9688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631fb617e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631fb617b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6518004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65180050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65180050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631fb617a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (1405 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555563fafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555563face85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555563fb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6797249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67972a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6797249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6797231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555563f45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555563f45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555563f2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555563bd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555563bd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6797232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67972330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67972330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555563bd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (1406 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2c730eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2c730be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2c730f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35fb305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35fb35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35fb305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35fb2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2c72a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2c72a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2c72898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2c6f38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2c6f38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35fb2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35fb2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35fb2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2c6f38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (1407 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa5a664eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa5a661e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa5a66562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5077449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50774a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5077449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5077431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa5a5fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa5a5faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa5a5df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa5a28ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa5a28eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5077432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50774330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50774330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa5a28ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (1408 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <
# | ...
# `---data was truncated (10240/117389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055985364feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055985364ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055985365062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a7ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a7ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a7ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a7ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598535e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598535e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598535ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559853279e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559853279b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a7ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a7ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a7ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559853279a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (1409 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, 
# | ...
# `---data was truncated (10240/62087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dcb720eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dcb71de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dcb72162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac75133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac7518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac75133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac7511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dcb6b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dcb6b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dcb69b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dcb34ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dcb34ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac7511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac7511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac7511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dcb34aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (1410 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055930d72deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055930d72ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055930d72e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f29849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f298a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f29849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f29831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055930d6c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055930d6c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055930d6a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055930d357e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055930d357b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f29832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f298330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f298330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055930d357a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (1411 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e74b3a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e74b3a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e74b3a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a59f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a59f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a59f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a59eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e74b33bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e74b33ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e74b3208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e74afcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e74afcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a59eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a59eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a59eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e74afcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (1412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/79861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cc5481eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cc547ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cc548262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b7d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b7d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b7d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b7d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cc5417bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cc5417a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cc53fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cc50abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cc50abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b7d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b7d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b7d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cc50aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (1413 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564607a80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564607a7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564607a8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6021c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6021c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6021c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6021c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564607a16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564607a16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646079fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646076aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646076aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6021c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6021c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6021c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646076aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (1414 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645d574eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645d574be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645d574f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5647733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f564778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5647733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f564771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645d56e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645d56e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645d56c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645d5378e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645d5378b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f564771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f564771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f564771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645d5378a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (1415 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055850181feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055850181ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055850182062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17e161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17e16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17e161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17e1603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585017b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585017b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055850179a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558501449e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558501449b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17e1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17e16050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17e16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558501449a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (1416 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056333eaf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056333eaefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056333eaf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81a851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056333ea88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056333ea88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056333ea6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056333e71ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056333e71cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81a851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056333e71ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (1417 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6)
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6)
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__p1.addr.i.i = alloca <4 x half>, align 8
# |   %__p2.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %13, ptr %__ret.i.i, align 8
# |   %14 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <8 x half>, align 16
# |   %__p1.addr.i.i = alloca <8 x half>, align 16
# |   %__p2.addr.i.i = alloca <8 x half>, align 16
# |   %__ret.i.i = alloca <8 x half>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i.i, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i.i, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16
# |   store <8 x half> %13, ptr %__ret.i.i, align 16
# |   %14 = load <8 x half>, ptr %__ret.i.i, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1)
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1
# | ...
# `---data was truncated (10240/42739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005638acd59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638acd56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638acd5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a6bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a6bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a6bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a6beed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638accefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638accefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638accd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638ac983e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638ac983b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a6beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a6beef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a6beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638ac983a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (1418 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605a2b1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605a2b19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605a2b1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8972133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f897218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8972133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f897211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605a2ab2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605a2ab2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605a2a978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605a2746e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605a2746b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f897211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f897211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f897211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605a2746a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (1419 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562791b0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562791b0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562791b1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f4181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f418725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f4181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f41803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562791aa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562791aa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562791a8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562791739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562791739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f41804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f418050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f418050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562791739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (1420 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d784fc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d784fc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d784fc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2cbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2cbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2cbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2cbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d784f59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d784f59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d784f3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d784bede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d784bedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2cbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2cbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2cbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d784beda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (1421 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2
# | ...
# `---data was truncated (10240/94673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5b4a2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5b4a2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5b4a2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5b49c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5b49c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5b49a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5b4658e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5b4658b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5b4658a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (1422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2785cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2785cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2785ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86a8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86a8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86a8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86a8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b278563bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b278563a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2785488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2781f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2781f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86a8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86a8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86a8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2781f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (1423 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c69af90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c69af8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c69af9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51a5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c69af26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c69af26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c69af0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c69abbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c69abbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51a5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c69abbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (1424 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4ef75deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4ef75ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4ef75e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd14f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd14f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd14f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd14f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4ef6f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4ef6f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4ef6d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4ef387e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4ef387b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd14f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd14f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd14f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4ef387a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (1425 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055863b0f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055863b0f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055863b0fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0ba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0ba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0ba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0ba51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055863b08fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055863b08fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055863b0748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055863ad23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055863ad23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0ba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0ba51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0ba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055863ad23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (1426 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559df61feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559df61fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559df61ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f719a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f719a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f719a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f719a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559df6194bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559df6194a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559df61798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559df5e28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559df5e28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f719a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f719a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f719a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559df5e28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (1427 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, a
# | ...
# `---data was truncated (10240/71115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8ee9e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8ee9e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8ee9e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd2ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd2ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd2ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd2ba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8ee979bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8ee979a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8ee95e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8ee60de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8ee60db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd2ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd2ba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd2ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8ee60da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (1428 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1800b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1800b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1800b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f683b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f683b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f683b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f683b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d18004ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d18004ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1800338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d17fce2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d17fce2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f683b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f683b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f683b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d17fce2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (1429 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c89013eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c89010e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c8901462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98b3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98b318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98b3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98b311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c88fa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c88fa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c88f8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c88c3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c88c3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98b311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98b311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98b311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c88c3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (1430 of 27910)
******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | declare noundef zeroext i1 @_Z1av() #1
# | 
# | declare noundef zeroext i1 @_Z1bv() #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.expect.i64(i64, i64) #2
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true)
# |   br i1 %call.expval, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true)
# |   br i1 %call1.expval, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i1 @llvm.expect.i1(i1, i1) #2
# | 
# | declare noundef zeroext i1 @_Z1cv() #1
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1cv()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:                                          ; preds = %lor.lhs.false
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %lor.end
# | 
# | lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
# |   %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.end
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %if.then, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %if.then, label %lor.lhs.false2
# | 
# | lor.lhs.false2:                                   ; preds = %lor.lhs.false
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.lhs.false2, %lor.lhs.false, %entry
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.lhs.false2
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %dec = add nsw i32 %2, -1
# |   store i32 %dec, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:     
# | ...
# `---data was truncated (10240/28468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# |  #0 0x0000557964749eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557964746e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055796474a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a97933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a9798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a97933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a9791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579646dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579646dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579646c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557964373e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557964373b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a9791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a9791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a9791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557964373a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (1431 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d7809ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d78099e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d7809d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc12ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc12aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc12ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc12ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d78032bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d78032a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d780178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d77cc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d77cc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc12ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc12ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc12ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d77cc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (1432 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a3a5d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a3a5d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a3a5d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f16a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f16aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f16a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f16a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a3a569bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a3a569a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a3a54e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a3a1fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a3a1fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f16a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f16a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f16a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a3a1fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (1433 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b73cb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b73cade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b73cb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d20105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d2015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d20105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d200ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b73c46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b73c46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b73c2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b738dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b738dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d200eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d200ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d200ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b738daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (1434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff85d98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff85d95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff85d9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f8fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f8faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f8fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f8fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff85d2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff85d2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff85d138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff859c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff859c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f8fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f8fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f8fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff859c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (1435 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d151a12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d151a0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d151a1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75e9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75e918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75e9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75e911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1519a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1519a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d15198d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d15163ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d15163cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75e911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75e911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75e911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d15163ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (1436 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ef6224eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ef6221e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ef622562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09e2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09e218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09e2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09e211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ef61babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ef61baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ef619f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ef5e4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ef5e4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09e211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09e211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09e211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ef5e4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (1437 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/62956) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2b851aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2b8517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2b851b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde87849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde878a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde87849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde87831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2b84b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2b84b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2b84958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2b8144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2b8144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde87832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde878330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde878330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2b8144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (1438 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/126428) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556560c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556560c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556560c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fd7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fd74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fd7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fd7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555656059bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555656059a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055565603e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555655cede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555655cedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fd7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fd74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fd74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555655ceda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (1439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c703085eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c703082e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c70308662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7ff649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7ff6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7ff649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7ff631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c70301bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c70301ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7030008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c702cafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c702cafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7ff632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7ff6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7ff6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c702cafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (1440 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564063ebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564063eb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564063ebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6553533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f655358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6553533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f655351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564063e51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564063e51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564063e368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564063ae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564063ae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f655351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f655351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f655351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564063ae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (1441 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdffdbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdffdb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdffdbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3553f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3553f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3553f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3553f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdffd50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdffd50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdffd358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdff9e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdff9e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3553f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3553f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3553f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdff9e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (1442 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vs
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563258ed4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563258ed1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563258ed562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce9a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce9a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce9a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce9a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563258e6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563258e6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563258e4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563258afee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563258afeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce9a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce9a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce9a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563258afea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (1443 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a09505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a09502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a0950662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5810d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5810d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5810d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5810d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a0949bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a0949ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a094808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a0912fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a0912fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5810d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5810d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5810d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a0912fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (1444 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   ret <8 x half> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   ret <4 x float> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca half, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %3, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %3, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2,
# | ...
# `---data was truncated (10240/17297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055c9f5470eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9f546de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9f547162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa26eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa26eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa26eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa26eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9f5406bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9f5406a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9f53eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9f509ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9f509ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa26eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa26eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa26eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9f509aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (1445 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558aab2d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aab2cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aab2d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4630a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4630a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4630a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4630a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aab266bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558aab266a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558aab24b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558aaaefae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558aaaefab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4630a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4630a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4630a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558aaaefaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (1446 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056118b638eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056118b635e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056118b63962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3681a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3681aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3681a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3681a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056118b5cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056118b5cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056118b5b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056118b262e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056118b262b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3681a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3681a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3681a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056118b262a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (1447 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585062bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585062b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585062bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb345333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb34538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb345333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb34531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558506251bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558506251a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585062368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558505ee5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558505ee5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb34531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb34531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb34531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558505ee5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (1448 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644ead3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644ead3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644ead4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1a3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1a398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1a3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1a391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644eacd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644eacd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644eacba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644ea969e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644ea969b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1a391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1a391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1a391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644ea969a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (1449 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d68e5d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d68e5d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d68e5d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa485449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4854a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa485449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa485431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d68e56ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d68e56ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d68e5538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d68e202e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d68e202b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa485432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4854330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4854330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d68e202a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (1450 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558809f1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558809f1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558809f1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4194333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f419438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4194333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f419431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558809eb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558809eb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558809e988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558809b47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558809b47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f419431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f419431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f419431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558809b47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (1451 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fac1dfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fac1df9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fac1dfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7affc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7affca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7affc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7affc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fac1d92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fac1d92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fac1d778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fac1a26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fac1a26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7affc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7affc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7affc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fac1a26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (1452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align
# | ...
# `---data was truncated (10240/14145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f4a21ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f4a219e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f4a21d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67a0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67a0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67a0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67a0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f4a1b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f4a1b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f4a1978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f49e46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f49e46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67a0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67a0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67a0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f49e46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (1453 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ae1d64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ae1d61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ae1d6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29c9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29c98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29c9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29c9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ae1cfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ae1cfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ae1cdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ae198ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ae198eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29c9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29c98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29c98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ae198ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (1454 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef
# | ...
# `---data was truncated (10240/78336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4abb13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4abb10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4abb1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6824d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6824d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6824d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6824d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4abaa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4abaa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4aba8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4ab73de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4ab73db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6824d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6824d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6824d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4ab73da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (1455 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556259768eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556259765e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055625976962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2edb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2edb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2edb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2edb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562596febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562596fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562596e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556259392e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556259392b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2edb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2edb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2edb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556259392a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (1456 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b21bb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b21bb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b21bb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03bd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03bd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03bd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03bd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b21b4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b21b4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b21b338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b217e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b217e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03bd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03bd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03bd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b217e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (1457 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd99697eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd99694e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd9969862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb592e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb592ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb592e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb592e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd9962dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd9962da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd996128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd992c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd992c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb592e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb592e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb592e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd992c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (1458 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d41eb47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d41eb44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d41eb4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7db7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7db7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7db7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7db7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d41eaddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d41eadda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d41eac28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d41e771e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d41e771b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7db7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7db7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7db7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d41e771a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (1459 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631e36a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631e369fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631e36a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe33b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe33b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe33b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe33b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631e3638bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631e3638a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631e361d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631e32cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631e32ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe33b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe33b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe33b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631e32cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (1460 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643feb88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643feb85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643feb8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f806fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f806fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f806fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f806fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643feb1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643feb1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643feb038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643fe7b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643fe7b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f806fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f806fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f806fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643fe7b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (1461 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ae47eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ae47e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ae47eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb899249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb899249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb899231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ae4780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ae4780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ae47658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ae4414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ae4414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb899232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8992330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ae4414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (1462 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddff81eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddff81be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddff81f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f84449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f844a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f84449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f84431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddff7b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddff7b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddff7998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddff448e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddff448b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f84432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f844330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f844330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddff448a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (1463 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/43507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561227415eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561227412e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056122741662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5640849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56408a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5640849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5640831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612273abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612273aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612273908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056122703fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056122703fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5640832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56408330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56408330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056122703fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (1464 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf4_f16(<vscale x 1 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf2_f16(<vscale x 2 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m1_f16(<vscale x 4 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m2_f16(<vscale x 8 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m4_f16(<vscale x 16 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m8_f16(<vscale x 32 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32mf2_f32(<vscale x 1 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m1_f32(<vscale x 2 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m2_f32(<vscale x 4 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m4_f32(<vscale x 8 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m8_f32(<vscale x 16 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m1_f64(<vscale x 1 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m2_f64(<vscale x 2 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m4_f64(<vscale x 4 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m8_f64(<vscale x 8 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6974d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6974d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6974d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0499049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04990a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0499049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0499031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d69746abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d69746aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d69744f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6970fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6970feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0499032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04990330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04990330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6970fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (1465 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 4 x 
# | ...
# `---data was truncated (10240/142016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557377dbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557377dbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557377dbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69e3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69e3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69e3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69e3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557377d54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557377d54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557377d398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573779e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573779e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69e3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69e3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69e3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573779e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (1466 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <
# | ...
# `---data was truncated (10240/14421) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556aa47beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556aa47bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556aa47bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff41e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff41e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff41e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff41e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556aa4754bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556aa4754a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556aa47398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556aa43e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556aa43e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff41e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff41e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff41e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556aa43e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (1467 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9f2814eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9f2811e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9f281562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0604d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0604d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0604d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0604d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9f27aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9f27aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9f278f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9f243ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9f243eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0604d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0604d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0604d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9f243ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (1468 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %bas
# | ...
# `---data was truncated (10240/60209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b5a05ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b5a059e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b5a05d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdff9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdff9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdff9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdff9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b59ff2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b59ff2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b59fd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b59c86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b59c86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdff9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdff9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdff9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b59c86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (1469 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/10610) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561dfa071eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561dfa06ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561dfa07262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8956c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8956ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8956c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8956c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dfa007bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561dfa007a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561df9fec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561df9c9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561df9c9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8956c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8956c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8956c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561df9c9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (1470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.a
# | ...
# `---data was truncated (10240/33190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ea805deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ea805ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ea805e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89b921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89b92725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89b921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89b9203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea7ff3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ea7ff3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ea7fd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ea7c87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ea7c87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89b9204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89b92050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89b92050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea7c87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (1471 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f110ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f110cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f110cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcc1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcc115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcc1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcc10ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f11064bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f11064a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f110498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f10cf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f10cf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcc10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcc10ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcc10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f10cf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (1472 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vundefined_f16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vundefined_f16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vundefined_f16m1() #0 {
# | entry:
# |   ret <vscale x 4 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vundefined_f16m2() #0 {
# | entry:
# |   ret <vscale x 8 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vundefined_f16m4() #0 {
# | entry:
# |   ret <vscale x 16 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vundefined_f16m8() #0 {
# | entry:
# |   ret <vscale x 32 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vundefined_f32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vundefined_f32m1() #0 {
# | entry:
# |   ret <vscale x 2 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vundefined_f32m2() #0 {
# | entry:
# |   ret <vscale x 4 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vundefined_f32m4() #0 {
# | entry:
# |   ret <vscale x 8 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vundefined_f32m8() #0 {
# | entry:
# |   ret <vscale x 16 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vundefined_f64m1() #0 {
# | entry:
# |   ret <vscale x 1 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vundefined_f64m2() #0 {
# | entry:
# |   ret <vscale x 2 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vundefined_f64m4() #0 {
# | entry:
# |   ret <vscale x 4 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vundefined_f64m8() #0 {
# | entry:
# |   ret <vscale x 8 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_i8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_i8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_i8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_i8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_i8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_i8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_i8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_i16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_i16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_i16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_i16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_i16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_i16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_i32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_i32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_i32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_i32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_i32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_i64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_i64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_i64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_i64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_u8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_u8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_u8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_u8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_u8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_u8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_u8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_u16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_u16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_u16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_u16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_u16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_u16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_u32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_u32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_u32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_u32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_u32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_u64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_u64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_u64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_u64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/63140) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d496794eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d496791e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d49679562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5b1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5b158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5b1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5b151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d49672abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d49672aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d49670f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4963bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4963beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5b151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5b151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5b151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4963bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (1473 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c92eb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c92eb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c92eb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8aeb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8aeb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8aeb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8aeb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c92e4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c92e4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c92e318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c92ae0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c92ae0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8aeb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8aeb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8aeb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c92ae0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (1474 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055919c6d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055919c6cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055919c6d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91aaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91aaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91aaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91aaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055919c666bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055919c666a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055919c64b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055919c2fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055919c2fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91aaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91aaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91aaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055919c2faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (1475 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e6fe84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e6fe81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e6fe8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98fca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98fcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98fca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98fca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e6fe1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e6fe1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e6fdff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e6faaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e6faaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98fca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98fca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98fca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e6faaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (1476 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32
# | ...
# `---data was truncated (10240/75405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590d61d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590d61d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590d61d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8eca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8eca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8eca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8eca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590d616cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590d616ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590d61518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590d5e00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590d5e00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8eca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8eca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8eca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590d5e00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (1477 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645f7eb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645f7eb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645f7eb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbd0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbd038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbd0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbd031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645f7e4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645f7e4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645f7e338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645f7ae2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645f7ae2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbd031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbd031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbd031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645f7ae2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (1478 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b122907eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b122904e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b12290862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd85c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd85c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd85c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd85c803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b12289dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b12289da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1228828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b122531e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b122531b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd85c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd85c8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd85c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b122531a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (1479 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b689a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b6899ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b689a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd9c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd9c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd9c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd9c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b68937bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b68937a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b6891c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b685cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b685cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd9c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd9c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd9c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b685cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (1480 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee8160deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee8160ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee8160e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22a9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22a92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22a9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22a9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee815a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee815a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee815888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee81237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee81237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22a9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22a92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22a92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee81237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (1481 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone   -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %add.i = fadd <4 x float> %2, %3
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %sub.i = fsub <2 x float> %2, %3
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <4 x float> %2, %3
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <2 x double> %2, %3
# |   store <2 x double> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <4 x float> %2, %3
# |   store <4 x float> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <2 x double> %2, %3
# |   store <2 x double> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   %v3.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   store <2 x float> %v3, ptr %v3.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   %2 = load <2 x float>, ptr %v3.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x float>, ptr %__p2.addr.i, align 8
# |   %mul.i = fmul <2 x float> %4, %5
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %6 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   %v3.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   store <4 x float> %v3, ptr %v3.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   %2 = load <4 x float>, ptr %v3.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load <4 x float>, ptr %__p2.addr.i, align 16
# |   %mul.i = fmul <4 x float> %4, %5
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/91378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b429a8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b429a8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b429a8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c1c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c1c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c1c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c1c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b429a24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b429a24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b429a098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4296b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4296b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c1c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c1c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c1c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4296b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (1482 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e6d0c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e6d0c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e6d0ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90beb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90beb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90beb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90beb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e6d05fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e6d05fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e6d0448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e6ccf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e6ccf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90beb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90beb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90beb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e6ccf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (1483 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d3e209eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d3e206e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d3e20a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d72705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d7275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d72705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d726ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d3e19fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d3e19fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d3e1848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d3de33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d3de33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d726eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d726ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d726ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d3de33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (1484 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaf7b73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaf7b70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaf7b7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe62ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe62eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe62ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe62ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaf7b09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaf7b09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaf7aee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaf779de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaf779db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe62ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe62ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe62ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaf779da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (1485 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f2afc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f2afc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f2afc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9a1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9a1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9a1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9a1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f2af5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f2af5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f2af418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f2abf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f2abf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9a1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9a1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9a1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f2abf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (1486 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec3d483eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec3d480e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec3d48462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aa3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aa3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aa3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aa3e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec3d419bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec3d419a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec3d3fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec3d0ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec3d0adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4aa3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aa3e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aa3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec3d0ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (1487 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d70723eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d70720e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d7072462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91ffd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91ffd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91ffd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91ffd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d706b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d706b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d7069e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d7034de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d7034db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91ffd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91ffd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91ffd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d7034da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (1488 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564aea614eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564aea611e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564aea61562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facfd21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facfd2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facfd21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facfd203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aea5aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aea5aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aea58f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aea23ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aea23eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facfd204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facfd2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facfd2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aea23ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (1489 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055caa0e5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055caa0e5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055caa0e5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8aa2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8aa2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8aa2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8aa2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caa0df3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055caa0df3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055caa0dd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055caa0a87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055caa0a87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8aa2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8aa2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8aa2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055caa0a87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (1490 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<vscale x
# | ...
# `---data was truncated (10240/11396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0c04e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0c04e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0c04e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6a601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6a60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6a601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6a6003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0c0479bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0c0479a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0c045e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0c010de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0c010db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6a6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6a60050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6a60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0c010da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (1491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603b9afeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603b9afbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603b9aff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84c2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84c2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84c2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84c2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603b9a94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603b9a94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603b9a798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603b9728e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603b9728b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84c2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84c2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84c2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603b9728a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (1492 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ce5105eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ce5102e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ce510662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3fdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3fdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3fdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3fdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ce509bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ce509ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ce50808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ce4d2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ce4d2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3fdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3fdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3fdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ce4d2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-cde-vec.c (1493 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 {
# | entry:
# |   %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111)
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %acc, ptr %acc.addr, align 8
# |   %0 = load <4 x i32>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113)
# |   %3 = bitcast <16 x i8> %2 to <4 x i32>
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <8 x half>, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   %0 = load <8 x half>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <4 x float>, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %n.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112)
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <2 x i64>, align 8
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = load <2 x i64>, ptr %n.addr, align 8
# |   %3 = bitcast <2 x i64> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113)
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x i32> %m, ptr %m.addr, align 8
# |   %0 = load <8 x i16>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <16 x i8>
# |   %2 = load <4 x i32>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x i32> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <2 x i64>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <2 x i64>, ptr %n.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %2 = load <4 x float>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12)
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load <8 x i16>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x i16> %1 to <16 x i8>
# |   %3 = load <4 x float>, ptr %m.addr, align 8
# |   %4 = bitcast <4 x float> %3 to <16 x i8>
# |   %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %n.addr, align 8
# |   %2 = bitcast <4 x float> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = load <8 x half>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x half> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %m.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# | ...
# `---data was truncated (10240/13030) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056391184aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563911847e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056391184b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efff5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efff5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efff5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efff5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639117e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639117e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639117c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563911474e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563911474b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efff5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efff5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efff5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563911474a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (1494 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f7bbceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f7bbcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f7bbcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33e3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33e3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33e3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33e3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f7bb64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f7bb64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f7bb498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f7b7f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f7b7f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33e3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33e3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33e3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f7b7f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (1495 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef328b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef328b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef328b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1df933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1df98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1df933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1df91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef32849bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef32849a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef3282e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef324dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef324ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1df91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1df91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1df91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef324dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (1496 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4d34f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4d34f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4d34f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc51905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc5195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc51905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc518ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4d348dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4d348da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4d34728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4d3121e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4d3121b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc518eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc518ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc518ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4d3121a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (1497 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe08b54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe08b51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe08b5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f535b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f535b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f535b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f535b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe08aeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe08aeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe08acf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe0877ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe0877eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f535b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f535b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f535b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe0877ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (1498 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558372842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055837283fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055837284362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b22b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b22b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b22b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b22aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583727d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583727d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583727bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055837246ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055837246cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b22aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b22aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b22aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055837246ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (1499 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6c2668eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6c2665e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6c266962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e3d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e3d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e3d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e3d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6c25febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6c25fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6c25e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6c2292e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6c2292b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e3d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e3d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e3d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6c2292a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (1500 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac24306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac24303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac2430762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d0921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d092725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d0921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d09203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac2429cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac2429ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac242818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac23f30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac23f30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d09204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d092050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d092050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac23f30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (1501 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/68073) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e07f6c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e07f6bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e07f6c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd21f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd21f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd21f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd21eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e07f656bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e07f656a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e07f63b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e07f2eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e07f2eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd21eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd21eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd21eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e07f2eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (1502 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a33ca85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a33ca82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a33ca8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa122a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa122aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa122a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa122a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a33ca1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a33ca1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a33ca008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a33c6afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a33c6afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa122a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa122a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa122a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a33c6afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (1503 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/88444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e38a75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e38a72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e38a7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb792b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb792b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb792b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb792b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e38a0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e38a0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e389f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e3869fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e3869fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb792b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb792b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb792b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e3869fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (1504 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c6628eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c6628be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c6628f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76bb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76bb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76bb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76bb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c66224bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c66224a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c662098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c65eb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c65eb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76bb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76bb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76bb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c65eb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (1505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/33764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562085aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562085aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562085af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c53d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c53d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c53d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c53ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562085a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562085a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562085a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562085719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562085719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c53ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c53cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c53cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562085719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (1506 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056129fb5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056129fb57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056129fb5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6d9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6d998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6d9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6d991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056129faf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056129faf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056129fad58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056129f784e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056129f784b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6d991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6d991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6d991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056129f784a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (1507 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/32709) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f38311beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f383118e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f38311c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96fde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96fdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96fde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96fde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3830b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3830b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3830968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f382d45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f382d45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96fde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96fde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96fde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f382d45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (1508 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c91bd5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c91bd59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c91bd5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0620133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f062018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0620133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f062011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c91bcf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c91bcf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c91bcd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c91b986e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c91b986b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f062011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f062011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f062011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c91b986a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (1509 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563188503eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563188500e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056318850462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e71d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e71d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e71d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e71d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563188499bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563188499a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056318847e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056318812de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056318812db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e71d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e71d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e71d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056318812da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (1510 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcad68beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcad688e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcad68c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facf5a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facf5a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facf5a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facf5a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcad621bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcad621a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcad6068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcad2b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcad2b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facf5a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facf5a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facf5a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcad2b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (1511 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056369fd27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056369fd24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056369fd2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc025a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc025aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc025a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc025a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056369fcbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056369fcbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056369fca28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056369f951e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056369f951b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc025a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc025a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc025a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056369f951a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (1512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564aff687eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564aff684e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564aff68862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8abd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8abd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8abd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8abd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aff61dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aff61da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aff6028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aff2b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aff2b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8abd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8abd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8abd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aff2b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (1513 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b5c492eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b5c48fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b5c49362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8689b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8689b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8689b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8689b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b5c428bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b5c428a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b5c40d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b5c0bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b5c0bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8689b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8689b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8689b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b5c0bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (1514 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd83c81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd83c7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd83c8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16cd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16cd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16cd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16cd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd83c17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd83c17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd83bfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd838abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd838abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16cd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16cd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16cd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd838aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (1515 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056192f7d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056192f7d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056192f7da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b39d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b39d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b39d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b39d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056192f76fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056192f76fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056192f7548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056192f403e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056192f403b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b39d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b39d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b39d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056192f403a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (1516 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631e8501eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631e84fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631e850262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b6f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b6f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b6f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b6f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631e8497bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631e8497a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631e847c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631e812be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631e812bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b6f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b6f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b6f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631e812ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (1517 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4bdb19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4bdb16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4bdb1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4b8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4b878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4b8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4b871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4bdaafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4bdaafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4bda948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4bd743e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4bd743b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4b871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4b871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4b871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4bd743a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (1518 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602276c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602276bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602276c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa219f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa219f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa219f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa219f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560227657bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560227657a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056022763c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602272ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602272ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa219f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa219f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa219f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602272eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (1519 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b66851aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b668517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b66851b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01dce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01dcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01dce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01dce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6684b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6684b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6684958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b668144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b668144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01dce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01dce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01dce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b668144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (1520 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractva
# | ...
# `---data was truncated (10240/22708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d62b74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d62b71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d62b7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30ff333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30ff38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30ff333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30ff31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d62b0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d62b0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d62aef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d6279ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d6279eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30ff31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30ff31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30ff31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d6279ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (1521 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d43e75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d43e72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d43e7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc406c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc406ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc406c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc406c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d43e0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d43e0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d43df08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d43a9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d43a9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc406c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc406c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc406c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d43a9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (1522 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b99ea0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b99e9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b99ea162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff07e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff07e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff07e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff07e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b99e36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b99e36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b99e1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b99acae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b99acab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff07e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff07e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff07e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b99acaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (1523 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617a3adceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617a3ad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617a3add62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f966b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f966b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f966b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f966b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617a3a72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617a3a72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617a3a578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617a3706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617a3706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f966b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f966b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f966b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617a3706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (1524 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d22bdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d22bd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d22bdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78cc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78cc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78cc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78cc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d22b71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d22b71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d22b568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d22805e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d22805b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78cc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78cc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78cc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d22805a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (1525 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572c1c41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572c1c3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572c1c4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4209649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42096a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4209649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4209631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572c1bd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572c1bd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572c1bbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572c186be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572c186bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4209632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42096330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42096330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572c186ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (1526 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c860505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c860502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c86050662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f705741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70574725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f705741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7057403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c86049bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c86049ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8604808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c86012fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c86012fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7057404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70574050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70574050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c86012fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (1527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558f2d4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558f2d48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558f2d4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc67ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc67ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc67ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc67aced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558f2ce1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558f2ce1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558f2cc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558f2975e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558f2975b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc67aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc67acef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc67acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558f2975a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (1528 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 
# | ...
# `---data was truncated (10240/69943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056351234deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056351234ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056351234e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc573249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc573249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc573231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635122e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635122e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635122c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563511f77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563511f77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc573232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563511f77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (1529 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0d3a1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0d3a1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0d3a1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f516dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f516dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f516dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f516dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0d39b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0d39b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0d39988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0d3647e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0d3647b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f516dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f516dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f516dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0d3647a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (1530 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566022a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055660229de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566022a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc29c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc29c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc29c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc29c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556602236bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556602236a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055660221b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556601ecae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556601ecab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc29c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc29c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc29c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556601ecaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (1531 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.a
# | ...
# `---data was truncated (10240/28771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557b8a97eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b8a97be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b8a97f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1265d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1265d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1265d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1265d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b8a914bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b8a914a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b8a8f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b8a5a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b8a5a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1265d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1265d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1265d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b8a5a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (1532 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b30ed12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b30ed0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b30ed1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f772cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f772cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f772cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f772cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b30eca8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b30eca8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b30ec8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b30e93ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b30e93cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f772cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f772cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f772cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b30e93ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (1533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da30331eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da3032ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da3033262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89ad933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89ad98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89ad933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89ad91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da302c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da302c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da302ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da2ff5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da2ff5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89ad91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89ad91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89ad91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da2ff5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (1534 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6f68ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6f68dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6f68de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9db1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9db16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9db1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9db1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6f6873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6f6873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6f68588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6f6507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6f6507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9db1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9db16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9db16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6f6507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (1535 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# | 
# | ...
# `---data was truncated (10240/23255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638d6f90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638d6f8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638d6f9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04c9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04c94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04c9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04c9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638d6f26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638d6f26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638d6f0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638d6bbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638d6bbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04c9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04c94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04c94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638d6bbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (1536 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056280be77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056280be74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056280be7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f036d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f036d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f036d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f036d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056280be0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056280be0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056280bdf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056280baa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056280baa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f036d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f036d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f036d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056280baa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (1537 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555926977eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555926974e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055592697862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba6d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba6d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba6d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba6d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055592690dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055592690da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559268f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559265a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559265a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba6d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba6d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba6d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559265a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (1538 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb55236eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb55233e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb5523762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c56049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c560a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c56049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c56031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb551ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb551cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb551b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb54e60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb54e60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c56032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c560330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c560330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb54e60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (1539 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3c030feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3c030ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3c031062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f626c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f626c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f626c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f626c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3c02a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3c02a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3c028a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3bff39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3bff39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f626c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f626c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f626c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3bff39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (1540 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056521aba5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056521aba2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056521aba662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd02ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd02ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd02ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd02ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056521ab3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056521ab3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056521ab208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056521a7cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056521a7cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd02ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd02ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd02ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056521a7cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (1541 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/66322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597ded49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597ded46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597ded4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f007c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f007c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f007c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f007c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597decdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597decdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597decc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597de973e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597de973b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f007c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f007c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f007c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597de973a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (1542 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055723c8d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055723c8cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055723c8d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1beea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1beeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1beea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1beea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055723c866bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055723c866a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055723c84b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055723c4fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055723c4fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1beea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1beea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1beea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055723c4faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (1543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d99ebc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d99ebc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d99ebc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f554c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f554c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f554c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f554c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d99eb59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d99eb59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d99eb3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d99e7ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d99e7edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f554c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f554c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f554c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d99e7eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (1544 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055589f81beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055589f818e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055589f81c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd54fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd54fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd54fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd54faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055589f7b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055589f7b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055589f7968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055589f445e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055589f445b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd54faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd54faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd54faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055589f445a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (1545 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055582236beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555822368e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055582236c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21e2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21e298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21e2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21e291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555822301bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555822301a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558222e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555821f95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555821f95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21e291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21e291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21e291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555821f95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (1546 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575d2f2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575d2f29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575d2f2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575d2ec2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575d2ec2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575d2ea78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575d2b56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575d2b56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbeb8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575d2b56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (1547 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %
# | ...
# `---data was truncated (10240/201226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056268e3b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056268e3ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056268e3b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40e7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40e7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40e7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40e7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056268e346bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056268e346a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056268e32b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056268dfdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056268dfdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40e7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40e7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40e7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056268dfdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (1548 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f322441eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f32243ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f32244262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a82333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a8238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a82333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a8231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3223d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3223d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3223bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f32206be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f32206bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a8231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a8231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a8231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f32206ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (1549 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558685fb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558685fade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558685fb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6843849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68438a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6843849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6843831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558685f46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558685f46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558685f2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558685bdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558685bdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6843832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68438330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68438330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558685bdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (1550 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/223809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c33648eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c33645e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c3364962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07f9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07f9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07f9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07f9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c335debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c335dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c335c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c33272e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c33272b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07f9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07f9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07f9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c33272a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (1551 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca targe
# | ...
# `---data was truncated (10240/53556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587cbc1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587cbc17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587cbc1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde26449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde26449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde26431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587cbbb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587cbbb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587cbb958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587cb844e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587cb844b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde26432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde264330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587cb844a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (1552 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/51193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e15902eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e158ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e1590362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5597333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f559738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5597333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f559731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e15898bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e15898a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e1587d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e1552ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e1552cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f559731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f559731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f559731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e1552ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (1553 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614f722deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614f722ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614f722e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc82c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc82c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc82c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc82c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614f71c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614f71c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614f71a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614f6e57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614f6e57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc82c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc82c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc82c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614f6e57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (1554 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4414e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4414e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4414e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f428b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f428b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f428b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f428b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f44147dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f44147da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4414628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f441111e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f441111b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f428b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f428b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f428b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f441111a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (1555 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055581a29feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055581a29ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055581a2a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd49341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4934725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd49341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd493403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055581a235bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055581a235a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055581a21a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555819ec9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555819ec9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd493404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4934050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4934050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555819ec9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (1556 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f75b63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f75b60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f75b6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31f7b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31f7b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31f7b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31f7aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f75af9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f75af9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f75ade8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f7578de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f7578db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31f7aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31f7aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31f7aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f7578da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (1557 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580036bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580036b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580036bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6779933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f677998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6779933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f677991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558003651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558003651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580036368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580032e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580032e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f677991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f677991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f677991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580032e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (1558 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558785454eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558785451e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055878545562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa22fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa22fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa22fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa22fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587853eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587853eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587853cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055878507ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055878507eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa22fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa22fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa22fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055878507ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (1559 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639114b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639114b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639114b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f918921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91892725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f918921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9189203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056391144cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056391144ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639114318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639110e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639110e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9189204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91892050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91892050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639110e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (1560 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598492faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598492f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598492fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38f8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38f838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38f8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38f831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559849290bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559849290a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598492758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559848f24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559848f24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38f831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38f831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38f831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559848f24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (1561 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563528dd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563528dcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563528dd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1253249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12532a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1253249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1253231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563528d68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563528d68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563528d4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635289fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635289fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1253232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12532330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12532330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635289fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (1562 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a2aa0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a2aa0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a2aa0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab10449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab104a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab10449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab10431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a2a9a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a2a9a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a2a9888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a2a637e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a2a637b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab10432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab104330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab104330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a2a637a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (1563 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563634479eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563634476e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056363447a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d4f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d4f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d4f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d4f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056363440fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056363440fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636343f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636340a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636340a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d4f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d4f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d4f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636340a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (1564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2571d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2571d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2571da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fead0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fead0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fead0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fead0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d25716fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d25716fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2571548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d256e03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d256e03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fead0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fead0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fead0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d256e03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (1565 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd4fbc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd4fbc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd4fbc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f223a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f223a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f223a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f223a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd4fb5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd4fb5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd4fb438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd4f7f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd4f7f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f223a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f223a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f223a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd4f7f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (1566 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a2898f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2898eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2898f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadef31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a289887bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a289887a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a28986c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a28951be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a28951bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadef31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a28951ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (1567 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591e85b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591e85b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591e85b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f414e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f414e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f414e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f414e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591e8549bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591e8549a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591e852e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591e81dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591e81ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f414e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f414e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f414e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591e81dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (1568 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e38cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e38ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e38cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ec7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ec718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ec7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ec711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e38c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e38c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e38c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e388fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e388fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ec711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ec711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ec711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e388faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (1569 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcd9657eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fcd9654e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fcd965862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd53e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd53e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd53e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd53e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcd95edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fcd95eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fcd95d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fcd9281e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fcd9281b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd53e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd53e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd53e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcd9281a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (1570 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> p
# | ...
# `---data was truncated (10240/24606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adc58e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055adc58e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055adc58ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa229249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2292a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa229249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa229231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adc587fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055adc587fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055adc58648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055adc5513e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055adc5513b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa229232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2292330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2292330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adc5513a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (1571 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556811765eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556811762e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055681176662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59baa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59baaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59baa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59baa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568116fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568116fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568116e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055681138fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055681138fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59baa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59baa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59baa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055681138fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (1572 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb77a5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb77a5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb77a5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6c2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6c2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6c2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6c2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb779f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb779f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb779d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb77687e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb77687b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6c2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6c2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6c2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb77687a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (1573 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store targ
# | ...
# `---data was truncated (10240/14667) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560584bf5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560584bf2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560584bf662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b17105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b1715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b17105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b170ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560584b8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560584b8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560584b708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056058481fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056058481fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b170eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b170ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b170ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056058481fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (1574 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/153905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056199b103eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056199b100e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056199b10462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f792dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f792dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f792dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f792dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056199b099bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056199b099a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056199b07e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056199ad2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056199ad2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f792dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f792dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f792dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056199ad2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (1575 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055910631aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559106317e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055910631b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc247649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2476a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc247649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc247631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591062b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591062b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591062958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559105f44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559105f44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc247632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2476330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2476330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559105f44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (1576 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vsc
# | ...
# `---data was truncated (10240/69951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffc3914eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffc3911e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffc391562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe933133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe93318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe933133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe93311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffc38aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffc38aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffc388f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffc353ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffc353eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe93311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe93311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe93311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffc353ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (1577 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638a5a92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638a5a8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638a5a9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f423b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f423b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f423b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f423b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638a5a28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638a5a28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638a5a0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638a56bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638a56bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f423b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f423b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f423b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638a56bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (1578 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574417b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574417b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574417ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f777d905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f777d95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f777d905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f777d8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055744174fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055744174fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574417348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574413e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574413e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f777d8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f777d8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f777d8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574413e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (1579 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, a
# | ...
# `---data was truncated (10240/28358) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c06d8b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c06d8ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c06d8b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f229cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f229cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f229cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f229cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c06d846bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c06d846a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c06d82b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c06d4dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c06d4dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f229cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f229cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f229cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c06d4daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (1580 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a50ebc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a50ebc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a50ebc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b05e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b05ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b05e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b05e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a50eb5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a50eb5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a50eb418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a50e7f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a50e7f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b05e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b05e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b05e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a50e7f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (1581 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/136489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f304b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f304b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f304b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e9af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f3044cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f3044ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f304318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f300e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f300e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f300e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (1582 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ae4e87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ae4e84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ae4e8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92abf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92abf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92abf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92abf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ae4e1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ae4e1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ae4e028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ae4ab1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ae4ab1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92abf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92abf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92abf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ae4ab1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (1583 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c158b21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c158b1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c158b2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fc321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fc32725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fc321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fc3203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c158ab7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c158ab7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c158a9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c15874be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c15874bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fc3204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fc32050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fc32050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c15874ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (1584 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a76bc8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a76bc8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a76bc9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6b9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6b938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6b9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6b931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a76bc25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a76bc25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a76bc0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a76b8b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a76b8b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6b931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6b931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6b931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a76b8b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (1585 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ccd31deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ccd31ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ccd31e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82e1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82e1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82e1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82e1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ccd2b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ccd2b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ccd2988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cccf47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cccf47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82e1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82e1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82e1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cccf47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (1586 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056030baaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056030baa9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056030baad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28c7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28c7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28c7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28c7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056030ba42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056030ba42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056030ba278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056030b6d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056030b6d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28c7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28c7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28c7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056030b6d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (1587 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a2769eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a2769be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a2769f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f330d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f330d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f330d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f330d403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a27634bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a27634a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a276198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a272c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a272c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f330d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f330d4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f330d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a272c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (1588 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598ce2a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598ce29fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598ce2a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e27249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e272a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e27249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e27231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598ce238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598ce238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598ce21d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598cdecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598cdeccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e27232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e272330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e272330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598cdecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (1589 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c26b273eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c26b270e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c26b27462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb90d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb90d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb90d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb90d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c26b209bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c26b209a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c26b1ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c26ae9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c26ae9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb90d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb90d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb90d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c26ae9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (1590 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6a924aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6a9247e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6a924b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf87049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf870a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf87049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf87031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6a91e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6a91e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6a91c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6a8e74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6a8e74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf87032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf870330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf870330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6a8e74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (1591 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/81756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e22aaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e22aabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e22aaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38a2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38a258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38a2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38a251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e22a44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e22a44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e22a298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e226d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e226d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38a251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38a251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38a251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e226d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (1592 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba30f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fba30f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fba30f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43a4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43a42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43a4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43a4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba3089bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fba3089a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fba306e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fba2d1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fba2d1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43a4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43a42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43a42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba2d1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (1593 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac7cebdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac7cebae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac7cebe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48ec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48ec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48ec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48ec91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac7ce53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac7ce53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac7ce388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac7cae7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac7cae7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48ec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48ec91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48ec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac7cae7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (1594 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.
# | ...
# `---data was truncated (10240/28162) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6f73c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6f73bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6f73c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa68305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa6835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa68305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa682ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6f7358bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6f7358a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6f733d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6f6fece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6f6fecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa682eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa682ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa682ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6f6feca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (1595 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559241000eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559240ffde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055924100162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f38049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f380a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f38049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f38031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559240f96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559240f96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559240f7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559240c2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559240c2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f38032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f380330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f380330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559240c2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (1596 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5a2f28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5a2f25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5a2f2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa951649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9516a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa951649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa951631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5a2ebebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5a2ebea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5a2ea38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5a2b52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5a2b52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa951632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9516330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9516330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5a2b52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (1597 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a85a6caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a85a6c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a85a6cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b41b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b41b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b41b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b41b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a85a660bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a85a660a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a85a6458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a85a2f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a85a2f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b41b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b41b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b41b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a85a2f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (1598 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634e1ac4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634e1ac1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634e1ac562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a40c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a40ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a40c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a40c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634e1a5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634e1a5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634e1a3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634e16eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634e16eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a40c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a40c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a40c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634e16eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (1599 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s0, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 
# | ...
# `---data was truncated (10240/18482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055630dd6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055630dd68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055630dd6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f197ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f197eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f197ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f197ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055630dd01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055630dd01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055630dce68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055630d995e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055630d995b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f197ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f197ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f197ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055630d995a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (1600 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue
# | ...
# `---data was truncated (10240/81764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055824057aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558240577e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055824057b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9343649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93436a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9343649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9343631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558240510bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558240510a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582404f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582401a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582401a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9343632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93436330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93436330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582401a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (1601 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563074956eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563074953e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056307495762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4755049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47550a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4755049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4755031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630748ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630748eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630748d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563074580e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563074580b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4755032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47550330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47550330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563074580a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (1602 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632bd799eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632bd796e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632bd79a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f085b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f085b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f085b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f085b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632bd72fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632bd72fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632bd7148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632bd3c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632bd3c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f085b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f085b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f085b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632bd3c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (1603 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.ad
# | ...
# `---data was truncated (10240/26762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3970b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3970b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3970b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4eb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4eb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4eb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4eb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a39704dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a39704da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3970328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a396ce1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a396ce1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4eb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4eb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4eb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a396ce1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (1604 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0
# | ...
# `---data was truncated (10240/29136) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559913e80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559913e7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559913e8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63cc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63cc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63cc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63cc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559913e16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559913e16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559913dfb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559913aaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559913aaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63cc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63cc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63cc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559913aaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (1605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2b3864eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2b3861e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2b386562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1704b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1704b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1704b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1704aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2b37fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2b37faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2b37df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2b348ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2b348eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1704aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1704aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1704aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2b348ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (1606 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056155b66deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056155b66ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056155b66e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7e3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7e3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7e3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7e3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056155b603bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056155b603a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056155b5e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056155b297e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056155b297b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7e3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7e3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7e3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056155b297a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (1607 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8f8c18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8f8c15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8f8c1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4828849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48288a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4828849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4828831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f8baebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8f8baea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8f8b938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8f8842e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8f8842b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4828832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48288330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48288330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f8842a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (1608 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b78e1b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b78e1ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b78e1b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f861dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f861dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f861dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f861dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b78e146bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b78e146a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b78e12b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b78dddae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b78dddab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f861dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f861dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f861dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b78dddaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (1609 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe13c79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe13c76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe13c7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ba6f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ba6f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ba6f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ba6eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe13c0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe13c0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe13bf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe138a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe138a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ba6eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ba6eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ba6eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe138a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (1610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e012d2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e012d2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e012d2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d4e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d4e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d4e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d4e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e012cc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e012cc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e012ca98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e012958e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e012958b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d4e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d4e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d4e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e012958a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-3v.c (1611 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %and.i = and <8 x i16> %2, %3
# |   store <8 x i16> %and.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %and.i = and <2 x i32> %2, %3
# |   store <2 x i32> %and.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %and.i = and <4 x i32> %2, %3
# |   store <4 x i32> %and.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %and.i = and <1 x i64> %2, %3
# |   store <1 x i64> %and.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %and.i = and <2 x i64> %2, %3
# |   store <2 x i64> %and.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, al
# | ...
# `---data was truncated (10240/70553) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556041dcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556041dc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556041dcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0e9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0e998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0e9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0e991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556041d60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556041d60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556041d458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560419f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560419f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0e991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0e991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0e991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560419f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (1612 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c4bcc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c4bcc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c4bcc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb311d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb311d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb311d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb311d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c4bc5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c4bc5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c4bc3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c4b8eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c4b8eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb311d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb311d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb311d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c4b8eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (1613 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm
# | ...
# `---data was truncated (10240/53200) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618a3500eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618a34fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618a350162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c0e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c0e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c0e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c0e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618a3496bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618a3496a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618a347b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618a312ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618a312ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c0e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c0e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c0e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618a312aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (1614 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dc2bb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dc2bb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dc2bb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd89d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd89d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd89d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd89d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dc2b49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dc2b49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dc2b2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dc27dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dc27ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd89d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd89d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd89d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dc27dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (1615 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> poison, i64 %0)
# |   ret <vscale x 1 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> poison, i64 %0)
# |   ret <vscale x 2 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> poison, i64 %0)
# |   ret <vscale x 4 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> poison, i64 %0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> poison, i64 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> poison, i64 %0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> poison, i64 %0)
# |   ret <vscale x 64 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> poison, i64 %0)
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> poison, i64 %0)
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> poison, i64 %0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> poison, i64 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> poison, i64 %0)
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> poison, i64 %0)
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32> poison, i64 %0)
# |   ret <vscale x 1 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vid_v_u32m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32> poison, i64 %0)
# |   ret <vscale x 2 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vid_v_u32m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32> poison, i64 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vid_v_u32m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32> poison, i64 %0)
# |   ret <vscale x 8 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vid_v_u32m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32> poison, i64 %0)
# |   ret <vscale x 16 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vid_v_u64m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/30303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d14073eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d14070e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d1407462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff45d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff45d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff45d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff45d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d14009bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d14009a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d13fee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d13c9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d13c9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff45d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff45d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff45d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d13c9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (1616 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f750478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f750475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f75047962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d43133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d4318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d43133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d4311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f75040ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f75040ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7503f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7500a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7500a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d4311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d4311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d4311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7500a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (1617 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa7e07ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa7e079e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa7e07d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe972733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe97278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe972733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe97271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa7e012bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa7e012a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa7dff78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa7dca6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa7dca6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe97271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe97271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe97271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa7dca6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (1618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b942b34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b942b31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b942b3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee00a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee00aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee00a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee00a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b942acabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b942acaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b942aaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b94275ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b94275eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee00a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee00a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee00a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b94275ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (1619 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a953009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a953006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a95300a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd775505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd77555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd775505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7754ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a952f9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a952f9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a952f848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a952c33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a952c33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7754eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7754ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7754ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a952c33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (1620 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb2803beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb28038e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb2803c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1e4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1e478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1e4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1e471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb27fd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb27fd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb27fb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb27c65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb27c65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1e471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1e471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1e471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb27c65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (1621 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1)
# |   ret float %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1)
# |   ret double %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1)
# |   ret float %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1)
# |   ret double %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1)
# |   ret float %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1)
# |   ret double %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1)
# |   ret float %frint64x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1)
# |   ret double %frint64x.i
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32x.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64x.f64(double) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611020b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611020b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611020b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03a4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03a478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03a4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03a471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056110204bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056110204ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611020308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561101cdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561101cdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03a471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03a471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03a471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561101cdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (1622 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be21566eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be21563e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be2156762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb17e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb17e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb17e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb17e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be214fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be214fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be214e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be21190e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be21190b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb17e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb17e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb17e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be21190a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (1623 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632b2407eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632b2404e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632b240862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3810a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3810a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3810a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3810a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632b239dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632b239da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632b23828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632b2031e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632b2031b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3810a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3810a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3810a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632b2031a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (1624 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056316251feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056316251ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056316252062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd10061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1006725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd10061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd100603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631624b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631624b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056316249a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563162149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563162149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd100604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1006050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1006050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563162149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (1625 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a27717eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a27714e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a2771862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cef505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cef55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cef505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cef4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a276adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a276ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a276928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a27341e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a27341b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cef4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cef4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cef4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a27341a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (1626 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a94075eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a94072e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a9407662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc4e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc4e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc4e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc4e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a9400bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a9400ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a93ff08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a93c9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a93c9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc4e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc4e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc4e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a93c9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (1627 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a31e658eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a31e655e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a31e65962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe500705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe50075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe500705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5006ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a31e5eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a31e5eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a31e5d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a31e282e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a31e282b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5006eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5006ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5006ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a31e282a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (1628 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f725598eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f725595e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f72559962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff622849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6228a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff622849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff622831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f72552ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f72552ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7255138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7251c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7251c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff622832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6228330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6228330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7251c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (1629 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e9f749eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e9f746e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e9f74a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7609333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f760938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7609333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f760931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e9f6dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e9f6dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e9f6c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e9f373e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e9f373b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f760931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f760931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f760931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e9f373a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (1630 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 
# | ...
# `---data was truncated (10240/22890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df9d9f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df9d9ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df9d9f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ae3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ae375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ae3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ae36ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df9d986bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df9d986a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df9d96b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df9d61ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df9d61ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ae36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ae36ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ae36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df9d61aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (1631 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d68c17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d68c14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d68c1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febf561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febf56725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febf561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febf5603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d68badbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d68bada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d68b928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d68841e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d68841b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febf5604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febf56050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febf56050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d68841a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (1632 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/62964) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b770874eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b770871e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b77087562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7c461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7c46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7c461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7c4603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b77080abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b77080aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7707ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b77049ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b77049eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7c4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7c46050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7c46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b77049ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (1633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648365e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648365dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648365e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f00c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f00ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f00c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f00c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564836578bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564836578a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056483655d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056483620ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056483620cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f00c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f00c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f00c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056483620ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (1634 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/12177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfd414deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfd414ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfd414e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5659733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f565978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5659733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f565971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfd40e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfd40e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfd40c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfd3d77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfd3d77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f565971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f565971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f565971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfd3d77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (1635 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630df218eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630df215e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630df21962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1be5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1be5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1be5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1be5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630df1aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630df1aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630df1938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630dee42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630dee42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1be5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1be5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1be5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630dee42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (1636 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f14319beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f143198e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f14319c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1543e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1543ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1543e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1543e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f143131bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f143131a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1431168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f142dc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f142dc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1543e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1543e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1543e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f142dc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (1637 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d60f539eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d60f536e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d60f53a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2067d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2067d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2067d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2067d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d60f4cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d60f4cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d60f4b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d60f163e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d60f163b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2067d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2067d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2067d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d60f163a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (1638 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_l
# | ...
# `---data was truncated (10240/13585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618b2f0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618b2f07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618b2f0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62eb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62eb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62eb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62eb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618b2ea0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618b2ea0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618b2e858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618b2b34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618b2b34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62eb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62eb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62eb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618b2b34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (1639 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea0a65deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea0a65ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea0a65e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c57a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c57a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c57a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c57a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea0a5f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea0a5f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea0a5d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea0a287e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea0a287b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c57a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c57a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c57a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea0a287a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (1640 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8475a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c84759de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8475a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff044905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff04495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff044905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0448ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c847536bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c847536a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c84751b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8471cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8471cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0448eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0448ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0448ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8471caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (1641 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599d4ca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599d4ca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599d4ca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7478d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7478d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7478d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7478d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599d4c3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599d4c3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599d4c208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599d48cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599d48cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7478d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7478d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7478d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599d48cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (1642 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align 8
# |   sto
# | ...
# `---data was truncated (10240/102864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b6b973eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b6b970e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b6b97462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f24733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f2478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f24733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f2471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b6b909bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b6b909a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b6b8ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b6b59de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b6b59db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f2471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f2471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f2471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b6b59da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (1643 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639b1a9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639b1a98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639b1a9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f594f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f594f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f594f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f594f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639b1a31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639b1a31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639b1a168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639b16c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639b16c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f594f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f594f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f594f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639b16c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (1644 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557c3d69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557c3d66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557c3d6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20e9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20e935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20e9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20e92ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557c3cffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557c3cffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557c3ce48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557c3993e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557c3993b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20e92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20e92ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20e92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557c3993a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (1645 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>
# | ...
# `---data was truncated (10240/76635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1a0181eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1a017ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1a018262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f733fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f733fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f733fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f733fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1a0117bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1a0117a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1a00fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a19fdabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a19fdabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f733fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f733fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f733fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a19fdaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (1646 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f5d622eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f5d61fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f5d62362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6711705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f671175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6711705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67116ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f5d5b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f5d5b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f5d59d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f5d24ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f5d24cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67116eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67116ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67116ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f5d24ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (1647 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6461cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6461c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6461cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67f8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67f8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67f8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67f8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c646162bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c646162a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6461478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c645df6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c645df6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67f8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67f8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67f8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c645df6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (1648 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b2d62beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b2d628e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b2d62c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee78849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee78849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee78831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b2d5c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b2d5c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b2d5a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b2d255e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b2d255b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee78832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee788330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b2d255a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (1649 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af3f412eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af3f40fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af3f41362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cb2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cb2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cb2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cb2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af3f3a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af3f3a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af3f38d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af3f03ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af3f03cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cb2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cb2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cb2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af3f03ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (1650 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4bf800eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4bf7fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4bf80162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faacdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faacdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faacdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faacdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4bf796bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4bf796a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4bf77b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4bf42ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4bf42ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faacdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faacdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faacdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4bf42aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (1651 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566436bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566436bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566436c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ce4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ce4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ce4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ce4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556643655bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556643655a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055664363a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566432e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566432e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ce4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ce4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ce4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566432e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (1652 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/48385) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e657f75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e657f72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e657f7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0c9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0c9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0c9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0c9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e657f0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e657f0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e657ef08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e657b9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e657b9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0c9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0c9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0c9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e657b9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (1653 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<vscale x
# | ...
# `---data was truncated (10240/119289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec4fc3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec4fc39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec4fc3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ce9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ce9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ce9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ce9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec4fbd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec4fbd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec4fbb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec4f866e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec4f866b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ce9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ce9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ce9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec4f866a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (1654 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.
# | ...
# `---data was truncated (10240/78156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056014086ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560140869e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056014086d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42d5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42d5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42d5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42d5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560140802bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560140802a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601407e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560140496e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560140496b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42d5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42d5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42d5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560140496a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (1655 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b68125eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b68122e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b6812662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa402733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa40278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa402733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa40271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b680bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b680bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b680a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b67d4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b67d4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa40271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa40271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa40271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b67d4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (1656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = ashr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = lshr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = ashr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = lshr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @lshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %shl = shl <8 x i32> %0, %1
# |   store <8 x i32> %shl, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @rshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %r
# | ...
# `---data was truncated (10240/50943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b9e6361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9e635ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9e636262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f499fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f499fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f499fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f499fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9e62f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9e62f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9e62dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9e5f8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9e5f8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f499fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f499fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f499fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9e5f8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (1657 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c36a08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c36a05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c36a0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4896449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48964a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4896449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4896431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c3699ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c3699ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c369838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c36632e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c36632b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4896432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48964330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48964330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c36632a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (1658 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d    -target-feature +v -target-feature +zfh -target-feature +zvfh    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 8)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t(<vscale x 16 x i8> %dest, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 8)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560184874eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560184871e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056018487562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0d3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0d30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0d3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0d3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056018480abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056018480aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601847ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056018449ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056018449eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0d3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0d30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0d30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056018449ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (1659 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bfe965eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bfe962e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bfe96662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f832e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f832e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f832e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f832e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bfe8fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bfe8fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bfe8e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bfe58fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bfe58fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f832e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f832e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f832e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bfe58fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (1660 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a69fb06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a69fb03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a69fb0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4da7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4da775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4da7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4da76ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a69fa9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a69fa9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a69fa818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a69f730e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a69f730b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4da76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4da76ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4da76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a69f730a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (1661 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec675c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec675bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec675c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcd1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcd158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcd1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcd151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec67557bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec67557a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec6753c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec671ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec671ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcd151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcd151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcd151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec671eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (1662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649fd8e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649fd8e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649fd8e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaafd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaafd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaafd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaafd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649fd87dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649fd87da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649fd8628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649fd511e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649fd511b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaafd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaafd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaafd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649fd511a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (1663 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbf2390eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbf238de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbf239162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe016f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe016f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe016f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe016f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbf2326bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbf2326a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbf230b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbf1fbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbf1fbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe016f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe016f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe016f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbf1fbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (1664 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb3ccb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb3ccb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb3ccb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4ee933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4ee98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4ee933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4ee91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb3cc4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb3cc4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb3cc338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb3c8e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb3c8e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4ee91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4ee91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4ee91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb3c8e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (1665 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557062e54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557062e51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557062e5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4200449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42004a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4200449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4200431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557062deabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557062deaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557062dcf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557062a7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557062a7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4200432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42004330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42004330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557062a7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (1666 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557595bf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557595bf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557595bf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a0d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a0d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a0d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a0d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557595b8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557595b8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557595b728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557595821e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557595821b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a0d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a0d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a0d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557595821a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (1667 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/13625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d28b5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d28b58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d28b5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa870d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa870d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa870d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa870d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d28af1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d28af1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d28ad68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d28785e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d28785b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa870d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa870d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa870d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d28785a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (1668 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64
# | ...
# `---data was truncated (10240/97248) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eac6eceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eac6ecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eac6ecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ae8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ae818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ae8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ae811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eac6e64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eac6e64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eac6e498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eac6af8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eac6af8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ae811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ae811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ae811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eac6af8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (1669 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564460ce2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564460cdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564460ce362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f415a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f415a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f415a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f415a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564460c78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564460c78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564460c5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056446090ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056446090cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f415a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f415a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f415a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056446090ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (1670 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3df1d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3df1d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3df1da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73ba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73ba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73ba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73ba51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3df16fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3df16fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3df1548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3dee03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3dee03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73ba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73ba51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73ba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3dee03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (1671 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr
# | ...
# `---data was truncated (10240/14461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e24bd15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e24bd12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e24bd1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43fa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43fa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43fa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43fa403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e24bcabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e24bcaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e24bc908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e24b93fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e24b93fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43fa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43fa4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43fa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e24b93fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (1672 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/12656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4f8f4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4f8f4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4f8f5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c9ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c9ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c9ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c9ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4f8ee5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4f8ee5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4f8eca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4f8b79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4f8b79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c9ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c9ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c9ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4f8b79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (1673 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd3b9f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd3b9f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd3b9f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7cde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7cde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7cde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7cde03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd3b98ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd3b98ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd3b9738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd3b622e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd3b622b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7cde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7cde050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7cde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd3b622a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (1674 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i)
# |   store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i)
# |   store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055de8ce02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de8cdffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de8ce0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f666d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f666d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f666d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f666d403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de8cd98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de8cd98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de8cd7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de8ca2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de8ca2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f666d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f666d4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f666d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de8ca2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (1675 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055baa9cabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055baa9ca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055baa9cac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe48eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe48eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe48eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe48eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baa9c41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055baa9c41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055baa9c268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055baa98d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055baa98d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe48eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe48eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe48eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baa98d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (1676 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd96938eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd96935e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd9693962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c5481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c548725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c5481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c54803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd968cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd968cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd968b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd96562e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd96562b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c54804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c548050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c548050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd96562a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (1677 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/41651) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055954d010eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055954d00de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055954d01162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe66af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe66af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe66af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe66af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055954cfa6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055954cfa6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055954cf8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055954cc3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055954cc3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe66af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe66af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe66af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055954cc3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (1678 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 
# | ...
# `---data was truncated (10240/73182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d2180beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d21808e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d2180c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff99b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff99b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff99b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff99b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d217a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d217a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d217868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d21435e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d21435b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff99b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff99b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff99b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d21435a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (1679 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed67d09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed67d06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed67d0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2237933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f223798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2237933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f223791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed67c9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed67c9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed67c848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed67933e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed67933b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f223791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f223791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f223791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed67933a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (1680 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561008679eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561008676e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056100867a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb768849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb768849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb768831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056100860fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056100860fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610085f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610082a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610082a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb768832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610082a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (1681 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555950667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555950664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055595066862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc52ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc52ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc52ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc52ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559505fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559505fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559505e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555950291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555950291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc52ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc52ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc52ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555950291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (1682 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622c981beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622c9818e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622c981c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f819481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81948725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f819481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8194803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622c97b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622c97b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622c97968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622c9445e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622c9445b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8194804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81948050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81948050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622c9445a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (1683 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055deeaa8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055deeaa87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055deeaa8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde99733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde9978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde99733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde9971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055deeaa20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055deeaa20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055deeaa058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055deea6b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055deea6b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde9971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde9971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde9971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055deea6b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (1684 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b756d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b756d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b756d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97a4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97a418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97a4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97a411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b7566abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b7566aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b7564f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b752fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b752feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97a411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97a411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97a411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b752fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (1685 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055647336beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556473368e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055647336c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72b5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72b558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72b5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72b551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556473301bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556473301a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564732e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556472f95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556472f95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72b551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72b551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72b551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556472f95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (1686 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2340b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2340b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2340b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f23404abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f23404aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f23402f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f233cdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f233cdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7aa111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f233cdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (1687 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555aa2879eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555aa2876e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555aa287a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46baa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46baa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46baa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46baa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555aa280fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555aa280fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555aa27f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555aa24a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555aa24a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46baa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46baa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46baa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aa24a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (1688 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i)
# |   %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8>
# |   store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i)
# |   %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i)
# |   %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8>
# |   store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i)
# |   %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005607e4527eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607e4524e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607e452862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1549505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f154955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1549505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15494ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e44bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607e44bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607e44a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607e4151e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607e4151b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15494eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15494ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15494ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e4151a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (1689 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f808585eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f808582e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f80858662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaa9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaa998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaa9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaa991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f80851bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f80851ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8085008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8081afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8081afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdaa991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaa991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaa991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8081afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (1690 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cb49c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cb49c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cb49ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2f1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2f12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2f1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2f1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cb495fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cb495fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cb49448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cb45f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cb45f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2f1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2f12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2f12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cb45f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (1691 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556955302eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569552ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055695530362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38a0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38a038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38a0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38a031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556955298bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556955298a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055695527d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556954f2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556954f2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38a031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38a031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38a031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556954f2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (1692 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625cb8caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625cb8c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625cb8cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ee6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ee638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ee6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ee631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625cb860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625cb860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625cb8458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625cb4f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625cb4f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ee631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ee631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ee631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625cb4f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (1693 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618a13e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618a13e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618a13ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ab4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ab40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ab4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ab4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618a137fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618a137fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618a13648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618a1013e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618a1013b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ab4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ab40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ab40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618a1013a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (1694 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056377354aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563773547e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056377354b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b1ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b1ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b1ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b1ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637734e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637734e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637734c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563773174e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563773174b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b1ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b1ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b1ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563773174a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (1695 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/65723) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a888270eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a88826de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a88827162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47fe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47fe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47fe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47fe031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a888206bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a888206a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8881eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a887e9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a887e9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47fe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47fe0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47fe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a887e9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (1696 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bc8e66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bc8e63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bc8e6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb72f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb72f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb72f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb72f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bc8dfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bc8dfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bc8de18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bc8a90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bc8a90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb72f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb72f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb72f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bc8a90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (1697 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c362742eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c36273fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c36274362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d0da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d0daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d0da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d0da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3626d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3626d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3626bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c36236ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c36236cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d0da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d0da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d0da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c36236ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (1698 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/98581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055744cbcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055744cbc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055744cbcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b2ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b2ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b2ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b2ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055744cb61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055744cb61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055744cb468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055744c7f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055744c7f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b2ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b2ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b2ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055744c7f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (1699 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2a97abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2a97a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2a97ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f3141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f314725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f3141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f31403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2a9741bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2a9741a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2a97268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2a93d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2a93d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f31404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f314050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f314050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2a93d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (1700 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb4a62beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb4a628e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb4a62c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f945bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f945bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f945bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f945bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb4a5c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb4a5c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb4a5a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb4a255e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb4a255b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f945bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f945bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f945bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb4a255a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (1701 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) 
# | ...
# `---data was truncated (10240/68437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648910a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648910a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648910a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056489103bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056489103ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648910208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564890ccfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564890ccfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74a8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564890ccfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (1702 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c2bc3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c2bc38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c2bc3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb2fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb2fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb2fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb2fe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c2bbd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c2bbd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c2bbb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c2b865e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c2b865b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb2fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb2fe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb2fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c2b865a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (1703 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80)
# |   %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64)
# |   %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4)
# |   %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1
# |   store <2 x i64> %6, ptr %0, align 8
# |   %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614c2702eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614c26ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614c270362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f864f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f864f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f864f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f864f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614c2698bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614c2698a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614c267d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614c232ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614c232cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f864f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f864f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f864f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614c232ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (1704 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/95445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558249d0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558249d08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558249d0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b35649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b356a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b35649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b35631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558249ca1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558249ca1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558249c868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558249935e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558249935b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b35632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b356330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b356330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558249935a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (1705 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b020a0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b020a08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b020a0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee63a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee63aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee63a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee63a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0209a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0209a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0209868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b020635e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b020635b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee63a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee63a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee63a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b020635a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (1706 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff41cefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff41cece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff41cf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57c2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57c20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57c2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57c2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff41c85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff41c85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff41c6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff41919e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff41919b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57c2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57c20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57c20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff41919a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (1707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056435b17eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056435b17be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056435b17f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a11133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a1118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a11133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a1111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056435b114bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056435b114a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056435b0f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056435ada8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056435ada8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a1111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a1111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a1111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056435ada8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (1708 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7abbb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7abbb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7abbb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b53049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b530a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b53049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b53031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7abb49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7abb49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7abb2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7ab7dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7ab7ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b53032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b530330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b530330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7ab7dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (1709 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631f439deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631f439ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631f439e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f496021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49602725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f496021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4960203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631f4333bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631f4333a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631f43188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631f3fc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631f3fc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4960204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49602050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49602050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631f3fc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (1710 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646ee727eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646ee724e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646ee72862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf62b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf62b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf62b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf62b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646ee6bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646ee6bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646ee6a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646ee351e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646ee351b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf62b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf62b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf62b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646ee351a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (1711 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596ef5d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596ef5d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596ef5da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0489533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f048958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0489533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f048951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596ef56fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596ef56fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596ef5548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596ef203e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596ef203b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f048951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f048951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f048951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596ef203a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (1712 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561cc7656eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561cc7653e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561cc765762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbc741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbc74725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbc741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbc7403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561cc75ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561cc75eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561cc75d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561cc7280e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561cc7280b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbc7404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbc74050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbc74050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cc7280a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (1713 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559009d6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559009d6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559009d6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0be6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0be62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0be6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0be6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559009d04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559009d04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559009ce98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559009998e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559009998b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0be6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0be62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0be62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559009998a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (1714 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558de8ecfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558de8ecce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558de8ed062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd48e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd48e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd48e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd48e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558de8e65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558de8e65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558de8e4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558de8af9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558de8af9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd48e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd48e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd48e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558de8af9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (1715 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afa67dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afa67dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afa67e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27b901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27b90725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27b901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27b9003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afa6775bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afa6775a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afa675a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afa6409e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afa6409b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27b9004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27b90050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27b90050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afa6409a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (1716 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055948a378eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055948a375e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055948a37962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb68649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb686a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb68649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb68631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055948a30ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055948a30ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055948a2f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559489fa2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559489fa2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb68632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb686330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb686330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559489fa2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (1717 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559580716eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559580713e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055958071762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f725081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72508725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f725081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7250803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595806acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595806aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595806918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559580340e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559580340b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7250804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72508050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72508050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559580340a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (1718 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddef8cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddef8cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddef8ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85d1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85d1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85d1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85d1ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddef863bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddef863a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddef8488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddef4f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddef4f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85d1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85d1cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85d1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddef4f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (1719 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset, i64 no
# | ...
# `---data was truncated (10240/287205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fab2b05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fab2b02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fab2b0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f8c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f8c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f8c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f8c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fab2a9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fab2a9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fab2a808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fab272fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fab272fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f8c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f8c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f8c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fab272fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (1720 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b02e6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b02e6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b02e7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4636d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4636d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4636d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4636d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b02e05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b02e05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b02dea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b02a99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b02a99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4636d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4636d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4636d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b02a99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (1721 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a59ca7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a59ca4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a59ca862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fe4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fe4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fe4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fe4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a59c3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a59c3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a59c228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a598d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a598d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5fe4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fe4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fe4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a598d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (1722 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602084b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602084b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602084b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf2201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf220725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf2201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf22003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056020844ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056020844ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602084338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602080e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602080e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf22004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf220050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf220050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602080e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (1723 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616eafc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616eafc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616eafc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3a2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3a298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3a2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3a291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616eaf5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616eaf5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616eaf3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616eabeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616eabeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3a291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3a291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3a291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616eabeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (1724 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ffd1ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ffd1e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ffd1ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f434f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f434f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f434f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f434f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ffd181bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ffd181a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ffd1668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ffce15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ffce15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f434f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f434f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f434f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ffce15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (1725 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9066b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9066b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9066ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54c0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54c098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54c0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54c091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c90664fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c90664fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9066348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9062e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9062e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54c091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54c091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54c091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9062e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (1726 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af64069eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af64066e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af6406a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b18533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b1858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b18533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b1851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af63fffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af63fffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af63fe48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af63c93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af63c93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b1851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b1851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b1851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af63c93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (1727 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# |  #0 0x000055b42e3afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b42e3ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b42e3b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff31d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff31d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff31d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff31d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b42e345bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b42e345a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b42e32a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b42dfd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b42dfd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff31d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff31d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff31d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b42dfd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (1728 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcb8e38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcb8e35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcb8e3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3740b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3740b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3740b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3740b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcb8dcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcb8dcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcb8db38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcb8a62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcb8a62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3740b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3740b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3740b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcb8a62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (1729 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056326ded6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056326ded3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056326ded762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e0731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056326de6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056326de6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056326de518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056326db00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056326db00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e0731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056326db00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (1730 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd604d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd604d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd604d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa36ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd6046bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd6046ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd604508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd600ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd600ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7aa36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa36ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd600ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (1731 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560aad7faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560aad7f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560aad7fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f954f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f954f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f954f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f954f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560aad790bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560aad790a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560aad7758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560aad424e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560aad424b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f954f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f954f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f954f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560aad424a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (1732 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a8adf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a8adefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a8adf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe074705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe07475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe074705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0746ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a8ad88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a8ad88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a8ad6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a8aa1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a8aa1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0746eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0746ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0746ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a8aa1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (1733 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559845d89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559845d86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559845d8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa942133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa94218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa942133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa94211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559845d1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559845d1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559845d048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598459b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598459b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa94211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa94211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa94211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598459b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (1734 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp sge <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp uge <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp sge <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581ea6eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581ea6e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581ea6eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe574649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5746a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe574649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe574631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581ea680bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581ea680a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581ea6658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581ea314e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581ea314b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe574632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5746330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5746330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581ea314a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (1735 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564526a8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564526a88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564526a8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff22b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff22b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff22b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff22b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564526a21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564526a21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564526a068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645266b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645266b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff22b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff22b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff22b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645266b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (1736 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/64341) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d51b731eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d51b72ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d51b73262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d06249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d06249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d06231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d51b6c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d51b6c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d51b6ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d51b35be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d51b35bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d06232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d062330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d51b35ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (1737 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4f84b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4f84b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4f84b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15dfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15dfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15dfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15dfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4f844ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4f844ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4f84338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4f80e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4f80e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15dfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15dfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15dfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4f80e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (1738 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fb5e68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fb5e65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fb5e6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3b7d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3b7d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3b7d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3b7ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fb5dfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fb5dfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fb5de38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fb5a92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fb5a92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3b7ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3b7cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3b7cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fb5a92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (1739 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556af5acceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556af5ac9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556af5acd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556af5a62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556af5a62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556af5a478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556af56f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556af56f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556af56f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (1740 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad6e497eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad6e494e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad6e49862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b46f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b46f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b46f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b46f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad6e42dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad6e42da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad6e4128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad6e0c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad6e0c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b46f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b46f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b46f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad6e0c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (1741 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563422d96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563422d93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563422d9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a50249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a502a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a50249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a50231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563422d2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563422d2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563422d118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634229c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634229c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a50232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a502330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a502330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634229c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (1742 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055708bd69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055708bd66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055708bd6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4bdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4bdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4bdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4bdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055708bcffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055708bcffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055708bce48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055708b993e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055708b993b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4bdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4bdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4bdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055708b993a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (1743 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558683489eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558683486e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055868348a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc303d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc303d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc303d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc303d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055868341fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055868341fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586834048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586830b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586830b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc303d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc303d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc303d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586830b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (1744 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   
# | ...
# `---data was truncated (10240/19123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565d9b46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565d9b43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565d9b4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8afed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8afed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8afed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8afed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565d9adcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565d9adca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565d9ac18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565d9770e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565d9770b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8afed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8afed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8afed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565d9770a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (1745 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b22088ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b220889e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b22088d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96d3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96d34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96d3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96d3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b220822bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b220822a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2208078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2204b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2204b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96d3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96d34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96d34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2204b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (1746 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = fneg <8 x half> %1
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = fneg <4 x float> %1
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %c, ptr %c.addr, align 2
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = mul <8 x i16> %0, %.splat
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = add <8 x i16> %2, %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i32 %c, ptr %c.addr, align 4
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = mul <4 x i32> %0, %.splat
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = add <4 x i32> %2, %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, ali
# | ...
# `---data was truncated (10240/60411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000558772380eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055877237de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055877238162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f419c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f419c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f419c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f419c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558772316bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558772316a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587722fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558771faae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558771faab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f419c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f419c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f419c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558771faaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (1747 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/60817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556066a9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556066a98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556066a9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f885ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f885aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f885ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f885ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556066a31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556066a31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556066a168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560666c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560666c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f885ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f885ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f885ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560666c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (1748 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsmul_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d0296eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d0296be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d0296f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ade733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ade78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ade733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ade71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d02904bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d02904a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d028e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d02598e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d02598b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ade71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ade71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ade71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d02598a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (1749 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e72714beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e727148e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e72714c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14cf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14cf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14cf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14cf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7270e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7270e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7270c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e726d75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e726d75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14cf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14cf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14cf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e726d75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (1750 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056411ab48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056411ab45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056411ab4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3ca049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3ca0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3ca049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3ca031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056411aadebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056411aadea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056411aac38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056411a772e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056411a772b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3ca032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3ca0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3ca0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056411a772a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (1751 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559eab130eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559eab12de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559eab13162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58b8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58b8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58b8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58b8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559eab0c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559eab0c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559eab0ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559eaad5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559eaad5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58b8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58b8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58b8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559eaad5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (1752 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/142024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652d1c75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652d1c72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652d1c7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f754b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f754b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f754b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f754b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652d1c0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652d1c0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652d1bf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652d189fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652d189fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f754b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f754b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f754b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652d189fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (1753 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i
# | ...
# `---data was truncated (10240/41934) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f20af2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f20aefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f20af362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd87a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd87a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd87a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd87a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f20a88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f20a88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f20a6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f2071ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f2071cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd87a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd87a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd87a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f2071ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (1754 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <4 x bfloat>, ptr %__promote, align 8
# |   store <4 x bfloat> %1, ptr %__ret, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %2, ptr %tmp, align 8
# |   %3 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x bfloat>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %low.addr = alloca <4 x bfloat>, align 8
# |   %high.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %low, ptr %low.addr, align 8
# |   store <4 x bfloat> %high, ptr %high.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %low.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %high.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x bfloat>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1, align 8
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x bfloat>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1, align 16
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005555f25ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555f25e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555f25ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2687933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f268798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2687933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f268791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555f2581bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555f2581a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555f25668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555f2215e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555f2215b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f268791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f268791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f268791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555f2215a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (1755 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056005ff68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056005ff65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056005ff6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe45f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe45f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe45f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe45f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056005fefebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056005fefea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056005fee38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056005fb92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056005fb92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe45f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe45f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe45f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056005fb92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (1756 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e08f29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e08f26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e08f2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad28c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad28ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad28c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad28c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e08ebfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e08ebfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e08ea48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e08b53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e08b53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad28c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad28c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad28c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e08b53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (1757 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633fcb23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633fcb20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633fcb2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e8f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e8f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e8f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e8f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633fcab9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633fcab9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633fca9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633fc74de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633fc74db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e8f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e8f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e8f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633fc74da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (1758 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555cb843eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555cb840e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555cb84462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff51649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff516a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff51649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff51631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555cb7d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555cb7d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555cb7be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555cb46de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555cb46db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff51632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff516330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff516330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555cb46da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (1759 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/83080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2a611eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2a611be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2a611f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cb1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cb1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cb1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cb1aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2a60b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2a60b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2a60998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2a5d48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2a5d48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5cb1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cb1aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cb1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2a5d48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (1760 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/39586) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aef5b9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aef5b97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aef5b9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa48621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4862725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa48621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa486203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aef5b30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aef5b30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aef5b158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aef57c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aef57c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa486204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4862050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4862050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aef57c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (1761 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570f797aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570f7977e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570f797b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4847249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48472a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4847249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4847231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570f7910bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570f7910a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570f78f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570f75a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570f75a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4847232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48472330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48472330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570f75a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (1762 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @test_vlenb() #0 {
# | entry:
# |   %0 = call i32 @llvm.read_register.i32(metadata !4)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.read_register.i32(metadata) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"vlenb"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x0000562d20466eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d20463e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d2046762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24ff049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24ff0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24ff049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24ff031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d203fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d203fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d203e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d20090e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d20090b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24ff032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24ff0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24ff0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d20090a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-cde-vfp.c (1763 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 {
# | entry:
# |   %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)
# |   %1 = bitcast float %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = load i32, ptr %m.addr, align 4
# |   %5 = bitcast i32 %4 to float
# |   %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5)
# |   %7 = bitcast float %6 to i32
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 {
# | entry:
# |   %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)
# |   %1 = bitcast double %0 to i64
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %m.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = load i64, ptr %m.addr, align 8
# |   %5 = bitcast i64 %4 to double
# |   %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5)
# |   %7 = bitcast double %6 to i64
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636187d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636187d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636187d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8d9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8d978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8d9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8d971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056361876cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056361876ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636187518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563618400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563618400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8d971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8d971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8d971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563618400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (1764 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056514d656eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056514d653e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056514d65762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f447e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f447e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f447e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f447e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056514d5ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056514d5eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056514d5d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056514d280e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056514d280b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f447e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f447e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f447e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056514d280a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (1765 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b003fbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b003fbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b003fbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61a9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61a958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61a9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61a951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b003f53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b003f53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b003f388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b003be7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b003be7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61a951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61a951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61a951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b003be7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (1766 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llv
# | ...
# `---data was truncated (10240/20513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e4b3b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e4b3b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e4b3b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7018105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f701815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7018105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70180ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e4b34ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e4b34ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e4b3338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e4afe2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e4afe2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70180eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70180ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70180ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e4afe2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (1767 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/18867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b6f610eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b6f60de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b6f61162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f139cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f139cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f139cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f139caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b6f5a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b6f5a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b6f58b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b6f23ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b6f23ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f139caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f139caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f139caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b6f23aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (1768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdd07deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bdd07ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bdd07e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f13249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f132a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f13249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f13231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdd013bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bdd013a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bdcff88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bdcca7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bdcca7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f13232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f132330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f132330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bdcca7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (1769 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x d
# | ...
# `---data was truncated (10240/19901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dafd6d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dafd6d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dafd6d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff871533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff87158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff871533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff87151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dafd66abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dafd66aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dafd64f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dafd2fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dafd2feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff87151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff87151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff87151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dafd2fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (1770 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580d0464eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580d0461e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580d046562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2422533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f242258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2422533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f242251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580d03fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580d03faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580d03df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580d008ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580d008eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f242251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f242251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f242251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580d008ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (1771 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwi
# | ...
# `---data was truncated (10240/235604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b7e078eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b7e075e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b7e07962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f447c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f447c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f447c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f447c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b7e00ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b7e00ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b7dff38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b7dca2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b7dca2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f447c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f447c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f447c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b7dca2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (1772 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586840bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586840b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586840bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c63933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c6398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c63933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c6391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558684051bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558684051a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586840368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558683ce5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558683ce5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c6391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c6391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c6391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558683ce5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (1773 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622c58e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622c58e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622c58ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ea7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ea798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ea7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ea791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622c587fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622c587fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622c58648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622c5513e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622c5513b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ea791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ea791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ea791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622c5513a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (1774 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da7c6baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da7c6b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da7c6bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9934e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9934ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9934e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9934e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da7c650bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da7c650a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da7c6358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da7c2e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da7c2e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9934e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9934e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9934e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da7c2e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (1775 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dfbd0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dfbd08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dfbd0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a32d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a32d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a32d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a32d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dfbca1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dfbca1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dfbc868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dfb935e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dfb935b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a32d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a32d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a32d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dfb935a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (1776 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557571b3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557571b3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557571b3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd523a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd523aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd523a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd523a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557571ad4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557571ad4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557571ab98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557571768e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557571768b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd523a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd523a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd523a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557571768a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (1777 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a190f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a190f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a190f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb502c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb502ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb502c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb502c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a19089bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a19089a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a1906e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a18d1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a18d1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb502c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb502c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb502c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a18d1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (1778 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555793842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055579383fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055579384362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bf9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bf958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bf9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bf951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557937d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557937d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557937bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055579346ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055579346cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bf951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bf951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bf951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055579346ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (1779 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4d481deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4d481ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4d481e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe77e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe77ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe77e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe77e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4d47b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4d47b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4d47988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4d4447e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4d4447b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe77e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe77e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe77e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4d4447a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (1780 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bad4b1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bad4b19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bad4b1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f2b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f2b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f2b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f2b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad4ab2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bad4ab2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bad4a978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bad4746e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bad4746b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f2b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f2b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f2b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad4746a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (1781 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c27ff11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c27ff0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c27ff1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4ab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4ab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4ab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4ab31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c27fea7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c27fea7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c27fe8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c27fb3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c27fb3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4ab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4ab31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4ab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c27fb3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (1782 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056318b76ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056318b769e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056318b76d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9574249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95742a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9574249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9574231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056318b702bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056318b702a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056318b6e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056318b396e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056318b396b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9574232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95742330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95742330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056318b396a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (1783 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005594ecae9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594ecae6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594ecaea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe50dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe50dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe50dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe50dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594eca7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594eca7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594eca648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594ec713e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594ec713b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe50dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe50dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe50dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594ec713a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (1784 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba21a61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba21a5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba21a6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5513a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5513aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5513a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5513a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba219f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba219f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba219dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba2168be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba2168bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5513a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5513a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5513a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba2168ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (1785 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfm
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a652b5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a652b58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a652b5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c08333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c0838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c08333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c0831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a652af1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a652af1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a652ad68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a652785e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a652785b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c0831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c0831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c0831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a652785a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (1786 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644e2006eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644e2003e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644e200762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e8a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e8a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e8a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e8a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644e1f9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644e1f9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644e1f818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644e1c30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644e1c30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e8a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e8a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e8a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644e1c30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (1787 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e792664eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e792661e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e79266562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f227fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f227fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f227fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f227fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7925fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7925faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7925df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e79228ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e79228eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f227fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f227fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f227fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e79228ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (1788 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ad6692eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ad668fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ad669362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50d7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50d778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50d7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50d771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ad6628bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ad6628a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ad660d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ad62bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ad62bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50d771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50d771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50d771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ad62bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (1789 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055775c1ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055775c1fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055775c20062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f456fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f456faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f456fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f456fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055775c195bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055775c195a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055775c17a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055775be29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055775be29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f456fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f456fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f456fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055775be29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (1790 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562770e3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562770e38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562770e3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b9ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b9ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b9ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b9ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562770dd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562770dd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562770db68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562770a65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562770a65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b9ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b9ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b9ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562770a65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (1791 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edb6b26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edb6b23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edb6b2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd8cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd8cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd8cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd8cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edb6abcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edb6abca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edb6aa18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edb6750e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edb6750b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd8cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd8cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd8cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edb6750a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (1792 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vasub_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556980c84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556980c81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556980c8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd63cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd63cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd63cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd63cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556980c1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556980c1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556980bff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569808aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569808aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd63cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd63cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd63cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569808aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (1793 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b68bd8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b68bd88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b68bd8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc90f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc90f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc90f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc90f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b68bd21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b68bd21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b68bd068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b68b9b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b68b9b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc90f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc90f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc90f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b68b9b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (1794 of 27910)
******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# |  #0 0x000055a86f142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a86f13fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a86f14362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f2b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f2b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f2b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f2b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a86f0d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a86f0d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a86f0bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a86ed6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a86ed6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f2b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f2b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f2b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a86ed6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (1795 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555804339eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555804336e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055580433a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e2df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e2df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e2df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e2df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558042cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558042cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558042b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555803f63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555803f63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e2df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e2df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e2df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555803f63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (1796 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565244862eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056524485fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056524486362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5427e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5427ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5427e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5427e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652447f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652447f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652447dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056524448ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056524448cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5427e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5427e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5427e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056524448ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (1797 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b1d8aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b1d8abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b1d8af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00a8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00a8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00a8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00a8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b1d844bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b1d844a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b1d8298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b1d4d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b1d4d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00a8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00a8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00a8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b1d4d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (1798 of 27910)
******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | %struct.S = type { ptr, ptr }
# | %struct.T = type { [2 x ptr] }
# | %struct.SS = type { ptr }
# | 
# | @__hip_cuid_ = addrspace(1) global i8 0
# | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4
# |   %1 = load i32, ptr %0, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 {
# | entry:
# |   %x.addr = alloca ptr addrspace(2), align 8, addrspace(5)
# |   %y.addr = alloca ptr addrspace(1), align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr
# |   store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8
# |   store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8
# |   %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0
# |   %1 = load i32, ptr addrspace(2) %arrayidx, align 4
# |   %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8
# |   %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0
# |   store i32 %1, ptr addrspace(1) %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind
# | define dso_local void @_Z4funcPi(ptr noundef %x) #1 {
# | entry:
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr %x, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 {
# | entry:
# |   %s = alloca %struct.S, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %s.ascast = addrspacecast ptr addrspace(5) %s to ptr
# |   %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1
# |   %3 = load ptr, ptr %y, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %4, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 {
# | entry:
# |   %s = alloca ptr, align 8, addrspace(5)
# |   %s.addr = alloca ptr, align 8, addrspace(5)
# |   %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr
# |   store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8
# |   %s1 = load ptr, ptr addrspace(5) %s, align 8
# |   store ptr %s1, ptr %s.addr.ascast, align 8
# |   %0 = load ptr, ptr %s.addr.ascast, align 8
# |   %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %3 = load ptr, ptr %s.addr.ascast, align 8
# |   %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1
# |   %4 = load ptr, ptr %y, align 8
# |   %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0
# |   %5 = load float, ptr %arrayidx2, align 4
# |   %add = fadd contract float %5, 1.000000e+00
# |   store float %add, ptr %arrayidx2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 {
# | entry:
# |   %t = alloca %struct.T, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %t.ascast = addrspacecast ptr addrspace(5) %t to ptr
# |   %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0
# |   %1 = load ptr, ptr %arrayidx, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0
# |   %2 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %2, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1
# |   %3 = load ptr, ptr %arrayidx3, align 8
# |   %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx4, align 4
# |   %add5 = fadd contract float %4, 2.000000e+00
# |   store float %add5, ptr %arrayidx4, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 {
# | entry:
# |   %a = alloca %struct.SS, align 8, addrspace(5)
# |   %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0
# |   store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8
# |   %a.ascast = addrspacecast ptr addrspace(5) %a to ptr
# |   %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0
# |   %0 = load ptr, ptr %x, align 8
# |   %1 = load float, ptr %0, align 4
# |   %add = fadd contract float %1, 3.000000e+00
# |   store float %add, ptr %0, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !2 = !{!"clang version 24.0.0"}
# | !3 = !{}
# | !4 = !{i64 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x0000564748836eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564748833e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056474883762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc77301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7730725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc77301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc773003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647487ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647487cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647487b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564748460e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564748460b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc773004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7730050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7730050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564748460a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/SystemZ/zvector.c (1799 of 27910)
******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector  -emit-llvm -o - -W -Wall -Werror  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c"
# | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
# | target triple = "s390x-unknown-linux-gnu"
# | 
# | @sc2 = global <16 x i8> zeroinitializer, align 8
# | @sc = global <16 x i8> zeroinitializer, align 8
# | @uc2 = global <16 x i8> zeroinitializer, align 8
# | @uc = global <16 x i8> zeroinitializer, align 8
# | @ss2 = global <8 x i16> zeroinitializer, align 8
# | @ss = global <8 x i16> zeroinitializer, align 8
# | @us2 = global <8 x i16> zeroinitializer, align 8
# | @us = global <8 x i16> zeroinitializer, align 8
# | @si2 = global <4 x i32> zeroinitializer, align 8
# | @si = global <4 x i32> zeroinitializer, align 8
# | @ui2 = global <4 x i32> zeroinitializer, align 8
# | @ui = global <4 x i32> zeroinitializer, align 8
# | @sl2 = global <2 x i64> zeroinitializer, align 8
# | @sl = global <2 x i64> zeroinitializer, align 8
# | @ul2 = global <2 x i64> zeroinitializer, align 8
# | @ul = global <2 x i64> zeroinitializer, align 8
# | @slll2 = global <1 x i128> zeroinitializer, align 8
# | @slll = global <1 x i128> zeroinitializer, align 8
# | @ulll2 = global <1 x i128> zeroinitializer, align 8
# | @ulll = global <1 x i128> zeroinitializer, align 8
# | @fd2 = global <2 x double> zeroinitializer, align 8
# | @fd = global <2 x double> zeroinitializer, align 8
# | @bc2 = global <16 x i8> zeroinitializer, align 8
# | @bc = global <16 x i8> zeroinitializer, align 8
# | @bs2 = global <8 x i16> zeroinitializer, align 8
# | @bs = global <8 x i16> zeroinitializer, align 8
# | @bi2 = global <4 x i32> zeroinitializer, align 8
# | @bi = global <4 x i32> zeroinitializer, align 8
# | @bl2 = global <2 x i64> zeroinitializer, align 8
# | @bl = global <2 x i64> zeroinitializer, align 8
# | @blll2 = global <1 x i128> zeroinitializer, align 8
# | @blll = global <1 x i128> zeroinitializer, align 8
# | @cnt = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_assign() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_pos() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_neg() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %sub = sub <16 x i8> zeroinitializer, %0
# |   store volatile <16 x i8> %sub, ptr @sc, align 8
# |   %1 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %sub1 = sub <8 x i16> zeroinitializer, %1
# |   store volatile <8 x i16> %sub1, ptr @ss, align 8
# |   %2 = load volatile <4 x i32>, ptr @si2, align 8
# |   %sub2 = sub <4 x i32> zeroinitializer, %2
# |   store volatile <4 x i32> %sub2, ptr @si, align 8
# |   %3 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %sub3 = sub <2 x i64> zeroinitializer, %3
# |   store volatile <2 x i64> %sub3, ptr @sl, align 8
# |   %4 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %sub4 = sub <1 x i128> zeroinitializer, %4
# |   store volatile <1 x i128> %sub4, ptr @slll, align 8
# |   %5 = load volatile <2 x double>, ptr @fd2, align 8
# |   %fneg = fneg <2 x double> %5
# |   store volatile <2 x double> %fneg, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_preinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_postinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_predec() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %dec = add <16 x i8> %0, splat (i8 -1)
# |   store volatile <16 x i8> %dec, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %dec1 = add <16 x i8> %1, splat (i8 -1)
# |   store volatile <16 x i8> %dec1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %dec2 = add <8 x i16> %2, splat (i16 -1)
# |   store volatile <8 x i16> %dec2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %dec3 = add <8 x i16> %3, splat (i16 -1)
# |   store volatile <8 x i16> %dec3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %dec4 = add <4 x i32> %4, splat (i32 -1)
# |   store volatile <4 x i32> %dec4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %dec5 = add <4 x i32> %5, splat (i32 -1)
# |   store volatile <4 x i32> %dec5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %dec6 = add <2 x i64> %6, splat (i64 -1)
# |   store volatile <2 x i64> %dec6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %dec7 = add <2 x i64> %7, splat (i64 -1)
# |   store volatile <2 x i64> %dec7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %dec8 = add <1 x i128> %8, splat (i128 -1)
# |   store volatile <1 x i128> %dec8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %dec
# | ...
# `---data was truncated (10240/152876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598a16a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598a16a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598a16a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b7cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b7cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b7cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b7cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598a163ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598a163ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598a16238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598a12d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598a12d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b7cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b7cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b7cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598a12d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (1800 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm
# | ...
# `---data was truncated (10240/35597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e844700eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8446fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e84470162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb602849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb602849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb602831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e844696bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e844696a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e84467b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e84432ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e84432ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb602832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6028330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e84432aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (1801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = e
# | ...
# `---data was truncated (10240/100513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eab6b64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eab6b61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eab6b6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc174b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc174b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc174b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc174b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eab6afabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eab6afaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eab6adf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eab678ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eab678eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc174b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc174b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc174b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eab678ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (1802 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c2926ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c29269e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c2926d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e9af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c29202bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c29202a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c291e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c28e96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c28e96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c28e96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (1803 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e45dbdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e45dbd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e45dbdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b9c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b9c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b9c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b9c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e45db72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e45db72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e45db578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e45d806e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e45d806b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b9c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b9c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b9c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e45d806a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (1804 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ca8b0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ca8b09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ca8b0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94bad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94bad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94bad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94bad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ca8aa2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ca8aa2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ca8a878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ca8736e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ca8736b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94bad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94bad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94bad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ca8736a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (1805 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 
# | ...
# `---data was truncated (10240/28361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa1a065eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa1a062e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa1a06662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73fcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73fcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73fcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73fcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa19ffbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa19ffba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa19fe08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa19c8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa19c8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73fcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73fcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73fcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa19c8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (1806 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync
# | ...
# `---data was truncated (10240/10618) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056118959deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056118959ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056118959e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6e2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6e2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6e2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6e2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561189533bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561189533a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611895188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611891c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611891c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6e2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6e2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6e2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611891c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (1807 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.a
# | ...
# `---data was truncated (10240/41678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f410d29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f410d26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f410d2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f054a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f054a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f054a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f054a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f410cbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f410cbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f410ca48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f410953e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f410953b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f054a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f054a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f054a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f410953a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (1808 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617b7207eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617b7204e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617b720862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f9f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f9f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f9f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f9f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617b719dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617b719da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617b71828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617b6e31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617b6e31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f9f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f9f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f9f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617b6e31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (1809 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3e1981eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3e197ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3e198262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73cd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73cd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73cd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73cd803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3e1917bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3e1917a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3e18fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3e15abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3e15abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73cd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73cd8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73cd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3e15aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (1810 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f90a3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f90a37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f90a3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4110649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41106a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4110649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4110631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f909d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f909d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f909b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f90664e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f90664b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4110632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41106330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41106330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f90664a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (1811 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5a8cdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5a8cdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5a8cdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad5d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad5d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad5d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad5d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5a8c74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5a8c74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5a8c598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5a8908e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5a8908b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad5d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad5d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad5d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5a8908a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (1812 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/79853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569664f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569664f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569664fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1775249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17752a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1775249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1775231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055696648fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055696648fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569664748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556966123e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556966123b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1775232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17752330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17752330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556966123a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (1813 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/39578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556228589eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556228586e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055622858a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2332933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f233298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2332933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f233291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055622851fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055622851fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562285048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562281b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562281b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f233291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f233291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f233291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562281b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (1814 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset
# | ...
# `---data was truncated (10240/287213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd0535beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd05358e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd0535c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc225449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2254a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc225449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc225431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd052f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd052f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd052d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd04f85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd04f85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc225432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2254330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2254330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd04f85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (1815 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9a5b00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9a5afde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9a5b0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87fe71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9a5a96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9a5a96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9a5a7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9a572ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9a572ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9a572aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (1816 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb28d62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb28d5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb28d6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff70eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff70eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff70eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff70eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb28cf8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb28cf8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb28cdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb2898ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb2898cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff70eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff70eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff70eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb2898ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (1817 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f795c4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f795c48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f795c4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4df4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4df4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4df4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4df4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f795be1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f795be1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f795bc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f795875e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f795875b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4df4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4df4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4df4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f795875a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (1818 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055601a690eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055601a68de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055601a69162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80dde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80ddea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80dde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80dde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055601a626bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055601a626a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055601a60b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055601a2bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055601a2bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80dde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80dde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80dde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055601a2baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (1819 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9414deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9414dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9414df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0058933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f005898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0058933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f005891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a941474bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a941474a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9414598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a941108e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a941108b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f005891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f005891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f005891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a941108a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (1820 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056551b853eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056551b850e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056551b85462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b34449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b344a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b34449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b34431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056551b7e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056551b7e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056551b7ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056551b47de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056551b47db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b34432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b344330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b344330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056551b47da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (1821 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 
# | ...
# `---data was truncated (10240/28683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f733567eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f733564e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f73356862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d58849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d588a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d58849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d58831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7334fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7334fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7334e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f733191e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f733191b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d58832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d588330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d588330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f733191a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (1822 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ba677eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ba677be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ba677f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45bcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45bcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45bcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45bcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ba6714bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ba6714a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ba66f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ba63a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ba63a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45bcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45bcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45bcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ba63a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (1823 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bc7b0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bc7b0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bc7b1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89f1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89f18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89f1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89f1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bc7aa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bc7aa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bc7a8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bc7739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bc7739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89f1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89f18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89f18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bc7739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (1824 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621f4571eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621f456ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621f457262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb45c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb45ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb45c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb45c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621f4507bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621f4507a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621f44ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621f419be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621f419bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb45c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb45c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb45c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621f419ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (1825 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fca93beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fca938e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fca93c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff8f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff8f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff8f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff8f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fca8d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fca8d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fca8b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fca565e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fca565b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff8f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff8f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff8f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fca565a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (1826 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056339bf05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056339bf02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056339bf0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bb7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bb758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bb7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bb751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056339be9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056339be9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056339be808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056339bb2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056339bb2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bb751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bb751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bb751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056339bb2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (1827 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573ad952eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573ad94fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573ad95362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f458e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f458e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f458e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f458e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573ad8e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573ad8e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573ad8cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573ad57ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573ad57cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f458e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f458e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f458e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573ad57ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (1828 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbccfd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbccfd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbccfd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e82d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e82d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e82d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e82d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbccf6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbccf6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbccf508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbccbffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbccbffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e82d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e82d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e82d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbccbffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (1829 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed76efeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed76efbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed76eff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5b2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5b2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5b2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5b2e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed76e94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed76e94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed76e798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed76b28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed76b28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5b2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5b2e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5b2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed76b28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (1830 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_and_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.and
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_or_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.or
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_xor_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.xor
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smax_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smin_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umax_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umin_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmax_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmin_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmaximum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.maximum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fminimum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.minimum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32_m8(<vscale x 16 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i32>, align 4
# |   store <vscale x 16 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 16 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @reduce_add_i64(<vscale x 1 x i64> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 1 x i64>, align 8
# |   store <vscale x 1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %a.addr, align 8
# |   %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %0)
# |   ret i64 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_mul_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.mul
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000562d62f28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d62f25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d62f2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff261449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2614a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff261449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff261431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d62ebebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d62ebea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d62ea38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d62b52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d62b52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff261432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2614330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2614330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d62b52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (1831 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/22298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d38819eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d38816e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d3881a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f304dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f304dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f304dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f304dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d387afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d387afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d387948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d38443e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d38443b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f304dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f304dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f304dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d38443a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (1832 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmset_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmset_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmset_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmset_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmset_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmset_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmset_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e2f53deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e2f53ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e2f53e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc46d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc46d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc46d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc46d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e2f4d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e2f4d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e2f4b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e2f167e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e2f167b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc46d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc46d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc46d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e2f167a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (1833 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f71d2e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f71d2e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f71d2e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3f7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3f738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3f7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3f731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f71d27dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f71d27da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f71d2628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f71cf11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f71cf11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3f731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3f731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3f731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f71cf11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (1834 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fb57e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fb57e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fb57e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0ac905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0ac95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0ac905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0ac8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fb577dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fb577da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fb57628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fb5411e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fb5411b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0ac8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0ac8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0ac8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fb5411a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (1835 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i)
# |   %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i)
# |   %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i)
# |   %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i)
# |   %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i)
# |   %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i)
# |   %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i)
# |   %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i)
# |   %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i)
# |   %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i)
# |   %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f64.i = bitcast <8 x i8> %1 
# | ...
# `---data was truncated (10240/18543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f6372cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6372cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6372ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fd0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fd0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fd0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fd0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f637263bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f637263a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6372488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f636ef7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f636ef7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fd0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fd0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fd0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f636ef7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (1836 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056431792aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564317927e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056431792b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc430d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc430d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc430d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc430d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643178c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643178c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643178a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564317554e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564317554b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc430d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc430d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc430d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564317554a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (1837 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8dca22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8dca1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8dca2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2472449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2472449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2472431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8dc9b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8dc9b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8dc99d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8dc64ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8dc64cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2472432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24724330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8dc64ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (1838 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ad4f7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ad4f79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ad4f7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5348a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5348aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5348a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5348a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ad4f12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ad4f12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ad4ef78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ad4ba6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ad4ba6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5348a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5348a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5348a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ad4ba6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (1839 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   
# | ...
# `---data was truncated (10240/13255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562499a0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562499a08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562499a0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71d1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71d1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71d1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71d1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624999a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624999a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624999868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562499635e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562499635b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71d1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71d1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71d1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562499635a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (1840 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d04ab23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d04ab20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d04ab2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f572581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57258725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f572581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5725803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d04aab9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d04aab9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d04aa9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d04a74de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d04a74db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5725804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57258050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57258050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d04a74da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (1841 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae7031aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae70317e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae7031b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54de133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54de18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54de133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54de11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae702b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae702b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae702958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae6ff44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae6ff44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54de11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54de11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54de11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae6ff44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (1842 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a60c41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a60c3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a60c4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feac8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feac8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feac8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feac8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a60bd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a60bd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a60bbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a6086be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a6086bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feac8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feac8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feac8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a6086ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (1843 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643351d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643351d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643351d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdde8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdde84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdde8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdde8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056433516dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056433516da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643351528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564334e01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564334e01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdde8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdde84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdde84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564334e01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (1844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be8397ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be83979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be8397d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2198333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f219838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2198333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f219831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be83912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be83912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be838f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be835a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be835a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f219831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f219831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f219831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be835a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (1845 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <8 x i8>, al
# | ...
# `---data was truncated (10240/26059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556381e21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556381e1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556381e2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc1f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc1f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc1f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc1f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556381db7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556381db7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556381d9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556381a4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556381a4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc1f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc1f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc1f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556381a4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (1846 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d4f256eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d4f253e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d4f25762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe47a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe47a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe47a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe47a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d4f1ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d4f1eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d4f1d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d4ee80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d4ee80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe47a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe47a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe47a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d4ee80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (1847 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615a290eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615a290be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615a290f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4944449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49444a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4944449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4944431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615a28a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615a28a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615a28898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615a2538e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615a2538b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4944432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49444330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49444330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615a2538a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (1848 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563119a60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563119a5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563119a6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6e0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6e00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6e0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6e0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631199f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631199f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631199db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056311968ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056311968ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6e0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6e00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6e00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056311968aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (1849 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590855f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590855f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590855f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9929733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f992978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9929733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f992971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559085589bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559085589a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055908556e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055908521de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055908521db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f992971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f992971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f992971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055908521da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (1850 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x 
# | ...
# `---data was truncated (10240/30682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e694a68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e694a65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e694a6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0072d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0072d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0072d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0072ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6949febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6949fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6949e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e694692e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e694692b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0072ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0072cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0072cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e694692a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (1851 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c6daa3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c6daa0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c6daa462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f352d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f352d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f352d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f352d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c6da39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c6da39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c6da1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c6d6cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c6d6cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f352d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f352d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f352d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c6d6cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (1852 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b320ed2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b320ecfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b320ed362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34b5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34b5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34b5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34b5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b320e68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b320e68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b320e4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b320afce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b320afcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34b5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34b5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34b5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b320afca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (1853 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617ab81feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617ab81ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617ab82062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff279f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff279f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff279f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff279f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617ab7b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617ab7b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617ab79a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617ab449e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617ab449b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff279f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff279f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff279f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617ab449a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (1854 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562919f40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562919f3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562919f4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa35a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa35a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa35a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa35a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562919ed6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562919ed6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562919ebb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562919b6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562919b6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa35a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa35a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa35a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562919b6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (1855 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625d3715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625d3712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625d371662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16a0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625d36abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625d36aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625d36908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625d333fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625d333fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16a08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625d333fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (1856 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643167b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643167b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643167b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cd7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cd718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cd7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cd711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056431674bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056431674ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643167308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643163dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643163dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cd711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cd711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cd711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643163dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (1857 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 
# | ...
# `---data was truncated (10240/66065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056101b43eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056101b43be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056101b43f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefa7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefa78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefa7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefa7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056101b3d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056101b3d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056101b3b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056101b068e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056101b068b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefa7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefa78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefa78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056101b068a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (1858 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee0a9e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee0a9e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee0a9e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06f7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06f7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06f7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06f7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee0a97bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee0a97ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee0a9608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee0a60fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee0a60fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06f7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06f7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06f7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee0a60fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (1859 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560657233eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560657230e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056065723462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7889849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78898a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7889849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7889831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606571c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606571c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606571ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560656e5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560656e5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7889832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78898330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78898330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560656e5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (1860 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bb6531eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bb652ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bb653262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c1db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c1db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c1db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c1db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bb64c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bb64c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bb64ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bb615be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bb615bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c1db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c1db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c1db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bb615ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-dot-product.c (1861 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 8
# |   %__s0_827 = alloca <4 x i32>, align 8
# |   %__s1_827 = alloca <16 x i8>, align 8
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x i32>, align 8
# |   %tmp2 = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0_827, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %1, ptr %__s1_827, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 8
# |   %4 = load <16 x i8>, ptr %__s1_827, align 8
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1,
# | ...
# `---data was truncated (10240/18322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055b3c2408eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3c2405e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3c240962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a19a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a19aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a19a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a19a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3c239ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3c239ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3c23838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3c2032e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3c2032b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a19a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a19a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a19a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3c2032a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (1862 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %
# | ...
# `---data was truncated (10240/11173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d8d4d6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8d4d68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8d4d6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe40a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe40a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe40a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe40a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8d4d01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8d4d01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8d4ce68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8d4995e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8d4995b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe40a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe40a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe40a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8d4995a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (1863 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ad63efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ad63ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ad63f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fceb7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fceb74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fceb7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fceb7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ad6385bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ad6385a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ad636a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ad6019e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ad6019b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fceb7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fceb74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fceb74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ad6019a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (1864 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a2bfb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a2bfb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a2bfb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50f7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50f76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50f7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50f7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a2bf4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a2bf4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a2bf338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a2bbe2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a2bbe2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50f7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50f76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50f76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a2bbe2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (1865 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e0167deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e0167ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e0167e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc14e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc14ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc14e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc14e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e01613bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e01613a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e015f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e012a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e012a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc14e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc14e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc14e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e012a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (1866 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aef438aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aef4387e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aef438b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff00081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0008725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff00081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff000803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aef4320bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aef4320a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aef43058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aef3fb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aef3fb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff000804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0008050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0008050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aef3fb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (1867 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x
# | ...
# `---data was truncated (10240/78032) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9b8915eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9b8912e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9b891662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24ef905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24ef95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24ef905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24ef8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9b88abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9b88aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9b88908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9b853fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9b853fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24ef8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24ef8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24ef8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9b853fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (1868 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/58326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbcb5caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbcb5c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbcb5cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f548e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f548e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f548e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f548e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbcb560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbcb560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbcb5458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbcb1f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbcb1f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f548e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f548e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f548e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbcb1f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (1869 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = and <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = and <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = and <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = and <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf0f092eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf0f08fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf0f09362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc95333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc9538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc95333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc9531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf0f028bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf0f028a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf0f00d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf0ecbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf0ecbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc9531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc9531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc9531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf0ecbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (1870 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055feb7bb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055feb7bade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055feb7bb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd338649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3386a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd338649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd338631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feb7b46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055feb7b46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055feb7b2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055feb77dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055feb77dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd338632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3386330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3386330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055feb77daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (1871 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv
# | ...
# `---data was truncated (10240/20082) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe27ef2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe27eefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe27ef362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4248c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4248ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4248c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4248c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe27e88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe27e88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe27e6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe27b1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe27b1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4248c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4248c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4248c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe27b1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (1872 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c497e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c497e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c497e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1967d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1967d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1967d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1967d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c4977abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c4977aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c4975f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c4940ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c4940eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1967d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1967d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1967d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c4940ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (1873 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557563059eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557563056e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055756305a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc205849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2058a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc205849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc205831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557562fefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557562fefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557562fd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557562c83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557562c83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc205832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2058330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2058330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557562c83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (1874 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 nou
# | ...
# `---data was truncated (10240/78890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7fe49deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7fe49ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7fe49e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97f5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97f538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97f5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97f531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7fe433bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7fe433a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7fe4188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7fe0c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7fe0c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97f531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97f531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97f531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7fe0c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (1875 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"Sma
# | ...
# `---data was truncated (10240/10293) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055687fcd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055687fcd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055687fcd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f666e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f666e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f666e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f666e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055687fc6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055687fc6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055687fc528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055687f901e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055687f901b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f666e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f666e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f666e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055687f901a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (1876 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560722149eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560722146e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056072214a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f688c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f688c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f688c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f688c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607220dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607220dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607220c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560721d73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560721d73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f688c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f688c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f688c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560721d73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (1877 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c29dcb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c29dcade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c29dcb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ed0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ed04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ed0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ed0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c29dc46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c29dc46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c29dc2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c29d8dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c29d8dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ed0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ed04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ed04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c29d8daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (1878 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559054d28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559054d25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559054d2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35e841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35e84725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35e841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35e8403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559054cbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559054cbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559054ca38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559054952e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559054952b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35e8404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35e84050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35e84050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559054952a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-shifts.c (1879 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -disable-O0-optnone    -target-cpu cortex-a8    -ffreestanding    -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"apcs-gnu"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559aadf7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559aadf7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559aadf7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b63a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b63a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b63a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b63a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559aadf14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559aadf14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559aadef98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559aadba8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559aadba8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b63a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b63a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b63a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559aadba8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (1880 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056407f539eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056407f536e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056407f53a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bff51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056407f4cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056407f4cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056407f4b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056407f163e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056407f163b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bff51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056407f163a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/builtins-riscv.c (1881 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 10, ptr %res, align 4
# |   store volatile i32 11, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055723b473eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055723b470e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055723b47462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5016733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f501678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5016733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f501671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055723b409bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055723b409a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055723b3ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055723b09de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055723b09db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f501671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f501671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f501671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055723b09da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (1882 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b608eb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b608eb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b608eba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb568e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb568e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb568e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb568e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b608e4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b608e4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b608e348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b608ae3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b608ae3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb568e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb568e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb568e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b608ae3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (1883 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv
# | ...
# `---data was truncated (10240/47720) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db37e60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db37e5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db37e6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f032ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f032caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f032ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f032ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db37df6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db37df6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db37ddb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db37a8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db37a8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f032ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f032ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f032ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db37a8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (1884 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b942a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b9429fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b942a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a5b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a5b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a5b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a5b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b94238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b94238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b9421d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b93ecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b93eccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a5b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a5b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a5b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b93ecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (1885 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556651d30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556651d2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556651d3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed48249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed482a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed48249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed48231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556651cc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556651cc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556651cab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055665195ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055665195ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed48232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed482330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed482330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055665195aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (1886 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 
# | ...
# `---data was truncated (10240/47772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2b909ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2b9099e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2b909d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21ac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21ac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21ac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21ac231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2b9032bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2b9032a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2b90178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2b8cc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2b8cc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21ac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21ac2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21ac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2b8cc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (1887 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627f699aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627f6997e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627f699b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe25e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe25e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe25e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe25e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627f6930bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627f6930a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627f69158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627f65c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627f65c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe25e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe25e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe25e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627f65c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (1888 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f580838eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f580835e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f58083962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff56c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff56c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff56c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff56c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5807cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5807cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5807b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f580462e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f580462b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff56c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff56c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff56c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f580462a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (1889 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/43515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c359e28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c359e25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c359e2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f928b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f928b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f928b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f928b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c359dbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c359dbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c359da38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c359a52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c359a52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f928b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f928b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f928b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c359a52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (1890 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d7e36eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d7e36be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d7e36f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0856333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f085638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0856333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f085631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d7e304bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d7e304a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d7e2e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d7df98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d7df98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f085631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f085631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f085631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d7df98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (1891 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b959ae6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b959ae3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b959ae762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b6781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b678725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b6781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b67803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b959a7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b959a7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b959a618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b959710e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b959710b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b67804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b678050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b678050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b959710a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (1892 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616de9feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616de9fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616de9ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73ce249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73ce2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73ce249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73ce231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616de994bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616de994a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616de9798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616de628e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616de628b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73ce232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73ce2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73ce2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616de628a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (1893 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1ff0e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1ff0dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1ff0e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc515449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5154a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc515449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc515431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1ff078bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1ff078a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1ff05d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1fed0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1fed0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc515432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5154330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5154330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1fed0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (1894 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ff640ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ff6409e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ff640d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4c9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4c9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4c9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4c9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ff63a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ff63a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ff63878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ff6036e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ff6036b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4c9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4c9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4c9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ff6036a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (1895 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc23c87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc23c84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc23c8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4830533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f483058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4830533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f483051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc23c1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc23c1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc23c028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc238b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc238b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f483051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f483051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f483051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc238b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (1896 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaefac2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaefabfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaefac362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5167933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f516798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5167933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f516791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaefa58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaefa58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaefa3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaef6ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaef6ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f516791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f516791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f516791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaef6eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (1897 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, pt
# | ...
# `---data was truncated (10240/79679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c17c376eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c17c373e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c17c37762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8110f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8110f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8110f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8110f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c17c30cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c17c30ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c17c2f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c17bfa0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c17bfa0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8110f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8110f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8110f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c17bfa0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (1898 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056280d6d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056280d6d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056280d6d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f191e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f191e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f191e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f191e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056280d66bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056280d66ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056280d6508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056280d2ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056280d2ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f191e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f191e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f191e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056280d2ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (1899 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1348a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1348a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1348a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f047b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f047b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f047b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f047b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f13483dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f13483da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1348228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1344d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1344d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f047b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f047b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f047b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1344d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (1900 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593537e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593537e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593537e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5242d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5242d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5242d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5242d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055935377cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055935377ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593537618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559353410e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559353410b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5242d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5242d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5242d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559353410a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (1901 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b49de0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b49de09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b49de0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f825eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f825eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f825eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f825eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b49dda2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b49dda2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b49dd878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b49da36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b49da36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f825eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f825eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f825eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b49da36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (1902 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555816cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555816c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555816cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe830333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe83038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe830333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe83031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555581661bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555581661a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555816468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555812f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555812f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe83031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe83031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe83031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555812f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (1903 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f08b0b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f08b0afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f08b0b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9b9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9b9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9b9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9b9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f08b048bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f08b048a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f08b02d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f08acdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f08acdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9b9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9b9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9b9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f08acdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (1904 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ecd682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ecd67fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ecd68362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd386a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd386aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd386a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd386a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ecd618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ecd618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ecd5fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ecd2ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ecd2acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd386a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd386a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd386a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ecd2aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (1905 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2057abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2057a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2057ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc21fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc21fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc21fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc21fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d205741bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d205741a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2057268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2053d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2053d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc21fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc21fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc21fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2053d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (1906 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e72361beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e723618e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e72361c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb838249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8382a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb838249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb838231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7235b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7235b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7235968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e723245e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e723245b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb838232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8382330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8382330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e723245a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (1907 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056242fd2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056242fd27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056242fd2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6321f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6321f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6321f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6321f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056242fcc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056242fcc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056242fca58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056242f954e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056242f954b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6321f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6321f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6321f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056242f954a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (1908 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558117f12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558117f0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558117f1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f636a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f636a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f636a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f636a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558117ea8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558117ea8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558117e8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558117b3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558117b3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f636a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f636a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f636a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558117b3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (1909 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559de3a41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559de3a3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559de3a4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedbce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedbcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedbce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedbce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559de39d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559de39d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559de39bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559de366be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559de366bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedbce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedbce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedbce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559de366ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (1910 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed192e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed192dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed192e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab09049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab090a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab09049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab09031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed19276bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed19276a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed1925b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed18f0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed18f0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab09032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab090330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab090330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed18f0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (1911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c971040eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c97103de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c97104162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f452241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45224725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f452241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4522403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c970fd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c970fd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c970fbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c970c6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c970c6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4522404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45224050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45224050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c970c6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (1912 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056210b1a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056210b19de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056210b1a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2bac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2baca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2bac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2bac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210b136bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056210b136a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056210b11b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056210adcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056210adcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2bac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2bac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2bac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056210adcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (1913 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b69a6bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b69a6bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b69a6be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7746e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7746ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7746e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7746e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b69a653bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b69a653a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b69a6388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b69a2e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b69a2e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7746e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7746e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7746e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b69a2e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (1914 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632c152eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632c152be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632c152f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b4de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b4dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b4de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b4de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632c14c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632c14c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632c14a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632c1158e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632c1158b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b4de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b4de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b4de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632c1158a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (1915 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ff0bd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ff0bd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ff0bd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a47f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a47f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a47f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a47f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ff0b6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ff0b6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ff0b508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ff07ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ff07ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a47f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a47f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a47f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ff07ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (1916 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @
# | ...
# `---data was truncated (10240/18570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f25d63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f25d60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f25d6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2c2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2c298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2c2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2c291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f25cf9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f25cf9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f25cde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f2598de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f2598db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2c291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2c291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2c291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f2598da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (1917 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %v
# | ...
# `---data was truncated (10240/86747) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4af330eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4af32de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4af33162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc032733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc03278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc032733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc03271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4af2c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4af2c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4af2ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4aef5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4aef5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc03271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc03271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc03271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4aef5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (1918 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = loa
# | ...
# `---data was truncated (10240/33443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdb6696eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdb6693e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdb669762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe052b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe052b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe052b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe052b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdb662cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdb662ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdb66118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdb62c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdb62c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe052b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe052b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe052b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdb62c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (1919 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589e2d12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589e2d0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589e2d1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f088e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f088e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f088e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f088e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589e2ca8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589e2ca8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589e2c8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589e293ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589e293cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f088e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f088e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f088e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589e293ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (1920 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x
# | ...
# `---data was truncated (10240/15375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a67d58ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a67d589e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a67d58d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf0b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf0b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf0b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf0b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a67d522bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a67d522a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a67d5078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a67d1b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a67d1b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf0b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf0b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf0b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a67d1b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (1921 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0)
# |   r
# | ...
# `---data was truncated (10240/43005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb5bdf4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb5bdf1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb5bdf562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3483449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3483449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3483431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb5bd8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb5bd8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb5bd6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb5ba1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb5ba1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3483432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34834330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb5ba1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (1922 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649e87cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649e87cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649e87d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa80db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa80db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa80db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa80db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649e8765bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649e8765a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649e874a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649e83f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649e83f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa80db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa80db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa80db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649e83f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (1923 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562675761eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056267575ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056267576262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37ff705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37ff75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37ff705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37ff6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626756f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626756f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626756dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056267538be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056267538bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37ff6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37ff6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37ff6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056267538ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (1924 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639e415eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639e415be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639e415f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7f6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7f6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7f6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7f6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639e40f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639e40f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639e40d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639e3d88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639e3d88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7f6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7f6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7f6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639e3d88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (1925 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x flo
# | ...
# `---data was truncated (10240/78024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7afceceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7afce9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7afced62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8124649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81246a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8124649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8124631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7afc82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7afc82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7afc678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7af916e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7af916b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8124632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81246330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81246330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7af916a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (1926 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557350a5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557350a5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557350a5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4edf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4edf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4edf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4edf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573509f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573509f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573509d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557350688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557350688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4edf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4edf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4edf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557350688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (1927 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/94157) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563194ad0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563194acde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563194ad162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2cd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2cd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2cd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2cd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563194a66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563194a66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563194a4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631946fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631946fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2cd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2cd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2cd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631946faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (1928 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b79a11ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b79a119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b79a11d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f443e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f443e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f443e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f443e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b79a0b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b79a0b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b79a0978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b799d46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b799d46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f443e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f443e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f443e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b799d46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (1929 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vsca
# | ...
# `---data was truncated (10240/11229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bce283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bce280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bce28462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd044133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd04418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd044133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd04411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bce219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bce219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bce1fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bcdeade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bcdeadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd04411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd04411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd04411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bcdeada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (1930 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cef87eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cef87be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cef87f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bb7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bb74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bb7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bb7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cef814bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cef814a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cef7f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cef4a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cef4a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bb7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bb74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bb74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cef4a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (1931 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056216fcbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056216fcbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056216fcbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0cb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0cb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0cb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0cb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056216fc53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056216fc53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056216fc388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056216f8e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056216f8e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0cb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0cb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0cb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056216f8e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (1932 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587ba600eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587ba5fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587ba60162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d81133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d8118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d81133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d8111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587ba596bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587ba596a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587ba57b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587ba22ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587ba22ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d8111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d8111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d8111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587ba22aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (1933 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.srshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nos
# | ...
# `---data was truncated (10240/11578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0e8dd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0e8dd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0e8dd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe276133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe27618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe276133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe27611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0e8d6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0e8d6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0e8d528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0e8a01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0e8a01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe27611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe27611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe27611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0e8a01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (1934 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2247fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2247f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2247fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12ac849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12ac8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12ac849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12ac831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a224791bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a224791a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2247768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a224425e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a224425b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12ac832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12ac8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12ac8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a224425a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (1935 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619aa9baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619aa9b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619aa9bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f17b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f17b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f17b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f17b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619aa950bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619aa950a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619aa9358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619aa5e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619aa5e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f17b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f17b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f17b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619aa5e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (1936 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a355aa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a355a9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a355aa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08e7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08e78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08e7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08e7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a355a37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a355a37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a355a1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3556cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3556cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08e7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08e78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08e78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3556cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (1937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f00d579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f00d576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f00d57a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aa9c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aa9c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aa9c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aa9c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f00d50fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f00d50fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f00d4f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f00d1a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f00d1a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aa9c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aa9c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aa9c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f00d1a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (1938 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/18925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564babaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564baba9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564babad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f752d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f752d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f752d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f752d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564bab42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564bab42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564bab278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564ba7d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564ba7d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f752d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f752d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f752d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564ba7d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (1939 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055872386beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558723868e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055872386c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f482fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f482fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f482fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f482fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558723801bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558723801a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587237e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558723495e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558723495b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f482fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f482fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f482fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558723495a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (1940 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/201234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d43b0f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d43b0f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d43b0f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff625f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff625f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff625f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff625f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d43b08ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d43b08ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d43b0738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d43ad22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d43ad22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff625f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff625f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff625f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d43ad22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (1941 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eecff13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eecff10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eecff1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec85049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec850a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec85049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec85031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eecfea9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eecfea9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eecfe8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eecfb3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eecfb3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec85032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec850330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec850330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eecfb3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (1942 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bc4a22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bc4a1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bc4a2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faddb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faddb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faddb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faddb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bc49b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bc49b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bc499d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bc464ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bc464cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faddb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faddb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faddb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bc464ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (1943 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a78fb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a78fb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a78fb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed41049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed410a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed41049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed41031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a78f4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a78f4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a78f338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a78be2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a78be2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed41032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed410330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed410330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a78be2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (1944 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/18303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6b203ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6b2039e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6b203d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2ae133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2ae18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2ae133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2ae11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6b1fd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6b1fd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6b1fb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6b1c66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6b1c66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2ae11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2ae11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2ae11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6b1c66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (1945 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635f8b89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635f8b86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635f8b8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c22733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c2278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c22733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c2271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635f8b1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635f8b1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635f8b048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635f87b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635f87b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c2271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c2271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c2271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635f87b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (1946 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5ab8d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5ab8cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5ab8d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e4ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e4ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e4ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e4ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5ab868bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5ab868a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5ab84d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5ab4fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5ab4fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e4ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e4ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e4ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5ab4fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (1947 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret bfloat %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x bfloat> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | !llvm.errno.tbaa = !{!6}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# | !6 = !{!7, !8, i64 0}
# | !7 = !{!"__libc_errno", !8, i64 0}
# | !8 = !{!"int", !9, i64 0}
# | !9 = !{!"omnipotent char", !10, i64 0}
# | !10 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c9c8891eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9c888ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9c889262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff215f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff215f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff215f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff215eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9c8827bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9c8827a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9c880c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9c84bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9c84bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff215eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff215eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff215eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9c84bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (1948 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloc
# | ...
# `---data was truncated (10240/71123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608cd428eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608cd425e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608cd42962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc083933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc08398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc083933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc08391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608cd3bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608cd3bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608cd3a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608cd052e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608cd052b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc08391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc08391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc08391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608cd052a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (1949 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/20131) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb3f65deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb3f65ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb3f65e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f925a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f925a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f925a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f925a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb3f5f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb3f5f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb3f5d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb3f287e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb3f287b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f925a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f925a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f925a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb3f287a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (1950 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6bbb20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6bbb1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6bbb2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe904d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe904d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe904d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe904d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6bbab6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6bbab6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6bba9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6bb74ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6bb74ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe904d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe904d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe904d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6bb74aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (1951 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea91070eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea9106de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea9107162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2201a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2201aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2201a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2201a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea91006bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea91006a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea90feb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea90c9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea90c9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2201a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2201a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2201a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea90c9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (1952 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620e08d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620e08d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620e08d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae8fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae8fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae8fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae8fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620e086cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620e086ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620e08518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620e0500e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620e0500b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae8fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae8fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae8fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620e0500a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (1953 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr 
# | ...
# `---data was truncated (10240/18895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b561dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b561d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b561dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff018333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff01838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff018333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff01831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b56171bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b56171a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b561568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b55e05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b55e05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff01831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff01831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff01831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b55e05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (1954 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofre
# | ...
# `---data was truncated (10240/183431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624b7662eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624b765fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624b766362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe605a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe605aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe605a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe605a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624b75f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624b75f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624b75dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624b728ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624b728cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe605a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe605a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe605a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624b728ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (1955 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a68e21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a68e1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a68e2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb0fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb0fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb0fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb0fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a68db7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a68db7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a68d9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a68a4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a68a4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb0fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb0fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb0fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a68a4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (1956 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale 
# | ...
# `---data was truncated (10240/30627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fa8796eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fa8793e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fa879762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6b5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6b5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6b5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6b5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fa872cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fa872ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fa87118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fa83c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fa83c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6b5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6b5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6b5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fa83c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (1957 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale 
# | ...
# `---data was truncated (10240/40937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555874113eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555874110e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055587411462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdee221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdee22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdee221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdee2203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558740a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558740a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055587408e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555873d3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555873d3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdee2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdee22050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdee22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555873d3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (1958 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 
# | ...
# `---data was truncated (10240/35980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000560696a57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560696a54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560696a5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2626049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26260a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2626049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2626031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606969edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606969eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606969d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560696681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560696681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2626032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26260330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26260330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560696681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (1959 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/124036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056243a1abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056243a1a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056243a1ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f33533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f3358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f33533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f3351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056243a141bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056243a141a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056243a1268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562439dd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562439dd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f3351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f3351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f3351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562439dd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (1960 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aaff44feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aaff44ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aaff45062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2257733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f225778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2257733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f225771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aaff3e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aaff3e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aaff3ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aaff079e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aaff079b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f225771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f225771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f225771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aaff079a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (1961 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055642f052eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055642f04fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055642f05362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8fe249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8fe2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8fe249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8fe231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055642efe8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055642efe8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055642efcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055642ec7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055642ec7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8fe232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8fe2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8fe2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055642ec7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (1962 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1
# | ...
# `---data was truncated (10240/19049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a0ad71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a0ad6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a0ad7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd1a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd1a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd1a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd1a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a0ad07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a0ad07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a0acec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a0a99be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a0a99bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd1a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd1a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd1a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a0a99ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (1963 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d99838aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d998387e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d99838b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8b9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8b9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8b9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8b9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d998320bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d998320a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9983058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d997fb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d997fb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8b9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8b9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8b9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d997fb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (1964 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b073727eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b073724e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b07372862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30cc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30cc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30cc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30cc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0736bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0736bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0736a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b073351e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b073351b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30cc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30cc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30cc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b073351a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (1965 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eec57aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eec57a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eec57ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ba7a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ba7a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ba7a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ba7a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eec5740bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eec5740a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eec57258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eec53d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eec53d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ba7a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ba7a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ba7a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eec53d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (1966 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, al
# | ...
# `---data was truncated (10240/28866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c39490eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c3948de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c3949162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42ac849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42ac8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42ac849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42ac831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c39426bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c39426a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c3940b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c390bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c390bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42ac832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42ac8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42ac8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c390baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (1967 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a45b324eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a45b321e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a45b32562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb818933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb81898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb818933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb81891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a45b2babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a45b2baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a45b29f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a45af4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a45af4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb81891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb81891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb81891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a45af4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (1968 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-unknown-linux-gnu"
# | 
# | @__riscv_cpu_model = external dso_local global { i32, i64, i64 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1808
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372035378380799
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 1152921505839391232
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775800
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 102892581
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775543
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 337970694
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f78ed29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f78ed26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f78ed2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c0e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c0e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c0e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c0e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f78ecbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f78ecbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f78eca48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f78e953e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f78e953b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c0e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c0e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c0e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f78e953a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (1969 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = loa
# | ...
# `---data was truncated (10240/23447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ca3377eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ca3374e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ca337862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c43e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c43ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c43e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c43e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ca330dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ca330da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ca32f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ca2fa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ca2fa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c43e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c43e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c43e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ca2fa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (1970 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629dc6a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629dc6a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629dc6a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9d7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9d7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9d7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9d7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629dc63cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629dc63ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629dc6218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629dc2d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629dc2d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9d7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9d7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9d7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629dc2d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (1971 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6d7e1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6d7e18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6d7e1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9a4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9a44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9a4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9a4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6d7db1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6d7db1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6d7d968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6d7a45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6d7a45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9a4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9a44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9a44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6d7a45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (1972 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f6f0f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f6f0f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f6f0f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f468e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f468e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f468e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f468e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f6f08bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f6f08ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f6f0708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f6ed1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f6ed1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f468e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f468e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f468e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f6ed1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (1973 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557820984eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557820981e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055782098562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea79a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea79a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea79a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea79a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055782091abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055782091aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578208ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578205aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578205aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea79a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea79a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea79a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578205aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (1974 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600de7d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600de7d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600de7d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e84d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e84d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e84d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e84d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600de76ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600de76ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600de7538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600de402e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600de402b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e84d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e84d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e84d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600de402a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (1975 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd0249ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd02499e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd0249d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf2b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf2b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf2b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf2b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd02432bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd02432a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd024178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd020c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd020c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf2b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf2b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf2b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd020c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (1976 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16
# | ...
# `---data was truncated (10240/15367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056329b161eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056329b15ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056329b16262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f465c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f465c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f465c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f465c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056329b0f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056329b0f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056329b0dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056329ad8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056329ad8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f465c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f465c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f465c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056329ad8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (1977 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/154207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d270f03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d270f00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d270f0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a54f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a54f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a54f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a54eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d270e99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d270e99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d270e7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d270b2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d270b2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a54eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a54eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a54eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d270b2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (1978 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/47706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3ac2cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3ac2cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3ac2d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f374e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f374e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f374e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f374e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3ac265bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3ac265a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3ac24a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3abef9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3abef9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f374e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f374e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f374e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3abef9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (1979 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559846a96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559846a93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559846a9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7934b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7934b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7934b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7934b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559846a2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559846a2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559846a118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598466c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598466c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7934b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7934b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7934b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598466c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (1980 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c51c18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c51c15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c51c1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff517333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff51738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff517333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff51731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c51baebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c51baea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c51b938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c51842e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c51842b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff51731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff51731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff51731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c51842a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (1981 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb1727feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb1727ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb1728062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe995905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe99595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe995905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9958ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb17215bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb17215a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb171fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb16ea9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb16ea9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9958eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9958ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9958ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb16ea9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (1982 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560b9f88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560b9f85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560b9f8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b6ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b6eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b6ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b6ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560b9f1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560b9f1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560b9f038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560b9bb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560b9bb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b6ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b6ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b6ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560b9bb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (1983 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055740b446eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055740b443e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055740b44762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6247849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62478a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6247849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6247831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055740b3dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055740b3dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055740b3c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055740b070e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055740b070b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6247832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62478330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62478330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055740b070a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (1984 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602a28a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602a28a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602a28aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70e2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70e2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70e2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70e2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602a283fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602a283fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602a28248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602a24d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602a24d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70e2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70e2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70e2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602a24d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (1985 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/41094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d477c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d477bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d477c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e82e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e82ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e82e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e82e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d47756bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d47756a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d4773b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d473eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d473eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e82e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e82e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e82e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d473eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (1986 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou
# | ...
# `---data was truncated (10240/28396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x0000562501e65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562501e62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562501e6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ba1305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ba135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ba1305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ba12ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562501dfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562501dfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562501de08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562501a8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562501a8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ba12eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ba12ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ba12ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562501a8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (1987 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561740361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056174035ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056174036262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fece1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fece115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fece1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fece10ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617402f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617402f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617402dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056173ff8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056173ff8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fece10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fece10ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fece10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056173ff8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (1988 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056168fb05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056168fb02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056168fb0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea12c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea12ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea12c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea12c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056168fa9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056168fa9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056168fa808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056168f72fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056168f72fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea12c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea12c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea12c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056168f72fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (1989 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, i64 %2, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_
# | ...
# `---data was truncated (10240/15323) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056309789eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056309789be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056309789f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4a3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4a338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4a3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4a331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563097834bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563097834a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630978198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630974c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630974c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4a331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4a331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4a331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630974c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (1990 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c47dcbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c47dcbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c47dcbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa298d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa298d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa298d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa298d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c47dc54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c47dc54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c47dc398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c47d8e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c47d8e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa298d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa298d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa298d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c47d8e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (1991 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab398c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab398c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab398c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafa4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafa4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafa4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafa4e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab3985bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab3985ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab398408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab394efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab394efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafa4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafa4e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafa4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab394efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (1992 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x 
# | ...
# `---data was truncated (10240/26696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d43737eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d43734e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d4373862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ea8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ea8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ea8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ea8e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d436cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d436cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d436b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d43361e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d43361b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ea8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ea8e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ea8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d43361a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (1993 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557de0ccceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557de0cc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557de0ccd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557de0c62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557de0c62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557de0c478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557de08f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557de08f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facc3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557de08f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (1994 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056436d56eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056436d56be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056436d56f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3234933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f323498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3234933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f323491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056436d504bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056436d504a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056436d4e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056436d198e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056436d198b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f323491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f323491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f323491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056436d198a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (1995 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d826b9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d826b98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d826b9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb86249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb862a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb86249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb86231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d826b31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d826b31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d826b168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8267c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8267c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb86232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb862330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb862330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8267c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm64-crc32.c (1996 of 27910)
******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32x(i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd50b65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd50b62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd50b6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c6f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c6f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c6f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c6f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd50afbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd50afba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd50ae08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd5078fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd5078fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c6f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c6f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c6f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd5078fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (1997 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.add
# | ...
# `---data was truncated (10240/14453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558359848eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558359845e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055835984962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc781333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc78138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc781333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc78131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583597debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583597dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583597c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558359472e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558359472b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc78131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc78131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc78131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558359472a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (1998 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654c2cfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654c2cf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654c2cfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f9cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f9cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f9cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f9cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654c2c92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654c2c92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654c2c778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654c2926e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654c2926b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f9cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f9cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f9cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654c2926a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (1999 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a4b877eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a4b874e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a4b87862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a58733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a5878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a58733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a5871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a4b80dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a4b80da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a4b7f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a4b4a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a4b4a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a5871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a5871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a5871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a4b4a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (2000 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b9163beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b91638e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b9163c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1807849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18078a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1807849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1807831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b915d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b915d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b915b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b91265e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b91265b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1807832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18078330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18078330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b91265a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (2001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eca888beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eca8888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eca888c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f567f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f567f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f567f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f567f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eca8821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eca8821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eca88068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eca84b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eca84b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f567f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f567f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f567f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eca84b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (2002 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/79671) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056471e297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056471e294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056471e29862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98a4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98a478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98a4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98a471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056471e22dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056471e22da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056471e2128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056471dec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056471dec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98a471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98a471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98a471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056471dec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2003 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/12431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648cb62feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648cb62ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648cb63062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9742449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9742449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9742431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648cb5c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648cb5c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648cb5aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648cb259e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648cb259b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9742432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97424330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648cb259a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (2004 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563787948eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563787945e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056378794962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b45b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b45b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b45b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b45b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637878debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637878dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637878c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563787572e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563787572b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b45b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b45b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b45b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563787572a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (2005 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c941a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c941a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c941a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19d341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19d34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19d341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19d3403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c9413bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c9413ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c941208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c93dcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c93dcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19d3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19d34050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19d34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c93dcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (2006 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbca5e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbca5dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbca5e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbddc01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbddc0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbddc01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbddc003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbca576bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbca576a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbca55b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbca20ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbca20ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbddc004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbddc0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbddc0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbca20aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (2007 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b86f0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b86f07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b86f0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f556f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f556f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f556f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f556f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b86ea0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b86ea0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b86e858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b86b34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b86b34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f556f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f556f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f556f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b86b34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (2008 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ff3845eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ff3842e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ff384662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa475905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa47595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa475905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4758ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ff37dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ff37dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ff37c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ff346fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ff346fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4758eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4758ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4758ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ff346fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (2009 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653bdf74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653bdf71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653bdf7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dcd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dcd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dcd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dcd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653bdf0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653bdf0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653bdeef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653bdb9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653bdb9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9dcd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dcd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dcd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653bdb9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (2010 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmclr_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmclr_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmclr_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmclr_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmclr_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmclr_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmclr_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056483db54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056483db51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056483db5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e21733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e2178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e21733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e2171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056483daeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056483daeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056483dacf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056483d77ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056483d77eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e2171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e2171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e2171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056483d77ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (2011 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2_m(<vscale x 2 x i1> %mask,
# | ...
# `---data was truncated (10240/13544) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbdad7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbdad79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbdad7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e18a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e18a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e18a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e18a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbdad12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbdad12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbdacf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbda9a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbda9a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e18a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e18a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e18a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbda9a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (2012 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556eaefaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556eaefa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556eaefab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f085f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f085f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f085f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f085f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556eaef40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556eaef40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556eaef258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556eaebd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556eaebd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f085f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f085f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f085f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eaebd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (2013 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555692cd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555692ccfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555692cd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb140933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb14098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb140933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb14091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555692c68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555692c68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555692c4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556928fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556928fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb14091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb14091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb14091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556928fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (2014 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ce8885eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ce8882e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ce888662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5107649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51076a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5107649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5107631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ce881bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ce881ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ce88008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ce84afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ce84afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5107632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51076330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51076330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ce84afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (2015 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609df14eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609df14be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609df14f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f926b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f926b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f926b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f926b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609df0e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609df0e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609df0c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609ded78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609ded78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f926b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f926b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f926b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609ded78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (2016 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfacc55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfacc52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfacc5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f328f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f328f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f328f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f328f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfacbebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfacbeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfacbd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfac87fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfac87fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f328f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f328f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f328f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfac87fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (2017 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db91b3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db91b3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db91b3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9abbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9abbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9abbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9abbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db91ad4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db91ad4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db91ab98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db91768e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db91768b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9abbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9abbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9abbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db91768a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (2018 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d7a41aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d7a417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d7a41b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaf5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaf52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaf5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaf5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d7a3b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d7a3b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d7a3958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d7a044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d7a044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaf5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaf52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaf52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d7a044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (2019 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 
# | ...
# `---data was truncated (10240/14824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f84262eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f8425fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f8426362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d84d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d84d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d84d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d84d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f841f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f841f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f841dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f83e8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f83e8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d84d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d84d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d84d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f83e8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (2020 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> 
# | ...
# `---data was truncated (10240/12298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a501aa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a501aa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a501aa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f189461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18946725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f189461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1894603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a501a3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a501a3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a501a218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5016d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5016d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1894604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18946050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18946050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5016d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (2021 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec453deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec453dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec453df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde32e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde32ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde32e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde32e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec45374bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec45374a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec453598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec45008e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec45008b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde32e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde32e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde32e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec45008a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (2022 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   store <vscale x 4 x i32> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %1, 1
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, <vscale x 4 x i32> %2, 2
# |   %7 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, <vscale x 4 x i32> %3, 3
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate4_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2, <vscale x 2 x i64> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   %x4.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   store <vscale x 2 x i64> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %1, 1
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, <vscale x 2 x i64> %2, 2
# |   %7 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, <vscale x 2 x i64> %3, 3
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vs
# | ...
# `---data was truncated (10240/21212) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005636f7868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636f7865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636f786962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5064c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5064c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5064c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5064c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636f77febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636f77fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636f77e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636f7492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636f7492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5064c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5064c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5064c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636f7492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (2023 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b04881aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b048817e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b04881b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56d8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56d858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56d8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56d851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0487b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0487b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0487958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b048444e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b048444b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56d851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56d851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56d851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b048444a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (2024 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad52c52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad52c4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad52c5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef40533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef4058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef40533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef4051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad52be8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad52be8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad52bcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad5287ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad5287cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef4051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef4051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef4051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad5287ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (2025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, 
# | ...
# `---data was truncated (10240/20307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d47156eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d47153e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d4715762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7975733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f797578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7975733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f797571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d470ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d470eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d470d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d46d80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d46d80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f797571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f797571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f797571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d46d80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (2026 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586f0f5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586f0f57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586f0f5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff66381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6638725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff66381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff663803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586f0ef0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586f0ef0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586f0ed58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586f0b84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586f0b84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff663804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6638050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6638050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586f0b84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (2027 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560e84caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560e84c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560e84cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa4261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa426725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa4261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa42603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560e8460bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560e8460a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560e84458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560e80f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560e80f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa42604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa426050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa426050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560e80f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (2028 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649c45c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649c45c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649c45ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d4881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d488725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d4881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d48803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649c455fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649c455fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649c45448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649c41f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649c41f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d48804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d488050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d488050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649c41f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (2029 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca67744eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca67741e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca6774562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faad6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faad698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faad6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faad691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca676dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca676daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca676bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca6736ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca6736eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faad691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faad691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faad691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca6736ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (2030 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = ca
# | ...
# `---data was truncated (10240/67474) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b362398eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b362395e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b36239962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42c0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42c00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42c0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42c0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b36232ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b36232ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3623138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b361fc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b361fc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42c0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42c00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42c00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b361fc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (2031 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a75baadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a75baaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a75baae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadfed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadfed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadfed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadfeced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a75ba43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a75ba43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a75ba288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a75b6d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a75b6d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadfeceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadfecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadfecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a75b6d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (2032 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c  -check-prefix=RV32ZBC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afe6637eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afe6634e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afe663862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f690ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f690baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f690ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f690ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afe65cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afe65cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afe65b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afe6261e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afe6261b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f690ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f690ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f690ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afe6261a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (2033 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e328514eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e328511e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e32851562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb19e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb19ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb19e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb19e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3284aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3284aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e32848f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e32813ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e32813eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb19e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb19e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb19e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e32813ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (2034 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bea9e92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bea9e8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bea9e9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f020be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f020be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f020be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f020be03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bea9e28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bea9e28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bea9e0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bea9abce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bea9abcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f020be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f020be050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f020be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bea9abca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2035 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd75550eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd7554de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd7555162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e4a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e4a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e4a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e4a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd754e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd754e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd754cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd7517ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd7517ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e4a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e4a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e4a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd7517aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (2036 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6b4599eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6b4596e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6b459a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7156b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7156b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7156b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7156b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6b452fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6b452fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6b45148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6b41c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6b41c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7156b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7156b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7156b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6b41c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (2037 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e480a8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e480a87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e480a8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa5d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa5d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa5d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa5d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e480a20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e480a20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e480a058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4806b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4806b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa5d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa5d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa5d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4806b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (2038 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %
# | ...
# `---data was truncated (10240/291999) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a244f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a244f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a244f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10dd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10dd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10dd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10dd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a2448abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a2448aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a2446f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a2411ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a2411eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10dd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10dd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10dd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a2411ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (2039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1c59c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1c59bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1c59c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9d7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9d7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9d7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9d7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1c5957bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1c5957a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1c593c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1c55ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1c55ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9d7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9d7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9d7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1c55eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (2040 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e000a39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e000a36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e000a3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca0c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca0c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca0c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca0c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0009cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0009cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0009b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e000663e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e000663b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca0c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca0c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca0c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e000663a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (2041 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617dbfc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617dbfc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617dbfc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0358f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0358f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0358f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0358f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617dbf5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617dbf5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617dbf408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617dbbefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617dbbefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0358f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0358f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0358f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617dbbefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (2042 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6ac536eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6ac533e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6ac53762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a96a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a96aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a96a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a96a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6ac4ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6ac4cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6ac4b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6ac160e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6ac160b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a96a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a96a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a96a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6ac160a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (2043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccea981eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccea97ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccea98262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f677b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f677b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f677b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f677b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccea917bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccea917a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccea8fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccea5abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccea5abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f677b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f677b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f677b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccea5aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (2044 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b8db12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b8db0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b8db1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4315533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f431558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4315533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f431551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b8daa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b8daa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b8da8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b8d73ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b8d73cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f431551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f431551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f431551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b8d73ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (2045 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565527024eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565527021e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056552702562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c2a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c2a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c2a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c2a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565526fbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565526fbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565526f9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565526c4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565526c4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c2a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c2a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c2a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565526c4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (2046 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstrid
# | ...
# `---data was truncated (10240/28111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f28367eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f28364e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f2836862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb59f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb59f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb59f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb59f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f282fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f282fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f282e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f27f91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f27f91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb59f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb59f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb59f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f27f91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (2047 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560e9f9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560e9f99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560e9f9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d11d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d11d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d11d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d11d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560e9f32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560e9f32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560e9f178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560e9bc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560e9bc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d11d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d11d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d11d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560e9bc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (2048 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"SmallDataLi
# | ...
# `---data was truncated (10240/10285) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd98760eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd9875de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd9876162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f303a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f303a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f303a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f303a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd986f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd986f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd986db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd9838ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd9838ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f303a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f303a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f303a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd9838aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (2049 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556abe995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556abe992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556abe99662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e55a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e55aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e55a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e55a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556abe92bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556abe92ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556abe9108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556abe5bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556abe5bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e55a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e55a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e55a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556abe5bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (2050 of 27910)
******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc |     not grep _foo2
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @bar() #0 {
# | entry:
# |   call void @foo2()
# |   ret void
# | }
# | 
# | declare void @foo2() #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# |  #0 0x000055b17760aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b177607e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b17760b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde30333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde3038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde30333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde3031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1775a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1775a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1775858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b177234e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b177234b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde3031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde3031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde3031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b177234a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: llc
# executed command: not grep _foo2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (2051 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557563a52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557563a4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557563a5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d41733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d4178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d41733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d4171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575639e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575639e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575639cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055756367ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055756367cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d4171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d4171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d4171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055756367ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (2052 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/14338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f8a78deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f8a78ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f8a78e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff032849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0328a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff032849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff032831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f8a723bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f8a723a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f8a7088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f8a3b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f8a3b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff032832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0328330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0328330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f8a3b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (2053 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat>
# | ...
# `---data was truncated (10240/53686) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8133a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8133a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8133a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc377649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3776a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc377649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc377631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b81333ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b81333ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8133238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b812fd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b812fd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc377632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3776330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3776330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b812fd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (2054 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/79071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2681a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2681a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2681a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a44e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a44ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a44e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a44e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d26813abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d26813aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d26811f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d267dcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d267dceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a44e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a44e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a44e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d267dcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (2055 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056387e423eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056387e420e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056387e42462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facee133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facee18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facee133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facee11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056387e3b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056387e3b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056387e39e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056387e04de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056387e04db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facee11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facee11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facee11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056387e04da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (2056 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569b2acfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569b2acce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569b2ad062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcab231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569b2a65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569b2a65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569b2a4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569b26f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569b26f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcab2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569b26f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (2057 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i
# | ...
# `---data was truncated (10240/14788) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563437588eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563437585e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056343758962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1918c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1918ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1918c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1918c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056343751ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056343751ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634375038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634371b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634371b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1918c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1918c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1918c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634371b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (2058 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | de
# | ...
# `---data was truncated (10240/12091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613da4cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613da4c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613da4cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdd9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdd935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdd9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdd92ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613da462bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613da462a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613da4478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613da0f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613da0f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdd92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdd92ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdd92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613da0f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (2059 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a0fd32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a0fd2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a0fd3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f006a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f006a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f006a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f006a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a0fcc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a0fcc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a0fcad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a0f95ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a0f95cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f006a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f006a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f006a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a0f95ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (2060 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, a
# | ...
# `---data was truncated (10240/29450) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecb30e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecb30dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecb30e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5f0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5f04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5f0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5f0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecb3078bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecb3078a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecb305d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecb2d0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecb2d0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5f0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5f04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5f04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecb2d0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (2061 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a86712feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a86712ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a86713062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef15849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef158a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef15849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef15831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8670c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8670c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8670aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a866d59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a866d59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef15832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef158330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef158330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a866d59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (2062 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4808e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4808e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4808e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9ba049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9ba0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9ba049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9ba031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b480879bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b480879a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b48085e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b48050de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b48050db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9ba032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9ba0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9ba0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b48050da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (2063 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be0ff7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be0ff78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be0ff7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1caef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1caef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1caef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1caef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be0ff11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be0ff11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be0fef68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be0fba5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be0fba5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1caef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1caef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1caef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be0fba5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (2064 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653285a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653285a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653285a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4fc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056532853abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056532853aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056532851f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653281cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653281ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4fc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653281cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2065 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561064349eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561064346e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056106434a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc70b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc70b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc70b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc70b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610642dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610642dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610642c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561063f73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561063f73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc70b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc70b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc70b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561063f73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (2066 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587061efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587061ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587061f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7387b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7387b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7387b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7387b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558706185bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558706185a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055870616a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558705e19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558705e19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7387b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7387b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7387b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558705e19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (2067 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.v
# | ...
# `---data was truncated (10240/58683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c8eedceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c8eed9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c8eedd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1891d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1891d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1891d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1891d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c8ee72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c8ee72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c8ee578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c8eb06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c8eb06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1891d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1891d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1891d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c8eb06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (2068 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b42ac9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b42ac9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b42aca062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f276ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f276ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f276ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f276ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b42ac35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b42ac35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b42ac1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b42a8c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b42a8c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f276ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f276ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f276ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b42a8c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (2069 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1d9471eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1d946ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1d947262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd43e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd43e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd43e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd43e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1d9407bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1d9407a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1d93ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1d909be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1d909bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd43e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd43e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd43e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1d909ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (2070 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/30690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055980341ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559803419e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055980341d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9868449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98684a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9868449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9868431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598033b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598033b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598033978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559803046e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559803046b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9868432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98684330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98684330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559803046a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (2071 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567fa4bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567fa4bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567fa4be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa94b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa94b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa94b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa94b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567fa453bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567fa453a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567fa4388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567fa0e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567fa0e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa94b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa94b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa94b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567fa0e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (2072 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bc2c2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bc2c27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bc2c2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f281df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f281df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f281df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f281deed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bc2bc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bc2bc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bc2ba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bc2854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bc2854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f281deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f281deef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f281deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bc2854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (2073 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644cfba4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644cfba1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644cfba562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fa9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fa90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fa9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fa9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644cfb3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644cfb3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644cfb1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644cf7cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644cf7ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fa9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fa90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fa90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644cf7cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (2074 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be10f68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be10f65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be10f6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd36f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd36f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd36f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd36f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be10efebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be10efea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be10ee38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be10b92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be10b92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd36f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd36f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd36f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be10b92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (2075 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564493454eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564493451e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056449345562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effdd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effdd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effdd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effdd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644933eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644933eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644933cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056449307ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056449307eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effdd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effdd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effdd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056449307ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (2076 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 
# | ...
# `---data was truncated (10240/10944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557275dbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557275db8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557275dbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93c2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93c2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93c2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93c2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557275d51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557275d51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557275d368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572759e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572759e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93c2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93c2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93c2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572759e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (2077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1f862ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1f8629e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1f862d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcf2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcf2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcf2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcf2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1f85c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1f85c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1f85a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1f8256e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1f8256b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcf2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcf2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcf2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1f8256a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (2078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3657f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3657f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3657fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ebfd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ebfd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ebfd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ebfced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c36578fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c36578fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3657748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c365423e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c365423b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ebfceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ebfcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ebfcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c365423a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (2079 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cb55beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cb55bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cb55bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04b3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04b3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04b3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04b3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cb5554bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cb5554a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cb55398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cb51e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cb51e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04b3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04b3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04b3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cb51e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (2080 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650ee710eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650ee70de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650ee71162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f508c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f508c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f508c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f508c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650ee6a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650ee6a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650ee68b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650ee33ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650ee33ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f508c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f508c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f508c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650ee33aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (2081 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590c70e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590c70e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590c70e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54c7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54c758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54c7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54c751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590c7079bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590c7079a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590c705e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590c6d0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590c6d0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54c751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54c751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54c751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590c6d0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (2082 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb31044eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb31041e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb3104562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccb301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccb30725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccb301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccb3003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb30fdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb30fdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb30fbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb30c6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb30c6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccb3004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccb30050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccb30050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb30c6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (2083 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x
# | ...
# `---data was truncated (10240/29267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba423b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba423b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba423ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b94e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b94ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b94e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b94e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba4234fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba4234fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba423348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba41fe3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba41fe3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b94e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b94e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b94e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba41fe3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (2084 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e5f55eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e5f55be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e5f55f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20ee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20ee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20ee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20ee71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e5f4f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e5f4f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e5f4d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e5f188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e5f188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20ee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20ee71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20ee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e5f188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (2085 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %x.addr, align 8
# |   %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>
# |   ret <8 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   %p.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   store <8 x i8> %p, ptr %p.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %p.addr, align 8
# |   %mask = and <8 x i8> %1, splat (i8 7)
# |   %shuf_idx = extractelement <8 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <8 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <8 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <8 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <8 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <8 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <8 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <8 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   ret <8 x i8> %shuf_ins21
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %x.addr, align 16
# |   %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
# |   ret <16 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %p.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store <16 x i8> %p, ptr %p.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %p.addr, align 16
# |   %mask = and <16 x i8> %1, splat (i8 15)
# |   %shuf_idx = extractelement <16 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <16 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <16 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <16 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <16 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <16 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <16 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <16 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   %shuf_idx22 = extractelement <16 x i8> %mask, i64 8
# |   %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22
# |   %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8
# |   %shuf_idx25 = extractelement <16 x i8> %mask, i64 9
# |   %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25
# |   %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9
# |   %shuf_idx28 = extractelement <16 x i8> %mask, i64 10
# |   %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28
# |   %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10
# |   %shuf_idx31 = extractelement <16 x i8> %mask, i64 11
# |   %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31
# |   %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11
# |   %shuf_idx34 = extractelement <16 x i8> %mask, i64 12
# |   %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34
# |   %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12
# |   %shuf_idx37 = extractelement <16 x i8> %mask, i64 13
# |   %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37
# |   %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13
# |   %shuf_idx40 = extractelement <16 x i8> %mask, i64 14
# |   %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40
# |   %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14
# |   %shuf_idx43 = extractelement <16 x i8> %mask, i64 15
# |   %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43
# |   %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15
# |   ret <16 x i8> %shuf_ins45
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d0ec4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d0ec4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d0ec5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c2f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c2f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c2f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c2f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d0ebe5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d0ebe5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d0ebca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d0e879e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d0e879b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c2f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c2f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c2f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d0e879a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (2086 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640af477eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640af474e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640af47862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15e2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15e2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15e2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15e2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640af40dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640af40da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640af3f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640af0a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640af0a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15e2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15e2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15e2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640af0a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (2087 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x half>
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x float>
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 {
# | entry:
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 {
# | entry:
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055a9240c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9240c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9240c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31cdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31cdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31cdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31cdc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a92405ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a92405ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9240438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a923cf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a923cf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31cdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31cdc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31cdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a923cf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (2088 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f55c2f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f55c2f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f55c2fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2143a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2143aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2143a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2143a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f55c28fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f55c28fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f55c2748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f55bf23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f55bf23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2143a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2143a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2143a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f55bf23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (2089 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586b00f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586b00f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586b00f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efea9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efea9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efea9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efea9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586b0089bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586b0089a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586b006e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586afd1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586afd1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efea9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efea9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efea9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586afd1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (2090 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643a5be7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643a5be4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643a5be862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fa6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fa678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fa6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fa671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643a5b7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643a5b7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643a5b628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643a5811e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643a5811b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fa671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fa671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fa671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643a5811a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (2091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dc419feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dc419ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dc41a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5352333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f535238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5352333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f535231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dc4135bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dc4135a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dc411a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557dc3dc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557dc3dc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f535231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f535231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f535231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dc3dc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (2092 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609a34efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609a34ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609a34f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f012d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f012d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f012d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f012d2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609a3485bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609a3485a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609a346a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609a3119e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609a3119b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f012d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f012d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f012d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609a3119a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (2093 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind 
# | ...
# `---data was truncated (10240/77062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3db3b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3db3ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3db3b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbdbf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbdbf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbdbf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbdbeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3db346bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3db346a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3db32b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3dafdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3dafdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbdbeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbdbeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbdbeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3dafdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (2094 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e6241deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e6241ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e6241e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc6a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc6a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc6a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc6a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e623b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e623b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e623988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e62047e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e62047b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc6a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc6a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc6a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e62047a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (2095 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f15db7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f15db7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f15db8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc51b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc51b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc51b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc51b0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f15db15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f15db15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f15dafa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f15d7a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f15d7a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc51b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc51b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc51b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f15d7a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (2096 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f3473ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f34739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f3473d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc14133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc1418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc14133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc1411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f346d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f346d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f346b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f34366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f34366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc1411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc1411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc1411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f34366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (2097 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e08bd6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e08bd6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e08bd7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb677f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb677f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb677f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb677f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e08bd05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e08bd05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e08bcea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e08b999e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e08b999b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb677f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb677f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb677f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e08b999a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (2098 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557aa5e4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557aa5e48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557aa5e4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32bb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32bb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32bb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32bb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557aa5de1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557aa5de1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557aa5dc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557aa5a75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557aa5a75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32bb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32bb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32bb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557aa5a75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (2099 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577c4de3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577c4de0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577c4de462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f253b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f253b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f253b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f253b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577c4d79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577c4d79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577c4d5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577c4a0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577c4a0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f253b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f253b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f253b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577c4a0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (2100 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dfaa2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dfaa27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dfaa2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e6ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e6ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e6ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e6ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dfa9c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dfa9c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dfa9a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dfa654e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dfa654b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e6ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e6ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e6ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dfa654a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (2101 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/12688) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576966efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576966ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576966f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcfda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcfdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcfda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcfda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557696685bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557696685a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055769666a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557696319e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557696319b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcfda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcfda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcfda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557696319a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (2102 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a555fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a555fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a555fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa5a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa5a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa5a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa5a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a55593bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a55593a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a555788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a55227e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a55227b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa5a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa5a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa5a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a55227a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (2103 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a937968eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a937965e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a93796962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8195933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f819598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8195933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f819591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9378febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9378fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9378e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a937592e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a937592b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f819591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f819591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f819591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a937592a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (2104 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbe8844eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbe8841e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbe884562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb28b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb28b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb28b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb28b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbe87dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbe87daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbe87bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbe846ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbe846eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb28b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb28b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb28b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbe846ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (2105 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/150649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f7a292eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f7a28fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f7a29362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54a831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f7a228bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f7a228a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f7a20d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f79ebce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f79ebcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54a831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f79ebca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (2106 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630d1a2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630d1a29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630d1a2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc6c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc6c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc6c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc6c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630d19c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630d19c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630d19a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630d1656e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630d1656b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc6c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc6c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc6c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630d1656a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (2107 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vr
# | ...
# `---data was truncated (10240/96265) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056383fa40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056383fa3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056383fa4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe21b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe21b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe21b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe21b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056383f9d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056383f9d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056383f9bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056383f66ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056383f66ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe21b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe21b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe21b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056383f66aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (2108 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaadd_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562983cd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562983cd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562983cd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f183bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f183bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f183bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f183bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562983c6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562983c6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562983c4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629838fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629838feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f183bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f183bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f183bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629838fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (2109 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d47776eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d47773e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d4777762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cf8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cf8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cf8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cf8eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d4770cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d4770ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d476f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d473a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d473a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cf8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cf8eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cf8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d473a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (2110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f48dbb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f48dbaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f48dbb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21df049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21df0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21df049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21df031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f48db47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f48db47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f48db2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f48d7dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f48d7dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21df032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21df0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21df0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f48d7dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (2111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2d6a2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2d6a2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2d6a2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0a9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0a9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0a9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0a9eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2d69c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2d69c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2d69a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2d6658e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2d6658b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0a9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0a9eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0a9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2d6658a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (2112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1856dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1856d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1856dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabb2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabb2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabb2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabb2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e185672bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e185672a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1856578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e185306e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e185306b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabb2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabb2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabb2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e185306a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (2113 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae0eb12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae0eb0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae0eb1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7d8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7d898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7d8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7d891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae0eaa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae0eaa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae0ea8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae0e73ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae0e73cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7d891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7d891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7d891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae0e73ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (2114 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   s
# | ...
# `---data was truncated (10240/280209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c440801eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4407fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c44080262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa784a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa784aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa784a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa784a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c440797bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c440797a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c44077c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c44042be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c44042bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa784a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa784a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa784a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c44042ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (2115 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9bec35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9bec32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9bec3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca9bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca9bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca9bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca9bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9bebcbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9bebcba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9bebb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9be85fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9be85fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca9bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca9bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca9bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9be85fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (2116 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e7ef1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e7ef17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e7ef1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5747049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57470a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5747049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5747031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e7eeb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e7eeb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e7ee958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e7eb44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e7eb44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5747032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57470330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57470330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e7eb44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (2117 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vect
# | ...
# `---data was truncated (10240/24229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580b3da4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580b3da1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580b3da562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1705a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1705a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1705a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1705a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580b3d3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580b3d3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580b3d1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580b39cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580b39ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1705a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1705a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1705a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580b39cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (2118 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b40f92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b40f8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b40f9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cda533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cda58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cda533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cda51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b40f28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b40f28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b40f0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b40bbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b40bbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9cda51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cda51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cda51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b40bbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (2119 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644f0e29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644f0e26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644f0e2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0fca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0fcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0fca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0fca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644f0dbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644f0dbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644f0da48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644f0a53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644f0a53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0fca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0fca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0fca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644f0a53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (2120 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622bc34eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622bc34be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622bc34f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3eeae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3eeaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3eeae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3eeae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622bc2e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622bc2e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622bc2c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622bbf78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622bbf78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3eeae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3eeae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3eeae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622bbf78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (2121 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f3a273eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f3a270e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f3a27462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f501f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f501f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f501f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f501f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f3a209bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f3a209a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f3a1ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f39e9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f39e9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f501f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f501f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f501f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f39e9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (2122 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652fdc72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652fdc6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652fdc7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06a2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06a2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06a2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06a2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652fdc08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652fdc08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652fdbed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652fd89ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652fd89cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06a2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06a2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06a2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652fd89ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (2123 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610c1c5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610c1c59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610c1c5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44b4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44b44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44b4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44b4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610c1bf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610c1bf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610c1bd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610c1886e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610c1886b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44b4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44b44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44b44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610c1886a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (2124 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrga
# | ...
# `---data was truncated (10240/28435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ff2582eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ff257fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ff258362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3584b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3584b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3584b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3584b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ff2518bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ff2518a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ff24fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ff21ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ff21acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3584b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3584b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3584b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ff21aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (2125 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9a738ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9a7389e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9a738d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c7a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c7a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c7a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c7a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9a7322bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9a7322a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9a73078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9a6fb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9a6fb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c7a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c7a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c7a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9a6fb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (2126 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608045beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608045bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608045bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdd4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdd4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdd4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdd4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560804554bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560804554a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608045398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608041e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608041e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdd4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdd4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdd4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608041e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (2127 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee810d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee810d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee810d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd62733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd6278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd62733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd6271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee8106abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee8106aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee8104f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee80cfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee80cfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd6271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd6271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd6271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee80cfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (2128 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056056488feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056056488ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056056489062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f634b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f634b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f634b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f634b2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560564825bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560564825a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056056480a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605644b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605644b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f634b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f634b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f634b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605644b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (2129 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a358bf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a358bf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a358bf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f707fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f707fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f707fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f707fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a358b8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a358b8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a358b728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a358821e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a358821b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f707fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f707fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f707fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a358821a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (2130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563aa89b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563aa89b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563aa89ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cbd41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cbd4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cbd41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cbd403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563aa894fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563aa894fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563aa89348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563aa85e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563aa85e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cbd404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cbd4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cbd4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563aa85e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (2131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f27c8cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f27c8cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f27c8ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1595249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15952a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1595249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1595231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f27c863bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f27c863a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f27c8488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f27c4f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f27c4f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1595232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15952330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15952330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f27c4f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (2132 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b89e88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b89e85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b89e8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72c7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72c758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72c7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72c751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b89e1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b89e1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b89e038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b89ab2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b89ab2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72c751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72c751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72c751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b89ab2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (2133 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = mul <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = mul <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = mul <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fmul <4 x float> %0, %1
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.m
# | ...
# `---data was truncated (10240/21288) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005576ad3c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576ad3bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576ad3c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76c4505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76c455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76c4505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76c44ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576ad356bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576ad356a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576ad33b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576acfeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576acfeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76c44eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76c44ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76c44ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576acfeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (2134 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db153c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db153c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db153c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb053d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb053d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb053d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb053d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db1535cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db1535ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db153418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db14ff0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db14ff0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb053d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb053d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb053d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db14ff0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (2135 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559960dddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559960ddae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559960dde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15ced05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15ced5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15ced05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15ceced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559960d73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559960d73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559960d588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559960a07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559960a07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15ceceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15cecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15cecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559960a07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (2136 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557498f7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557498f78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557498f7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2f0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2f08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2f0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2f0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557498f11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557498f11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557498ef68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557498ba5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557498ba5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2f0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2f08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2f08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557498ba5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (2137 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558920435eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558920432e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055892043662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9c6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9c60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9c6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9c6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589203cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589203cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589203b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055892005fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055892005fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9c6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9c60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9c60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055892005fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (2138 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare 
# | ...
# `---data was truncated (10240/20139) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce200bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce200b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce200bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafb5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafb538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafb5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafb531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce20051bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce20051a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce200368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce1fce5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce1fce5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafb531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafb531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafb531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce1fce5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (2139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be2c71eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be2c71be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be2c71f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c28505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c2855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c28505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c284ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be2c6b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be2c6b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be2c6998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be2c348e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be2c348b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c284eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c284ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c284ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be2c348a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (2140 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1c2a53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1c2a50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1c2a5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f180e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f180e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f180e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f180e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1c29e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1c29e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1c29ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1c267de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1c267db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f180e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f180e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f180e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1c267da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (2141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582261e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582261e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582261ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21d5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21d5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21d5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21d5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055822617fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055822617fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582261648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558225e13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558225e13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21d5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21d5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21d5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558225e13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (2142 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e7d110eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e7d10de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e7d11162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb0f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb0f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb0f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb0f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e7d0a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e7d0a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e7d08b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e7cd3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e7cd3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb0f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb0f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb0f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e7cd3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (2143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b25d20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b25d1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b25d2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fe5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fe58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fe5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fe5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b25cb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b25cb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b25c9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b2594ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b2594ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fe5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fe58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fe58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b2594aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (2144 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555624e27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555624e24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555624e2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16d6f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16d6f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16d6f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16d6eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555624dbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555624dbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555624da28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555624a51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555624a51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16d6eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16d6eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16d6eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555624a51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (2145 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612b7b86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612b7b83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612b7b8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe346649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe346649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe346631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612b7b1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612b7b1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612b7b018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612b77b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612b77b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe346632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3466330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612b77b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2146 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/12439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d542f8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d542f87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d542f8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1deb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1deb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1deb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1deb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d542f20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d542f20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d542f058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d542bb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d542bb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1deb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1deb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1deb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d542bb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (2147 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/110284) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607d6301eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607d62fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607d630262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a94849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a948a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a94849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a94831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607d6297bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607d6297a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607d627c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607d5f2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607d5f2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a94832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a948330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a948330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607d5f2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (2148 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9956b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9956b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9956b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3ae533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3ae58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3ae533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3ae51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b99564bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b99564ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9956308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9952dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9952dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3ae51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3ae51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3ae51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9952dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (2149 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559560567eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559560564e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055956056862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8ad249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8ad2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8ad249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8ad231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595604fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595604fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595604e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559560191e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559560191b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8ad232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8ad2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8ad2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559560191a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (2150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align
# | ...
# `---data was truncated (10240/39416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d97c32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d97c2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d97c3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f497b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f497b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f497b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f497b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d97bc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d97bc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d97bad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d9785ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d9785cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f497b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f497b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f497b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d9785ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (2151 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e455895eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e455892e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e45589662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d4bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d4bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d4bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d4bced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e45582bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e45582ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4558108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4554bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4554bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d4bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d4bcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d4bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4554bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (2152 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, al
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055abd5041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055abd503ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055abd504262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4319249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43192a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4319249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4319231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abd4fd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055abd4fd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055abd4fbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055abd4c6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055abd4c6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4319232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43192330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43192330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abd4c6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (2153 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be4d3cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be4d3c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be4d3cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44df21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44df2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44df21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44df203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be4d362bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be4d362a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be4d3478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be4cff6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be4cff6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44df204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44df2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44df2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be4cff6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (2154 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c770924eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c770921e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c77092562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f304eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f304eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f304eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f304eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7708babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7708baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c77089f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c77054ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c77054eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f304eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f304eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f304eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c77054ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (2155 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564dd7179eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564dd7176e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564dd717a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66da933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66da98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66da933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66da91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564dd710fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564dd710fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564dd70f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564dd6da3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564dd6da3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66da91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66da91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66da91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564dd6da3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (2156 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfca2b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfca2b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfca2b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd71933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd7198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd71933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd7191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfca249bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfca249a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfca22e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfc9edde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfc9eddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd7191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd7191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd7191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfc9edda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (2157 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9584bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9584bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9584c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b09849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b098a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b09849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b09831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e958455bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e958455a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e95843a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9580e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9580e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b09832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b098330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b098330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9580e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (2158 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581b38daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581b38d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581b38db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92bb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92bb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92bb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92bb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581b3870bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581b3870a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581b38558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581b3504e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581b3504b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92bb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92bb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92bb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581b3504a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: Modules/pr93497.cppm (2159 of 27910)
******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 3
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm      -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp      -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm      -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.Thing = type { i32 }
# | %struct.C = type { i32 }
# | %struct.NonConstexprDtor = type { i32 }
# | 
# | $needed = comdat any
# | 
# | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4
# | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4
# | @_ZW3mod11ConstantPtr = external global ptr, align 8
# | @_ZW3mod16NonConstantValue = external global %struct.C, align 4
# | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4
# | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }]
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z3usev() #0 {
# | entry:
# |   %t1 = alloca %struct.Thing, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | declare noundef i32 @_Z7consumei(i32 noundef) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use2v() #0 {
# | entry:
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %0 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0)
# |   ret i32 %call
# | }
# | 
# | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use3v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ptr = alloca ptr, align 8
# |   %agg.tmp = alloca %struct.C, align 4
# |   %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8
# |   store ptr %0, ptr %Ptr, align 8
# |   %1 = load ptr, ptr %Ptr, align 8
# |   %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0
# |   %2 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %2, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %3 = load ptr, ptr %Ptr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %4 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr i32 @needed() #0 comdat {
# | entry:
# |   %call = call noundef i32 @_Z7consumei(i32 noundef 43)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use4v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ref = alloca %struct.C, align 4
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false)
# |   %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0
# |   %0 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %1 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use5v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %V = alloca %struct.NonConstexprDtor, align 4
# |   %cleanup.dest.slot = alloca i32, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %1 = load i32, ptr %raw1, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %1)
# |   store i32 %call, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | if.end:                                           ; preds = %entry
# |   %call2 = call i32 @needed()
# |   store i32 %call2, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %if.end, %if.then
# |   call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3
# | 
# | declare void @_ZGIW3mod()
# | 
# | ; Function Attrs: noinline nounwind
# | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" {
# | entry:
# |   call void @_ZGIW3mod()
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #5 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# |  #0 0x000055c127331eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c12732ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c12733262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb6a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb6a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb6a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb6a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1272c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1272c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1272ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c126f5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c126f5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb6a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb6a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb6a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c126f5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (2160 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625eea40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625eea3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625eea4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa611b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa611b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa611b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa611b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625ee9d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625ee9d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625ee9bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625ee66ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625ee66ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa611b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa611b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa611b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625ee66aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (2161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ac8ea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ac8e9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ac8ea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24e8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24e838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24e8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24e831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ac8e37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ac8e37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ac8e1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ac8acbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ac8acbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24e831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24e831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24e831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ac8acba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (2162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dad1b3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dad1b37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dad1b3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3b8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3b878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3b8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3b871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dad1ad0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dad1ad0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dad1ab58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dad1764e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dad1764b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3b871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3b871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3b871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dad1764a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (2163 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd11d78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd11d75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd11d7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77eeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd11d0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd11d0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd11cf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd119a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd119a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd119a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (2164 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a85aaa8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a85aaa5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a85aaa962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfe4305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfe435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfe4305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfe42ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a85aa3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a85aa3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a85aa238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a85a6d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a85a6d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfe42eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfe42ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfe42ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a85a6d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (2165 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055caeb01beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055caeb018e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055caeb01c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f449b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f449b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f449b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f449b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caeafb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055caeafb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055caeaf968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055caeac45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055caeac45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f449b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f449b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f449b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055caeac45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (2166 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16
# | ...
# `---data was truncated (10240/62095) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e17cabdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e17cabae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e17cabe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9b3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9b3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9b3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9b3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e17ca53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e17ca53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e17ca388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e17c6e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e17c6e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9b3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9b3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9b3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e17c6e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (2167 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac85dcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac85dc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac85dcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06cbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06cbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06cbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06cbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac85d60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac85d60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac85d458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac859f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac859f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06cbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06cbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06cbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac859f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (2168 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c8674aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c86747e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c8674b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35d7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35d778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35d7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35d771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c866e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c866e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c866c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c86374e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c86374b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35d771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35d771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35d771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c86374a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (2169 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633f4905eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633f4902e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633f490662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22f0c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22f0c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22f0c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22f0c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633f489bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633f489ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633f48808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633f452fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633f452fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22f0c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22f0c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22f0c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633f452fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (2170 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b32a076eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b32a073e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b32a07762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda38d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda38d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda38d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda38d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b32a00cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b32a00ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b329ff18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b329ca0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b329ca0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda38d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda38d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda38d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b329ca0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (2171 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd84faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfd84f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfd84fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad49333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad4938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad49333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad4931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd8490bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfd8490a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfd84758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfd8124e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfd8124b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad4931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad4931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad4931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd8124a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-crc32.c (2172 of 27910)
******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586aba99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586aba96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586aba9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff16f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff16f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff16f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff16f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586aba2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586aba2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586aba148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586ab6c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586ab6c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff16f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff16f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff16f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586ab6c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (2173 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# | ...
# `---data was truncated (10240/30866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd95545eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd95542e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd9554662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6832733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f683278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6832733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f683271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd954dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd954dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd954c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd9516fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd9516fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f683271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f683271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f683271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd9516fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (2174 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654a87d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654a87cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654a87d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39de849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39de8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39de849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39de831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654a8768bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654a8768a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654a874d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654a83fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654a83fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39de832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39de8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39de8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654a83fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (2175 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574cbee8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574cbee5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574cbee962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5be2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5be295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5be2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5be28ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574cbe7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574cbe7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574cbe638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574cbb12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574cbb12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5be28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5be28ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5be28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574cbb12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (2176 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale 
# | ...
# `---data was truncated (10240/56179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056307bae0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056307badde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056307bae162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59ada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59adaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59ada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59ada31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056307ba76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056307ba76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056307ba5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056307b70ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056307b70ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59ada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59ada330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59ada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056307b70aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (2177 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563421b9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563421b97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563421b9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ed9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ed9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ed9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ed9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563421b30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563421b30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563421b158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634217c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634217c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ed9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ed9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ed9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634217c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (2178 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ba4b2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ba4b2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ba4b2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7435649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74356a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7435649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7435631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ba4ac3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ba4ac3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ba4aa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ba4757e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ba4757b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7435632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74356330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74356330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ba4757a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (2179 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e365040eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e36503de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e36504162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f297de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f297dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f297de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f297de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e364fd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e364fd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e364fbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e364c6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e364c6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f297de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f297de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f297de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e364c6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (2180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565165baeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565165babe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565165baf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe556933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe55698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe556933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe55691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565165b44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565165b44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565165b298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651657d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651657d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe55691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe55691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe55691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651657d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (2181 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @l
# | ...
# `---data was truncated (10240/62760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a80925eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a80922e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a8092662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28fd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28fd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28fd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28fd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a808bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a808bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a808a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a8054fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a8054fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28fd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28fd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28fd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a8054fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (2182 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3fa27aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3fa277e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3fa27b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feca3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feca378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feca3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feca371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3fa210bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3fa210a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3fa1f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3f9ea4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3f9ea4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feca371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feca371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feca371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3f9ea4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (2183 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.v
# | ...
# `---data was truncated (10240/53192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a388658eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a388655e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a38865962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29b8a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29b8a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29b8a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29b8a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3885eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3885eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3885d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a388282e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a388282b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29b8a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29b8a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29b8a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a388282a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (2184 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055803deeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055803dee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055803deeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6228049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62280a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6228049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6228031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055803de80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055803de80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055803de658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055803db14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055803db14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6228032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62280330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62280330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055803db14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (2185 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631abb58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631abb55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631abb5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc734649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7346a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc734649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc734631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631abaeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631abaeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631abad38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631ab782e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631ab782b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc734632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7346330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7346330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631ab782a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (2186 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr %0, i64 %2)
# |   %4 =
# | ...
# `---data was truncated (10240/33471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640deb26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640deb23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640deb2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdeb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdeb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdeb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdeb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640deabcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640deabca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640deaa18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640de750e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640de750b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdeb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdeb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdeb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640de750a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (2187 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e132b59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e132b56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e132b5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8475c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8475ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8475c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8475c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e132aefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e132aefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e132ad48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e132783e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e132783b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8475c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8475c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8475c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e132783a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (2188 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055904bdaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055904bda9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055904bdad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55e821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55e82725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55e821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55e8203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055904bd42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055904bd42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055904bd278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055904b9d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055904b9d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55e8204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55e82050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55e82050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055904b9d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (2189 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056526608deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056526608ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056526608e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac44a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac44a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac44a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac44a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565266023bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565266023a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652660088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565265cb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565265cb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac44a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac44a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac44a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565265cb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (2190 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16
# | ...
# `---data was truncated (10240/84971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621976aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621976a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621976ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb118649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1186a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb118649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb118631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562197642bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562197642a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621976278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621972d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621972d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb118632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1186330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1186330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621972d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (2191 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f266931eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f26692ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f26693262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadba849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadba8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadba849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadba831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2668c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2668c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2668ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f26655be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f26655bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadba832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadba8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadba8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f26655ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (2192 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i
# | ...
# `---data was truncated (10240/51303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abf2df0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055abf2dede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055abf2df162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3612333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f361238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3612333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f361231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abf2d86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055abf2d86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055abf2d6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055abf2a1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055abf2a1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f361231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f361231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f361231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abf2a1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (2193 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc248b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc248afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc248b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f447e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f447e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f447e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f447e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc24848bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc24848a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc2482d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc244dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc244dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f447e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f447e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f447e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc244dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (2194 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618bbc2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618bbc27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618bbc2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b59505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b5955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b59505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b594ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618bbbc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618bbbc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618bbba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618bb854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618bb854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b594eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b594ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b594ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618bb854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (2195 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576c3e1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576c3e1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576c3e1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cc3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cc378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cc3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cc371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576c3db4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576c3db4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576c3d998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576c3a48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576c3a48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cc371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cc371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cc371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576c3a48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (2196 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056375037ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563750379e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056375037d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32dc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32dc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32dc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32dc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563750312bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563750312a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637502f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056374ffa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056374ffa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32dc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32dc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32dc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056374ffa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (2197 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i8 @subscript_int8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i8 @subscript_uint8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i16 @subscript_int16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i16 @subscript_uint16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_int32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_uint32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 2 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 1 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double> %a.coerce, i64 0)
# |   store <4 x double> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x double>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b9d1bfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9d1bfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9d1bfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b5b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b5b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b5b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b5b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9d1b93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9d1b93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9d1b788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9d1827e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9d1827b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b5b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b5b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b5b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9d1827a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (2198 of 27910)
******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# |  #0 0x00005571477b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571477b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571477b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c21b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c21b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c21b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c21b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055714774cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055714774ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571477318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571473e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571473e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c21b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c21b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c21b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571473e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (2199 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 
# | ...
# `---data was truncated (10240/39226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b43e5bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b43e5b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b43e5bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e19533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e1958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e19533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e1951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b43e551bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b43e551a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b43e5368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b43e1e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b43e1e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e1951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e1951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e1951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b43e1e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (2200 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3b914eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3b914be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3b914f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8633f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8633f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8633f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8633f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3b90e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3b90e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3b90c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3b8d78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3b8d78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8633f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8633f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8633f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3b8d78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (2201 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16093eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c16093be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c16093f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d7ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d7ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d7ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d7ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1608d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1608d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1608b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c160568e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c160568b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d7ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d7ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d7ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c160568a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (2202 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d76c6bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d76c6b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d76c6bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe27dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe27dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe27dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe27dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d76c651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d76c651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d76c6368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d76c2e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d76c2e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe27dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe27dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe27dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d76c2e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (2203 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr,
# | ...
# `---data was truncated (10240/30874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056421fdd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056421fdd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056421fdd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36c0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36c08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36c0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36c0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056421fd6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056421fd6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056421fd538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056421fa02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056421fa02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36c0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36c08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36c08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056421fa02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (2204 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8
# | ...
# `---data was truncated (10240/60809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2a4d30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2a4d2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2a4d3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe838133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe83818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe838133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe83811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2a4cc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2a4cc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2a4cab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2a495ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2a495ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe83811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe83811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe83811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2a495aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (2205 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561891cf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561891cf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561891cf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a31c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a31ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a31c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a31c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561891c8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561891c8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561891c728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561891921e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561891921b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a31c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a31c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a31c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561891921a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (2206 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563739e14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563739e11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563739e1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98fba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98fbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98fba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98fba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563739daabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563739daaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563739d8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563739a3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563739a3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98fba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98fba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98fba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563739a3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (2207 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdadc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bdadc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bdadc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e12c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e12ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e12c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e12c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdad5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bdad5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bdad3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bda9eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bda9eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e12c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e12c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e12c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bda9eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (2208 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i
# | ...
# `---data was truncated (10240/215478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a9592feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a9592ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a9593062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbdc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbdc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbdc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbdc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a958c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a958c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a958aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a95559e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a95559b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbdc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbdc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbdc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a95559a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (2209 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6fd3cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6fd3c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6fd3cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a42933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a4298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a42933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a4291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6fd361bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6fd361a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6fd3468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6fcff5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6fcff5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a4291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a4291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a4291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6fcff5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (2210 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/148020) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f191ca0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f191c9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f191ca162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75bee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75beea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75bee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75bee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f191c36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f191c36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f191c1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1918cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1918cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75bee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75bee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75bee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1918caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (2211 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e35453eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e35450e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e3545462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72f5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72f56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72f5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72f5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e353e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e353e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e353ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e3507de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e3507db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72f5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72f56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72f56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e3507da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (2212 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563401601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634015fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056340160262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ead733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ead78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ead733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ead71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563401597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563401597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056340157c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056340122be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056340122bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ead71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ead71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ead71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056340122ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (2213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608304e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608304e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608304ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0c4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0c44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0c4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0c4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056083047fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056083047fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608304648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560830113e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560830113b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0c4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0c44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0c44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560830113a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (2214 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/32701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567ef1ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567ef1cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567ef1cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97f981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97f98725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97f981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97f9803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567ef164bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567ef164a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567ef1498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567eedf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567eedf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97f9804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97f98050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97f98050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567eedf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (2215 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale
# | ...
# `---data was truncated (10240/12129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de0c4dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de0c4d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de0c4dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf62733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf6278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf62733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf6271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de0c471bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de0c471a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de0c4568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de0c105e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de0c105b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf6271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf6271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf6271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de0c105a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (2216 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650727d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650727cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650727d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2613905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f261395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2613905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26138ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565072766bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565072766a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056507274b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650723fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650723fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26138eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26138ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26138ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650723faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (2217 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607b5188eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607b5185e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607b518962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f4f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f4f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f4f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f4f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607b511ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607b511ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607b51038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607b4db2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607b4db2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f4f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f4f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f4f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607b4db2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (2218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055952cd5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055952cd5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055952cd5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3beef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3beef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3beef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3beef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055952ccf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055952ccf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055952ccd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055952c988e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055952c988b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3beef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3beef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3beef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055952c988a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (2219 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636f463beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636f4638e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636f463c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636f45d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636f45d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636f45b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636f4265e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636f4265b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facc431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636f4265a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (2220 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055941ad09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055941ad06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055941ad0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5020733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f502078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5020733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f502071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055941ac9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055941ac9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055941ac848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055941a933e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055941a933b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f502071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f502071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f502071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055941a933a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (2221 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b080082eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b08007fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b08008362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efff9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efff958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efff9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efff951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b080018bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b080018a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b07fffd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b07fcace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b07fcacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efff951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efff951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efff951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b07fcaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (2222 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbc0307eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbc0304e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbc030862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0982d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0982d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0982d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0982d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbc029dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbc029da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbc02828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbbff31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbbff31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0982d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0982d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0982d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbbff31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (2223 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e35226eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e35223e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e3522762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4d5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4d5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4d5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4d5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e351bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e351bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e351a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e34e50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e34e50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4d5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4d5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4d5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e34e50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (2224 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd0f2a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd0f2a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd0f2a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6934c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6934c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6934c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6934c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd0f23bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd0f23ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd0f2208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd0eecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd0eecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6934c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6934c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6934c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd0eecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (2225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da05933eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da05930e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da0593462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53ca533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53ca58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53ca533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53ca51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da058c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da058c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da058ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da0555de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da0555db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53ca51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53ca51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53ca51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da0555da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (2226 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/101483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055665893deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055665893ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055665893e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd51a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd51aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd51a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd51a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566588d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566588d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566588b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556658567e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556658567b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd51a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd51a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd51a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556658567a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (2227 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc112f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc112f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc112f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d9be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d9bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d9be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d9be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc1128dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc1128da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc112728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc10f21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc10f21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d9be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d9be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d9be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc10f21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (2228 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   
# | ...
# `---data was truncated (10240/135119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559342734eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559342731e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055934273562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6138505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f613855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6138505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61384ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593426cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593426caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593426af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055934235ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055934235eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61384eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61384ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61384ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055934235ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (2229 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611fdae0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611fdadde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611fdae162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9f1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9f198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9f1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9f191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611fda76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611fda76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611fda5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611fd70ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611fd70ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9f191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9f191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9f191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611fd70aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (2230 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f20a80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f20a7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f20a8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f20a16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f20a16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f209fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f206aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f206aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87c211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f206aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm_acle.c (2231 of 27910)
******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dmb() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dsb() #0 {
# | entry:
# |   call void @llvm.arm.dsb(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_isb() #0 {
# | entry:
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pld() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pldx() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pli() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_plix() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 32
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %4, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i32, ptr %__x.addr.i, align 4
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %shr.i = lshr i32 %5, %6
# |   %7 = load i32, ptr %__x.addr.i, align 4
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 32, %8
# |   %shl.i = shl i32 %7, %sub.i
# |   %or.i = or i32 %shr.i, %shl.i
# |   store i32 %or.i, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | __ror.exit:                                       ; preds = %if.then.i, %if.end.i
# |   %9 = load i32, ptr %retval.i, align 4
# |   ret i32 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i.i = alloca i32, align 4
# |   %__x.addr.i.i = alloca i32, align 4
# |   %__y.addr.i.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   store i32 %2, ptr %__x.addr.i.i, align 4
# |   store i32 %3, ptr %__y.addr.i.i, align 4
# |   %4 = load i32, ptr %__y.addr.i.i, align 4
# |   %rem.i.i = urem i32 %4, 32
# |   store i32 %rem.i.i, ptr %__y.addr.i.i, align 4
# |   %5 = load i32, ptr %__y.addr.i.i, align 4
# |   %cmp.i.i = icmp eq i32 %5, 0
# |   br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i
# | 
# | if.then.i.i:                                      ; preds = %entry
# |   %6 = load i32, ptr %__x.addr.i.i, align 4
# |   store i32 %6, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | if.end.i.i:                                       ; preds = %entry
# |   %7 = load i32, ptr %__x.addr.i.i, align 4
# |   %8 = load i32, ptr %__y.addr.i.i, align 4
# |   %shr.i.i = lshr i32 %7, %8
# |   %9 = load i32, ptr %__x.addr.i.i, align 4
# |   %10 = load i32, ptr %__y.addr.i.i, align 4
# |   %sub.i.i = sub i32 32, %10
# |   %shl.i.i = shl i32 %9, %sub.i.i
# |   %or.i.i = or i32 %shr.i.i, %shl.i.i
# |   store i32 %or.i.i, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | __rorl.exit:                                      ; preds = %if.then.i.i, %if.end.i.i
# |   %11 = load i32, ptr %retval.i.i, align 4
# |   ret i32 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i64, align 8
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i64, align 8
# |   %y.addr = alloca i32, align 4
# |   store i64 %x, ptr %x.addr, align 8
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i64, ptr %x.addr, align 8
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 64
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i64, ptr %__x.addr.i, align 8
# |   store i64 %4, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i64, ptr %__x.addr.i, align 8
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %sh_prom.i = zext i32 %6 to i64
# |   %shr.i = lshr i64 %5, %sh_prom.i
# |   %7 = load i64, ptr %__x.addr.i, align 8
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 64, %8
# |   %sh_prom1.i = zext i32 %sub.i to i64
# |   %shl.i = shl i64 %7, %sh_prom1.i
# |   %or.i = or i64 %shr.i, %shl.i
# |   store i64 %or.i, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | __rorll.exit:                                     ; preds = %if.then.i, %if.end.i
# |   %9 = load i64, ptr %retval.i, align 8
# |   ret i64 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clz(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzl(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzll(i64 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i64, align 8
# |   %t.addr = alloca i64, align 8
# |   store i64 %t, ptr %t.addr, align 8
# |   %0 = load i64, ptr %t.addr, align 8
# |   store i64 %0, ptr %__t.addr.i, align 8
# |   %1 = load i64, ptr %__t.addr.i, align 8
# |   %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false)
# |   %3 = trunc i64 %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %cls.i = call i32 @llvm.arm.cls(i32 %1)
# |   ret i32 %cls.i
# | }
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/86891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f456afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f456ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f456b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbb3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbb378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbb3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbb371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f45645bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f45645a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f4562a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f452d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f452d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbb371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbb371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbb371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f452d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (2232 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588ff8f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588ff8f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588ff8f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea39d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea39d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea39d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea39d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588ff88bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588ff88ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588ff8708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588ff51fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588ff51fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea39d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea39d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea39d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588ff51fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (2233 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4094e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4094e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4094e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fb9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fb92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fb9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fb9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a40947dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a40947da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4094628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a409111e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a409111b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fb9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fb92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fb92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a409111a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (2234 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bf
# | ...
# `---data was truncated (10240/13040) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556420903eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556420900e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055642090462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2efdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2efdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2efdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2efdc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556420899bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556420899a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055642087e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055642052de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055642052db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2efdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2efdc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2efdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055642052da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (2235 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c49838beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c498388e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c49838c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faea4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faea48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faea4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faea4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c498321bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c498321a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4983068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c497fb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c497fb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faea4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faea48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faea48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c497fb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (2236 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed3aabceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed3aab9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed3aabd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0964f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0964f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0964f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0964f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed3aa52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed3aa52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed3aa378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed3a6e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed3a6e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0964f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0964f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0964f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed3a6e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (2237 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2f3358eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2f3355e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2f335962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8845449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88454a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8845449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8845431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2f32eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2f32eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2f32d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2f2f82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2f2f82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8845432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88454330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88454330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2f2f82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (2238 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f082a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f082a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f082aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f700e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f700e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f700e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f700e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f0823fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f0823fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f082248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f07ed3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f07ed3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f700e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f700e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f700e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f07ed3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (2239 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d1ecfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d1ecfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d1ecfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a60d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a60d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a60d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a60d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d1ec93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d1ec93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d1ec788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d1e927e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d1e927b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a60d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a60d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a60d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d1e927a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (2240 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3)
# |   %5 = and <8 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3)
# |   %5 = and <4 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3)
# |   %5 = and <2 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3)
# |   %5 = and <16 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = xor i16 %0, -1
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = load <8 x half>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = load <4 x float>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <2 x i64>, ptr %a.addr, align 8
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   %5 = load <2 x i64>, ptr %b.addr, align 8
# |   %6 = bitcast <2 x i64> %5 to <4 x i32>
# |   %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6
# |   %8 = bitcast <4 x i32> %7 to <2 x i64>
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, ali
# | ...
# `---data was truncated (10240/13928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055678bf14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055678bf11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055678bf1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c9681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c968725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c9681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c96803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055678beaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055678beaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055678be8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055678bb3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055678bb3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c96804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c968050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c968050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055678bb3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (2241 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbd3c5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbd3c57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbd3c5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2344e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2344ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2344e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2344e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbd3bf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbd3bf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbd3bd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbd3884e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbd3884b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2344e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2344e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2344e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbd3884a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (2242 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558de798ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558de7989e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558de798d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3cb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3cb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3cb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3cb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558de7922bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558de7922a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558de79078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558de75b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558de75b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3cb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3cb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3cb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558de75b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (2243 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556872aeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556872aebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556872aef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbf3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbf398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbf3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbf391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556872a84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556872a84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556872a698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556872718e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556872718b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbf391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbf391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbf391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556872718a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (2244 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/15718) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564abd11deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564abd11ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564abd11e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b62b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b62b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b62b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b62b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564abd0b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564abd0b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564abd0988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564abcd47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564abcd47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b62b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b62b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b62b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564abcd47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (2245 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560c1dedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560c1deae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560c1dee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6090449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6090449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6090431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560c1d83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560c1d83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560c1d688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560c1a17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560c1a17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6090432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60904330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560c1a17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (2246 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604bb0e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604bb0e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604bb0e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d07049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d070a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d07049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d07031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604bb07cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604bb07ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604bb0618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604bad10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604bad10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d07032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d070330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d070330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604bad10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (2247 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555d5618eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555d5615e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555d561962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a2d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a2d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a2d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555d55aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555d55aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555d55938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555d5242e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555d5242b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a2d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a2d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a2d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555d5242a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (2248 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0,
# | ...
# `---data was truncated (10240/29451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056364ceeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056364cee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056364ceeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3721e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3721ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3721e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3721e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056364ce80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056364ce80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056364ce658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056364cb14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056364cb14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3721e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3721e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3721e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056364cb14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (2249 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2971f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2971f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2971f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f498f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f498f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f498f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f498f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c29718ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c29718ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2971738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c296e22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c296e22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f498f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f498f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f498f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c296e22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (2250 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a35ea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a35e9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a35ea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff740d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff740d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff740d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff740ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a35e37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a35e37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a35e1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a35acbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a35acbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff740ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff740cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff740cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a35acba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (2251 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/25287) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594c0a90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594c0a8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594c0a9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b97c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b97ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b97c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b97c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594c0a26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594c0a26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594c0a0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594c06bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594c06bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b97c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b97c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b97c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594c06baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (2252 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c  -check-prefix=RV64ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c354913eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c354910e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c35491462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3de3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3de3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3de3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3de3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3548a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3548a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c35488e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c35453de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c35453db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3de3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3de3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3de3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c35453da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (2253 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056183f9e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056183f9e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056183f9e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd837905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd83795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd837905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8378ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056183f97dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056183f97da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056183f9628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056183f611e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056183f611b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8378eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8378ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8378ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056183f611a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (2254 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/70979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec988daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec988d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec988db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6742649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67426a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6742649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6742631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec98870bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec98870a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec988558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec98504e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec98504b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6742632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67426330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67426330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec98504a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (2255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd4e607eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd4e604e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd4e60862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe18249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe182a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe18249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe18231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd4e59dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd4e59da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd4e5828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd4e231e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd4e231b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe18232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe182330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe182330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd4e231a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (2256 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c1cc42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c1cc3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c1cc4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc40133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc4018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc40133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc4011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c1cbd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c1cbd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c1cbbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c1c86ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c1c86cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc4011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc4011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc4011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c1c86ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (2257 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559eebb7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559eebb77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559eebb7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7e9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7e995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7e9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7e98ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559eebb10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559eebb10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559eebaf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559eeb7a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559eeb7a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7e98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7e98ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7e98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559eeb7a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (2258 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056180172eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056180172be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056180172f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8629b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8629b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8629b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8629b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618016c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618016c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618016a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561801358e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561801358b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8629b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8629b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8629b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561801358a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (2259 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3ef10eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3ef10be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3ef10f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa375249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3752a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa375249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa375231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3ef0a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3ef0a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3ef0898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3eed38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3eed38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa375232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3752330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3752330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3eed38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (2260 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578383b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578383b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578383b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c62849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c62849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c62831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055783834ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055783834ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578383338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557837fe2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557837fe2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c62832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c628330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557837fe2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (2261 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a46c01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a46bfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a46c0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa548f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa548f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa548f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa548f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a46b97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a46b97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a46b7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a4682be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a4682bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa548f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa548f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa548f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a4682ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (2262 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599697d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599697d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599697d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbecbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbecbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbecbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbecbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055996976ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055996976ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599697538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559969402e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559969402b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbecbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbecbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbecbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559969402a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (2263 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f8b144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f8b141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f8b14562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66ce049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66ce0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66ce049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66ce031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f8b0dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f8b0daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f8b0bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f8ad6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f8ad6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66ce032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66ce0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66ce0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f8ad6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (2264 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddde6d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddde6d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddde6d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd901849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9018a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd901849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd901831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddde66cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddde66ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddde6518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddde300e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddde300b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd901832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9018330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9018330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddde300a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (2265 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f235cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f235cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f235d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01a5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f23565bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f23565a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f2354a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f231f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f231f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01a5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f231f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (2266 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a51276eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a51273e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a5127762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa324249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3242a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa324249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa324231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a5120cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a5120ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a511f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a50ea0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a50ea0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa324232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3242330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3242330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a50ea0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (2267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x 
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584fb980eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584fb97de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584fb98162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00fa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00fa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00fa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00fa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584fb916bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584fb916a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584fb8fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584fb5aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584fb5aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00fa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00fa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00fa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584fb5aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (2268 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i)
# |   store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i)
# |   store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i)
# |   store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i)
# |   store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i)
# |   store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i)
# |   store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i)
# |   store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i)
# |   store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i)
# |   store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i)
# |   store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i)
# |   store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i)
# |   st
# | ...
# `---data was truncated (10240/16770) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000555beb8e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555beb8e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555beb8e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02ccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02ccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02ccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02ccf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555beb87ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555beb87ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555beb8638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555beb512e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555beb512b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02ccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02ccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02ccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555beb512a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (2269 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vmv_v_v_i16mf4(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vmv_v_v_i16mf2(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vmv_v_v_i16m1(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vmv_v_v_i16m2(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vmv_v_v_i16m4(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vmv_v_v_i16m8(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/68067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a1454beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a14548e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a1454c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0215049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02150a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0215049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0215031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a144e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a144e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a144c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a14175e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a14175b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0215032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02150330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02150330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a14175a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (2270 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597870dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597870dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597870e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd518133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd51818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd518133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd51811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559787075bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559787075a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055978705a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559786d09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559786d09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd51811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd51811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd51811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559786d09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (2271 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056143feceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056143fecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056143fecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00bef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00bef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00bef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00bef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056143fe64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056143fe64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056143fe498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056143faf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056143faf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00bef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00bef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00bef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056143faf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (2272 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581944b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581944b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581944ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbee81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbee8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbee81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbee803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055819444fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055819444fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581944348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581940e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581940e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbee804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbee8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbee8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581940e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (2273 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dec67dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dec67dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dec67e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ae4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ae4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ae4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ae4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dec6775bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dec6775a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dec675a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dec6409e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dec6409b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ae4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ae4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ae4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dec6409a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (2274 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i)
# |   %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8>
# |   store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i)
# |   %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i)
# |   %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8>
# |   store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i)
# |   %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i)
# |   %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8>
# |   store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i)
# |   %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i)
# |   %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8>
# |   store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i)
# |   %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i)
# |   %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8>
# |   store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i)
# |   %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i)
# |   %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8>
# |   store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x
# | ...
# `---data was truncated (10240/16447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c07a115eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c07a112e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c07a11662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f136e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f136e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f136e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f136e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c07a0abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c07a0aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c07a0908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c079d3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c079d3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f136e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f136e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f136e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c079d3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (2275 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c982976eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c982973e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c98297762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aeff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aeff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aeff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aeff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c98290cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c98290ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9828f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9825a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9825a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2aeff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aeff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aeff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9825a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (2276 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056405b977eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056405b974e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056405b97862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f099d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f099d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f099d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f099d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056405b90dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056405b90da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056405b8f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056405b5a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056405b5a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f099d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f099d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f099d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056405b5a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (2277 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdebdbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdebdbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdebdbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc05d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc05d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc05d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc05d2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdebd54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdebd54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdebd398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdeb9e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdeb9e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc05d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc05d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc05d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdeb9e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (2278 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562980635eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562980632e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056298063662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f622b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f622b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f622b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f622b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629805cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629805cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629805b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056298025fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056298025fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f622b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f622b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f622b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056298025fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (2279 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e711a49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e711a46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e711a4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2455533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f245558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2455533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f245551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7119dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7119dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7119c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e711673e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e711673b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f245551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f245551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f245551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e711673a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (2280 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f66e11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f66e0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f66e1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb49a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb49a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb49a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb49a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f66da7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f66da7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f66d8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f66a3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f66a3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb49a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb49a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb49a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f66a3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (2281 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcreate_v_f16m1_f16m2(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %3 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %2, <vscale x 4 x half> %1, i64 4)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m1_f16m4(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %5 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %4, <vscale x 4 x half> %1, i64 4)
# |   %6 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %5, <vscale x 4 x half> %2, i64 8)
# |   %7 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %6, <vscale x 4 x half> %3, i64 12)
# |   ret <vscale x 16 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m1_f16m8(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   %v4.addr = alloca <vscale x 4 x half>, align 2
# |   %v5.addr = alloca <vscale x 4 x half>, align 2
# |   %v6.addr = alloca <vscale x 4 x half>, align 2
# |   %v7.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x half> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x half> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x half> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x half> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x half>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x half>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x half>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x half>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %9 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %8, <vscale x 4 x half> %1, i64 4)
# |   %10 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %9, <vscale x 4 x half> %2, i64 8)
# |   %11 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %10, <vscale x 4 x half> %3, i64 12)
# |   %12 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %11, <vscale x 4 x half> %4, i64 16)
# |   %13 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %12, <vscale x 4 x half> %5, i64 20)
# |   %14 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %13, <vscale x 4 x half> %6, i64 24)
# |   %15 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %14, <vscale x 4 x half> %7, i64 28)
# |   ret <vscale x 32 x half> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m2_f16m4(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %3 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %2, <vscale x 8 x half> %1, i64 8)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m2_f16m8(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   %v2.addr = alloca <vscale x 8 x half>, align 2
# |   %v3.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %5 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %4, <vscale x 8 x half> %1, i64 8)
# |   %6 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %5, <vscale x 8 x half> %2, i64 16)
# |   %7 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %6, <vscale x 8 x half> %3, i64 24)
# |   ret <vscale x 32 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m4_f16m8(<vscale x 16 x half> %v0, <vscale x 16 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x half>, align 2
# |   %v1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> %0, i64 0)
# |   %3 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %2, <vscale x 16 x half> %1, i64 16)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcreate_v_f32m1_f32m2(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 2 x float>, align 4
# |   %v1.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %v0, ptr %v0.addr, align 4
# |   store <vscale x 2 x float> %v1, ptr %v1.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %v0.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %v1.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> %0, i64 0)
# |   %3 = call <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/593252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb7d4abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb7d4a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb7d4ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1350849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1350849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1350831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb7d441bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb7d441a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb7d4268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb7d0d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb7d0d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1350832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13508330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb7d0d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (2282 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557d28c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557d28bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557d28c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf02c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf02ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf02c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf02c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557d2856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557d2856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557d283b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557d24eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557d24eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf02c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf02c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf02c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557d24eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (2283 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, a
# | ...
# `---data was truncated (10240/18875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600159c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600159c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600159c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f442fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f442fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f442fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f442fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056001595ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056001595ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600159438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600155f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600155f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f442fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f442fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f442fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600155f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2284 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscal
# | ...
# `---data was truncated (10240/12471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbf47cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbf47c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbf47cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95a0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95a00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95a0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95a0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbf4761bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbf4761a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbf47468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbf43f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbf43f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95a0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95a00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95a00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbf43f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (2285 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b451c9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b451c9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b451c9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d5c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d5c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d5c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d5c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b451c34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b451c34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b451c198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4518c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4518c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d5c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d5c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d5c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4518c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (2286 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607e61c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607e61bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607e61c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f817db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f817db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f817db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f817db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e6157bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607e6157a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607e613c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607e5debe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607e5debb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f817db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f817db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f817db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e5deba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (2287 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556eaaa3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556eaaa3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556eaaa4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b41d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b41d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b41d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b41d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556eaa9d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556eaa9d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556eaa9ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556eaa669e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556eaa669b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b41d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b41d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b41d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eaa669a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (2288 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = loa
# | ...
# `---data was truncated (10240/18917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580765f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580765f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580765fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0523133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f052318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0523133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f052311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055807658fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055807658fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580765748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558076223e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558076223b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f052311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f052311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f052311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558076223a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (2289 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e9d8c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e9d8c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e9d8c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dca631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e9d85dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e9d85da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e9d8428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e9d4f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e9d4f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0dca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dca6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e9d4f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (2290 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmac
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a088238eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a088235e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a08823962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f607e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f607e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f607e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f607e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0881cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0881cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0881b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a087e62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a087e62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f607e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f607e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f607e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a087e62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (2291 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, al
# | ...
# `---data was truncated (10240/92370) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eab3f08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eab3f05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eab3f0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fa6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fa6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fa6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fa6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eab3e9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eab3e9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eab3e838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eab3b32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eab3b32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fa6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fa6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fa6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eab3b32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (2292 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056080f41deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056080f41ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056080f41e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40b6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40b638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40b6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40b631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056080f3b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056080f3b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056080f3988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056080f047e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056080f047b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40b631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40b631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40b631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056080f047a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (2293 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c  -check-prefix=RV64ZKND-ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596b8b78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596b8b75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596b8b7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd53fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd53fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd53fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd53fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596b8b0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596b8b0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596b8af38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596b87a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596b87a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd53fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd53fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd53fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596b87a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm_acle_swp.c (2294 of 27910)
******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7m-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret i32 %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ca67dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ca67d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ca67dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f873c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f873c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f873c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f873c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ca6771bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ca6771a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ca67568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ca6405e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ca6405b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f873c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f873c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f873c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ca6405a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (2295 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557af6bddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557af6bdae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557af6bde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b63049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b630a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b63049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b63031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557af6b73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557af6b73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557af6b588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557af6807e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557af6807b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b63032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b630330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b630330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557af6807a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (2296 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2cd5d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2cd5d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2cd5d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6ca01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6ca0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6ca01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6ca003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2cd56cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2cd56ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2cd5518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2cd200e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2cd200b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6ca004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6ca0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6ca0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2cd200a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (2297 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f725cc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f725cbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f725cc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8e9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8e938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8e9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8e931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f725c56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f725c56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f725c3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7258eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7258eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8e931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8e931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8e931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7258eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (2298 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056462c7d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056462c7d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056462c7d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80ecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80ecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80ecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80ecb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056462c769bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056462c769a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056462c74e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056462c3fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056462c3fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80ecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80ecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80ecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056462c3fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (2299 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614be70feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614be70ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614be71062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7423933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f742398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7423933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f742391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614be6a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614be6a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614be68a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614be339e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614be339b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f742391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f742391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f742391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614be339a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (2300 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b486142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b48613fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b48614362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc32da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc32daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc32da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc32da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4860d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4860d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4860bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b485d6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b485d6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc32da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc32da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc32da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b485d6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (2301 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fe14e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fe14e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fe14e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedfae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedfaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedfae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedfae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fe147cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fe147ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fe14618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fe1110e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fe1110b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedfae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedfae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedfae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fe1110a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (2302 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(
# | ...
# `---data was truncated (10240/32505) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056420bfabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056420bfa8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056420bfac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9b1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9b1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9b1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9b1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056420bf41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056420bf41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056420bf268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056420bbd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056420bbd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9b1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9b1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9b1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056420bbd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (2303 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c6e10beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c6e108e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c6e10c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0215905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f021595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0215905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02158ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c6e0a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c6e0a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c6e0868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c6dd35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c6dd35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02158eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02158ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02158ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c6dd35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (2304 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store
# | ...
# `---data was truncated (10240/79497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606c9c01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606c9bfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606c9c0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f739ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f739eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f739ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f739ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606c9b97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606c9b97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606c9b7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606c982be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606c982bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f739ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f739ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f739ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606c982ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (2305 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64, i64,
# | ...
# `---data was truncated (10240/120460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f800519eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f800516e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f80051a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4b7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4b738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4b7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4b731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8004afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8004afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8004948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f800143e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f800143b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4b731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4b731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4b731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f800143a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (2306 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d99659eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d99656e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d9965a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7001849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70018a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7001849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7001831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d995efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d995efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d995d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d99283e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d99283b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7001832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70018330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70018330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d99283a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (2307 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fea1054eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fea1051e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fea105562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69a2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fea0feabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fea0feaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fea0fcf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fea0c7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fea0c7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69a24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fea0c7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (2308 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4e22a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4e22a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4e22a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ce7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ce7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ce7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ce7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4e223abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4e223aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4e221f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4e1ecee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4e1eceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ce7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ce7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ce7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4e1ecea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (2309 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/100952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f28935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f28932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f2893662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5fb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5fb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5fb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5fb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f288cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f288cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f288b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f2855fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f2855fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5fb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5fb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5fb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f2855fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (2310 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %b
# | ...
# `---data was truncated (10240/38307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee3a158eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee3a155e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee3a15962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f4a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f4a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f4a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f4a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee3a0eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee3a0eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee3a0d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee39d82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee39d82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f4a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f4a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f4a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee39d82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (2311 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055953ecffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055953ecfce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055953ed0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4257e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4257ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4257e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4257e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055953ec95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055953ec95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055953ec7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055953e929e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055953e929b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4257e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4257e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4257e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055953e929a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (2312 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0436e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0436dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0436e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b9c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b9c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b9c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b9c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e043676bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e043676a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e04365b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e04330ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e04330ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b9c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b9c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b9c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e04330aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (2313 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bac9a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bac9a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bac9a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fced0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fced078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fced0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fced071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bac93dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bac93da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bac9228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bac5d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bac5d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fced071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fced071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fced071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bac5d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (2314 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a175f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a175f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a175fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc1501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc150725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc1501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc15003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a1758fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a1758fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a175748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a17223e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a17223b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc15004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc150050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc150050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a17223a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (2315 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b1e626eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b1e623e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b1e62762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fcc105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fcc15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fcc105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fcc0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b1e5bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b1e5bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b1e5a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b1e250e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b1e250b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fcc0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fcc0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fcc0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b1e250a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (2316 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5ea7afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5ea7ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5ea7b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbce8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbce8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbce8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbce8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5ea745bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5ea745a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5ea72a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5ea3d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5ea3d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbce8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbce8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbce8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5ea3d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (2317 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d84905eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d84902e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d8490662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1837733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f183778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1837733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f183771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d8489bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d8489ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d848808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d8452fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d8452fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f183771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f183771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f183771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d8452fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (2318 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d29e386eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d29e383e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d29e38762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ce1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ce12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ce1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ce1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d29e31cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d29e31ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d29e3018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d29dfb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d29dfb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ce1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ce12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ce12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d29dfb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (2319 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/53678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b48a23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b48a20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b48a2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1268649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12686a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1268649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1268631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b489b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b489b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b4899e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b4864de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b4864db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1268632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12686330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12686330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b4864da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (2320 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1f3826eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1f3823e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1f382762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6444c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6444ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6444c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6444c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1f37bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1f37bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1f37a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1f3450e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1f3450b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6444c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6444c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6444c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1f3450a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (2321 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c43c21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c43c1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c43c2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae75105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae7515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae75105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae750ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c43bb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c43bb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c43b9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c4384be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c4384bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae750eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae750ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae750ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c4384ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (2322 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8dd437eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8dd434e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8dd43862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74cc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74cc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74cc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74cc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8dd3cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8dd3cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8dd3b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8dd061e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8dd061b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74cc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74cc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74cc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8dd061a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (2323 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync
# | ...
# `---data was truncated (10240/183423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a7a4d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a7a4d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a7a4d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f1fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f1fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f1fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f1fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a7a46ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a7a46ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a7a4538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a7a102e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a7a102b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f1fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f1fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f1fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a7a102a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (2324 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555eb1f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555eb1f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555eb1f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f645de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f645dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f645de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f645de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555eb1f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555eb1f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555eb1ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555eb1ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555eb1ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f645de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f645de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f645de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555eb1ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (2325 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afaeeedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afaeeeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afaeeee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff672a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff672aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff672a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff672a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afaee83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afaee83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afaee688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afaeb17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afaeb17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff672a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff672a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff672a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afaeb17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (2326 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f9eef7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f9eef4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f9eef862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa88ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa88caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa88ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa88ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f9ee8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f9ee8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f9ee728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f9eb21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f9eb21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa88ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa88ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa88ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f9eb21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (2327 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cf6a4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cf6a47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cf6a4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f109d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f109d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f109d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f109d4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cf69e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cf69e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cf69c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cf6674e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cf6674b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f109d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f109d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f109d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cf6674a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (2328 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594bb765eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594bb762e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594bb76662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2496505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f249655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2496505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24964ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594bb6fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594bb6fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594bb6e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594bb38fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594bb38fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24964eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24964ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24964ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594bb38fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (2329 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055daa8cfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055daa8cfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055daa8cfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc68cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc68cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc68cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc68cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daa8c93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055daa8c93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055daa8c788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055daa8927e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055daa8927b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc68cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc68cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc68cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daa8927a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (2330 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffb0549eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffb0546e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffb054a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdeb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdeb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdeb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdeb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffb04dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffb04dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffb04c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffb0173e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffb0173b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdeb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdeb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdeb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffb0173a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (2331 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646ce753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646ce750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646ce75462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe203d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe203d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe203d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe203d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646ce6e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646ce6e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646ce6ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646ce37de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646ce37db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe203d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe203d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe203d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646ce37da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (2332 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642337d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642337d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642337d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4998b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4998b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4998b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4998b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056423376abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056423376aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056423374f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642333fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642333feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4998b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4998b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4998b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642333fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (2333 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d65bc11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d65bc0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d65bc1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f360cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f360cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f360cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f360cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d65bba7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d65bba7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d65bb8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d65b83be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d65b83bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f360cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f360cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f360cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d65b83ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (2334 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb4896eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb4896be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb4896f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2775333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f277538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2775333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f277531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb48904bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb48904a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb488e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb48598e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb48598b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f277531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f277531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f277531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb48598a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (2335 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612da431eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612da42ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612da43262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e2c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e2c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e2c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e2c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612da3c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612da3c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612da3ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612da05be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612da05bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e2c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e2c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e2c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612da05ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (2336 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c  -check-prefix=RV32XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clo_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c0b16eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c0b16be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c0b16f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f473da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f473daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f473da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f473da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c0b104bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c0b104a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c0b0e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c0ad98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c0ad98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f473da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f473da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f473da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c0ad98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2337 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/26710) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f218de1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f218ddee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f218de262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e68933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e6898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e68933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e6891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f218d77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f218d77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f218d5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f218a0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f218a0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e6891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e6891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e6891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f218a0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (2338 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa75a34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa75a31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa75a3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4010849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40108a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4010849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4010831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa759cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa759caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa759af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa7565ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa7565eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4010832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40108330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40108330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa7565ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (2339 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0,
# | ...
# `---data was truncated (10240/28346) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e45d852eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e45d84fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e45d85362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1383649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13836a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1383649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1383631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e45d7e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e45d7e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e45d7cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e45d47ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e45d47cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1383632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13836330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13836330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e45d47ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (2340 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db1016deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db1016ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db1016e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f025c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f025c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f025c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f025c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db10103bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db10103a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db100e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db0fd97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db0fd97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f025c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f025c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f025c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db0fd97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (2341 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558aa9d19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aa9d16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aa9d1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e7a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e7a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e7a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e7a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aa9cafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558aa9cafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558aa9c948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558aa9943e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558aa9943b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e7a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e7a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e7a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558aa9943a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (2342 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c27a289eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c27a286e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c27a28a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faeb3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faeb38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faeb3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faeb3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c27a21fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c27a21fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c27a2048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c279eb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c279eb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faeb3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faeb38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faeb38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c279eb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (2343 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8738e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8738e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8738e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4569449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45694a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4569449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4569431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f87387bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f87387ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8738608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f87350fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f87350fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4569432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45694330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45694330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f87350fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-poly-add.c (2344 of 27910)
******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi    -target-feature +neon    -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   store <8 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <4 x i16>
# |   store <4 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <1 x i64>
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   store <16 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <16 x i8>, ptr %ref.tmp.i, align 8
# |   store <16 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <16 x i8>, ptr %__ret.i, align 8
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <8 x i16>
# |   store <8 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 8
# |   store <8 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i16>, ptr %__ret.i, align 8
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 8
# |   %__p1.addr.i = alloca <2 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = load <2 x i64>, ptr %b.addr, align 8
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   store <2 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i64>, ptr %ref.tmp.i, align 8
# |   store <2 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i64>, ptr %__ret.i, align 8
# |   ret <2 x i64> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557a7e451eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a7e44ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a7e45262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfce333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfce38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfce333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfce31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a7e3e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a7e3e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a7e3cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a7e07be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a7e07bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfce31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfce31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfce31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a7e07ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (2345 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f91f2beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f91f2bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f91f2bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa84ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa84caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa84ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa84ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f91f254bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f91f254a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f91f2398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f91eee8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f91eee8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa84ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa84ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa84ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f91eee8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (2346 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653daa1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653daa1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653daa1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1d8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1d878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1d8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1d871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653da9b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653da9b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653da9998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653da648e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653da648b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1d871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1d871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1d871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653da648a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (2347 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b75c08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b75c05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b75c0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9c8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9c88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9c8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9c8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b75b9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b75b9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b75b838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b75832e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b75832b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9c8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9c88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9c88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b75832a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (2348 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ffc3bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ffc3b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ffc3bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00b3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00b3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00b3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00b3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ffc351bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ffc351a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ffc3368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ffbfe5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ffbfe5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00b3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00b3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00b3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ffbfe5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (2349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f59380eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f5937de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f5938162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d95a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d95a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d95a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d95a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f59316bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f59316a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f592fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f58faae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f58faab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d95a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d95a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d95a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f58faaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (2350 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6c498ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6c4989e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6c498d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f922d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f922d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f922d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f922d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6c4922bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6c4922a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6c49078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6c45b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6c45b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f922d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f922d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f922d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6c45b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (2351 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628b89bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628b89bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628b89c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99cbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99cbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99cbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99cbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628b8955bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628b8955a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628b893a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628b85e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628b85e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99cbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99cbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99cbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628b85e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (2352 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d490a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d490a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d490a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1921e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1921ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1921e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1921e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d4903abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d4903aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d4901f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d48ccee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d48cceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1921e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1921e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1921e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d48ccea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (2353 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>
# | ...
# `---data was truncated (10240/153805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055741ba23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055741ba20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055741ba2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4215333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f421538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4215333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f421531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055741b9b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055741b9b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055741b99e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055741b64de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055741b64db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f421531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f421531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f421531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055741b64da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (2354 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575bcfa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575bcf9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575bcfa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1665533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f166558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1665533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f166551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575bcf36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575bcf36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575bcf1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575bcbcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575bcbcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f166551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f166551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f166551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575bcbcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (2355 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d792ba7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d792ba4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d792ba862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff084933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff08498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff084933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff08491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d792b3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d792b3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d792b228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7927d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7927d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff08491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff08491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff08491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7927d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (2356 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %sr
# | ...
# `---data was truncated (10240/288111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa579a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa579a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa579a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f24a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f24aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f24a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f24a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa5793dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa5793da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa579228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa575d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa575d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f24a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f24a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f24a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa575d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (2357 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/67482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056324d80deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056324d80ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056324d80e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65c4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65c40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65c4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65c4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056324d7a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056324d7a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056324d7888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056324d437e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056324d437b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65c4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65c40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65c40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056324d437a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (2358 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv
# | ...
# `---data was truncated (10240/53548) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c86e8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c86e88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c86e8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3834649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38346a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3834649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3834631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c86e21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c86e21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c86e068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c86ab5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c86ab5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3834632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38346330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38346330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c86ab5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (2359 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af53df9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af53df6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af53dfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80e2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80e278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80e2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80e271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af53d8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af53d8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af53d748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af53a23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af53a23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80e271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80e271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80e271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af53a23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (2360 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/121927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055999c30ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055999c309e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055999c30d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ec9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ec9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ec9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ec9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055999c2a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055999c2a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055999c2878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055999bf36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055999bf36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ec9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ec9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ec9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055999bf36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (2361 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d27c8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d27c87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d27c8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea29249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea292a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea29249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea29231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d27c20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d27c20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d27c058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d278b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d278b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea29232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea292330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea292330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d278b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (2362 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/110070) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612c12fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612c12f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612c12fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0529333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f052938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0529333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f052931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612c1291bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612c1291a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612c12768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612c0f25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612c0f25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f052931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f052931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f052931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612c0f25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (2363 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ae3f93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ae3f90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ae3f9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37c9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37c958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37c9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37c951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ae3f29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ae3f29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ae3f0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ae3bbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ae3bbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37c951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37c951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37c951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ae3bbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (2364 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale
# | ...
# `---data was truncated (10240/11640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d8b5b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d8b5b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d8b5b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8874933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f887498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8874933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f887491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d8b54ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d8b54ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d8b5338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d8b1e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d8b1e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f887491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f887491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f887491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d8b1e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (2365 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<
# | ...
# `---data was truncated (10240/119297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c740163eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c740160e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c74016462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f377f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f377f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f377f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f377f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7400f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7400f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7400de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c73fd8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c73fd8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f377f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f377f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f377f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c73fd8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (2366 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align
# | ...
# `---data was truncated (10240/102872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa9264feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa9264ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa9265062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa57e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa57e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa57e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa57e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa925e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa925e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa925ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa92279e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa92279b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa57e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa57e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa57e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa92279a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (2367 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c78f87feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c78f87ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c78f88062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f452b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f452b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f452b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f452b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c78f815bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c78f815a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c78f7fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c78f4a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c78f4a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f452b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f452b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f452b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c78f4a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (2368 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f529b64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f529b61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f529b6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84e8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84e898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84e8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84e891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f529afabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f529afaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f529adf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f52978ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f52978eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84e891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84e891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84e891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f52978ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (2369 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe395f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe395f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe395f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dde049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dde0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dde049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dde031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe39589bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe39589a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe3956e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe3921de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe3921db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9dde032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dde0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dde0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe3921da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (2370 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c62cd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c62cd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c62cd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb7ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb7ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb7ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb7ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c62c6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c62c6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c62c518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c62900e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c62900b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb7ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb7ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb7ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c62900a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (2371 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cfd769eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cfd766e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cfd76a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb9be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb9bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb9be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb9be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cfd6ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cfd6ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cfd6e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cfd393e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cfd393b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb9be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb9be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb9be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cfd393a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (2372 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c8b503eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c8b500e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c8b50462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d6a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d6a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d6a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d6a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c8b499bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c8b499a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c8b47e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c8b12de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c8b12db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d6a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d6a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d6a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c8b12da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (2373 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdc8e50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdc8e4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdc8e5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1848333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f184838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1848333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f184831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdc8de6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdc8de6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdc8dcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdc8a7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdc8a7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f184831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f184831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f184831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdc8a7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (2374 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620ff167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620ff164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620ff16862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff585449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5854a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff585449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff585431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620ff0fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620ff0fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620ff0e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620fed91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620fed91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff585432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5854330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5854330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620fed91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (2375 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i6
# | ...
# `---data was truncated (10240/67158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af52665eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af52662e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af5266662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dccd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dccd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dccd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dccd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af525fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af525fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af525e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af5228fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af5228fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5dccd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dccd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dccd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af5228fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (2376 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556ffa7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556ffa7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556ffa7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7df4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7df498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7df4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7df491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556ffa14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556ffa14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556ff9f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556ff6a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556ff6a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7df491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7df491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7df491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556ff6a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (2377 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/62752) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563358ea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563358e9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563358ea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42fc01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42fc0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42fc01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42fc003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563358e37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563358e37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563358e1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563358acbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563358acbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42fc004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42fc0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42fc0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563358acba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (2378 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568c9092eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568c908fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568c909362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2887b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2887b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2887b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2887b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568c9028bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568c9028a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568c900d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568c8cbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568c8cbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2887b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2887b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2887b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568c8cbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (2379 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 
# | ...
# `---data was truncated (10240/98445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1fad75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1fad72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1fad7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9ca133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9ca18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9ca133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9ca11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1fad0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1fad0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1facf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1fa99fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1fa99fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9ca11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9ca11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9ca11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1fa99fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (2380 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d14244eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d14241e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d1424562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf1c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf1c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf1c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf1c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d141dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d141daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d141bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d13e6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d13e6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf1c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf1c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf1c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d13e6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (2381 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c0c45eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c0c45be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c0c45f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d42249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d42249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d42231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c0c3f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c0c3f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c0c3d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c0c088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c0c088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d42232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d422330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c0c088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (2382 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056321d5e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056321d5e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056321d5e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff803649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8036a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff803649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff803631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056321d57abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056321d57aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056321d55f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056321d20ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056321d20eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff803632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8036330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8036330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056321d20ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (2383 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590bc4bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590bc4b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590bc4bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf0f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf0f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf0f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf0f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590bc452bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590bc452a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590bc4378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590bc0e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590bc0e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf0f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf0f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf0f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590bc0e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (2384 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b71febceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b71feb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b71febd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bd8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bd8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bd8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bd8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b71fe52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b71fe52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b71fe378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b71fae6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b71fae6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bd8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bd8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bd8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b71fae6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (2385 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec588f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec588f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec588fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f711d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f711d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f711d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f711d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec5888fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec5888fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec588748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec58523e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec58523b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f711d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f711d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f711d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec58523a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (2386 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x 
# | ...
# `---data was truncated (10240/18674) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dffa72ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dffa729e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dffa72d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9191933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f919198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9191933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f919191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dffa6c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dffa6c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dffa6a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dffa356e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dffa356b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f919191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f919191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f919191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dffa356a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (2387 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb14d8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb14d8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb14d8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f889f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f889f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f889f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f889f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb14d23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb14d23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb14d088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb149b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb149b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f889f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f889f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f889f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb149b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (2388 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a6e133eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a6e130e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a6e13462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe431449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4314a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe431449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe431431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a6e0c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a6e0c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a6e0ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a6dd5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a6dd5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe431432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4314330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4314330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a6dd5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (2389 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/273705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639fbb25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639fbb22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639fbb2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ef7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ef7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ef7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ef7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639fbabbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639fbabba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639fbaa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639fb74fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639fb74fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ef7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ef7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ef7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639fb74fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (2390 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563310af2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563310aefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563310af362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72b0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72b038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72b0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72b031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563310a88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563310a88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563310a6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056331071ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056331071cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72b031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72b031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72b031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056331071ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (2391 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f819c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f819bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f819c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8abe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8abe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8abe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8abe431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f81956bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f81956a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f8193b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f815eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f815eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8abe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8abe4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8abe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f815eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (2392 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %p0.addr = alloca <4 x float>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <4 x float> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <4 x float>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005654aea00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654ae9fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654aea0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa442249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa442249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa442231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654ae996bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654ae996a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654ae97b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654ae62ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654ae62ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa442232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4422330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654ae62aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (2393 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e2fdb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e2fdb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e2fdb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6627933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f662798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6627933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f662791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e2fd49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e2fd49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e2fd2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e2f9dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e2f9ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f662791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f662791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f662791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e2f9dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (2394 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560981c4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560981c47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560981c4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa5c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa5c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa5c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa5c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560981be0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560981be0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560981bc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560981874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560981874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa5c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa5c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa5c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560981874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (2395 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055762b33eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055762b33be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055762b33f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe60f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe60f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe60f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe60f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055762b2d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055762b2d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055762b2b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055762af68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055762af68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe60f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe60f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe60f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055762af68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (2396 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/26976) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556497c00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556497bfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556497c0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aeec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aeeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aeec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aeec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556497b96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556497b96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556497b7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055649782ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055649782ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2aeec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aeec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aeec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055649782aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (2397 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638bef4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638bef47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638bef4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e73905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e7395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e73905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e738ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638beee0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638beee0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638beec58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638beb74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638beb74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e738eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e738ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e738ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638beb74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (2398 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |  
# | ...
# `---data was truncated (10240/30268) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bb114ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bb1149e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bb114d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a84849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a848a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a84849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a84831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bb10e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bb10e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bb10c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bb0d76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bb0d76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a84832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a848330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a848330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bb0d76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (2399 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634e0f6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634e0f68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634e0f6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27f8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27f84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27f8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27f8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634e0f01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634e0f01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634e0ee68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634e0b95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634e0b95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27f8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27f84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27f84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634e0b95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (2400 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fcc5a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fcc5a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fcc5a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6b5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6b5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6b5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6b5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fcc53abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fcc53aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fcc51f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fcc1cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fcc1ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6b5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6b5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6b5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fcc1cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (2401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9d9b8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9d9b87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9d9b8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae81133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae8118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae81133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae8111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9d9b20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9d9b20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9d9b058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9d97b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9d97b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae8111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae8111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae8111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9d97b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (2402 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbd311deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbd311ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbd311e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38b1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38b1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38b1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38b1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbd30b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbd30b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbd30988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbd2d47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbd2d47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38b1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38b1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38b1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbd2d47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (2403 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cf2297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cf2294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cf229862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe420133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe42018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe420133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe42011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cf222dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cf222da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cf22128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cf1ec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cf1ec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe42011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe42011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe42011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cf1ec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (2404 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd081a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd081a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd081a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b22f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b22f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b22f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b22f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd0813cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd0813ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd081218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd07dd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd07dd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b22f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b22f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b22f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd07dd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (2405 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564753c2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564753c27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564753c2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2536e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2536ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2536e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2536e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564753bc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564753bc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564753ba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564753854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564753854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2536e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2536e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2536e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564753854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (2406 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586b0d8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586b0d8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586b0d8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb549d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb549d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb549d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb549d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586b0d24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586b0d24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586b0d098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586b09b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586b09b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb549d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb549d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb549d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586b09b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (2407 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603623eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603623e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603623ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc84933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc8498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc84933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc8491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560362382bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560362382a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603623678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560362016e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560362016b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc8491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc8491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc8491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560362016a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (2408 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b2c3aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b2c3a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b2c3ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f357a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f357a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f357a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f357a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b2c340bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b2c340a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b2c3258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b2bfd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b2bfd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f357a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f357a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f357a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b2bfd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (2409 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628b3725eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628b3722e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628b372662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d61e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d61e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d61e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d61e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628b36bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628b36bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628b36a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628b334fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628b334fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d61e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d61e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d61e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628b334fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (2410 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = al
# | ...
# `---data was truncated (10240/40137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5f991beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5f9918e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5f991c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c10e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c10e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c10e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c10e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5f98b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5f98b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5f98968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5f9545e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5f9545b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c10e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c10e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c10e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5f9545a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (2411 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fa0d8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fa0d8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fa0d8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ceb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ceb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ceb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ceb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fa0d23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fa0d23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fa0d088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fa09b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fa09b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ceb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ceb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ceb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fa09b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (2412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/26756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa66438eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa66435e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa6643962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc420c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc420c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc420c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc420c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa663cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa663cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa663b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa66062e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa66062b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc420c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc420c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc420c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa66062a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (2413 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b71706eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b71703e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b7170762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8c401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8c40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8c401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8c4003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b7169cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b7169ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b716818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b71330e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b71330b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8c4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8c40050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8c40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b71330a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (2414 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564766704eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564766701e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056476670562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca77c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca77ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca77c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca77c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056476669abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056476669aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056476667f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056476632ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056476632eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca77c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca77c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca77c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056476632ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (2415 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb6d255eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb6d252e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb6d25662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c23849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c23849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c23831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb6d1ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb6d1eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb6d1d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb6ce7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb6ce7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c23832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c238330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb6ce7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (2416 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdb35d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdb35d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdb35d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2469b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2469b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2469b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2469aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdb3569bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdb3569a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdb354e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdb31fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdb31fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2469aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2469aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2469aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdb31fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (2417 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 8 x 
# | ...
# `---data was truncated (10240/124028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642de96deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642de96ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642de96e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77e0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77e078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77e0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77e071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642de903bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642de903a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642de8e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642de597e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642de597b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77e071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77e071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77e071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642de597a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (2418 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/41659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558da9627eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558da9624e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558da962862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d8bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d8bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d8bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d8bc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558da95bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558da95bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558da95a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558da9251e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558da9251b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d8bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d8bc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d8bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558da9251a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (2419 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d9091eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d9091be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d9091f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc69d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc69d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc69d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc69d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d908b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d908b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d908998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d90548e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d90548b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc69d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc69d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc69d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d90548a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (2420 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056392747feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056392747ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056392748062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8ef533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8ef58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8ef533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8ef51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563927415bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563927415a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639273fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639270a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639270a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8ef51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8ef51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8ef51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639270a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (2421 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ff9c8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ff9c87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ff9c8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f663aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f663aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f663aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f663aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ff9c20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ff9c20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ff9c058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ff98b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ff98b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f663aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f663aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f663aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ff98b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (2422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055633c75ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055633c759e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055633c75d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b2aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b2aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b2aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b2aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055633c6f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055633c6f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055633c6d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055633c386e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055633c386b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b2aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b2aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b2aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055633c386a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (2423 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cc2623eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cc2620e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cc262462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f56533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f5658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f56533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f5651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cc25b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cc25b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cc259e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cc224de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cc224db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f5651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f5651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f5651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cc224da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (2424 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635ee946eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635ee943e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635ee94762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c42d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c42d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c42d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c42ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635ee8dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635ee8dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635ee8c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635ee570e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635ee570b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c42ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c42cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c42cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635ee570a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (2425 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8f970aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8f9707e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8f970b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8685533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f868558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8685533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f868551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8f96a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8f96a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8f96858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8f9334e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8f9334b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f868551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f868551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f868551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8f9334a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (2426 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/31876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055705c7e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055705c7e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055705c7e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd33bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd33bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd33bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd33bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055705c779bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055705c779a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055705c75e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055705c40de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055705c40db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd33bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd33bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd33bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055705c40da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (2427 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d571e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d571e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d571e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1525049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15250a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1525049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1525031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d57179bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d57179a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d5715e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d56e0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d56e0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1525032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15250330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15250330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d56e0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (2428 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559413adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559413aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559413ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ef9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ef978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ef9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ef971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555941343bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555941343a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559413288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555940fd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555940fd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ef971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ef971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ef971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555940fd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (2429 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e39ec84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e39ec81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e39ec8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3b6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3b64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3b6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3b6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e39ec1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e39ec1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e39ebff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e39e8aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e39e8aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3b6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3b64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3b64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e39e8aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (2430 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c  -check-prefix=RV64ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64im(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.aes64im(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ds(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64im(i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9efaaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9efaa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9efaab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9810705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f981075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9810705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98106ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9efa40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9efa40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9efa258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9ef6d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9ef6d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98106eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98106ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98106ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9ef6d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (2431 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/22375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ab4101eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ab40fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ab410262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f6df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f6df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f6df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f6df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ab4097bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ab4097a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ab407c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ab3d2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ab3d2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f6df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f6df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f6df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ab3d2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (2432 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652b5a3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652b5a3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652b5a4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6759733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f675978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6759733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f675971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652b59d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652b59d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652b59ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652b5669e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652b5669b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f675971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f675971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f675971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652b5669a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (2433 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1
# | ...
# `---data was truncated (10240/154215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd2efceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfd2ef9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfd2efd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd01ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd01baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd01ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd01ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd2e92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfd2e92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfd2e778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfd2b26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfd2b26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd01ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd01ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd01ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd2b26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (2434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/63510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056054ebb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056054ebafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056054ebb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f050fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f050fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f050fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f050fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056054eb48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056054eb48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056054eb2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056054e7dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056054e7dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f050fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f050fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f050fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056054e7dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (2435 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561005ab6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561005ab3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561005ab762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dccb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dccb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dccb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dccb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561005a4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561005a4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561005a318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610056e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610056e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dccb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dccb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dccb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610056e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (2436 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |  
# | ...
# `---data was truncated (10240/22074) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585869a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585869a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585869a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9438905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f943895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9438905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94388ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055858693bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055858693ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585869208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585865cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585865cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94388eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94388ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94388ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585865cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (2437 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564434f5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564434f58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564434f5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f99e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f99ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f99e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f99e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564434ef1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564434ef1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564434ed68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564434b85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564434b85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f99e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f99e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f99e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564434b85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (2438 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b89cdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b89cd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b89cdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe153333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe15338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe153333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe15331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b89c72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b89c72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b89c578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b89906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b89906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe15331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe15331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe15331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b89906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (2439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055576ec4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055576ec4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055576ec5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a13933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a1398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a13933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a1391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055576ebe5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055576ebe5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055576ebca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055576e879e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055576e879b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a1391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a1391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a1391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055576e879a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (2440 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556267157eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556267154e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055626715862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cbb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cbb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cbb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cbb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562670edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562670eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562670d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556266d81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556266d81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cbb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cbb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cbb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556266d81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (2441 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557938c19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557938c16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557938c1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa254449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2544a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa254449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa254431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557938bafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557938bafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557938b948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557938843e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557938843b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa254432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2544330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2544330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557938843a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (2442 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8bc478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8bc475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8bc47962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c96933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c9698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c96933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c9691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8bc40ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8bc40ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8bc3f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8bc0a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8bc0a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c9691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c9691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c9691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8bc0a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (2443 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607dcbc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607dcbc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607dcbc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10a5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10a52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10a5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10a5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607dcb5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607dcb5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607dcb428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607dc7f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607dc7f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10a5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10a52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10a52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607dc7f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (2444 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x
# | ...
# `---data was truncated (10240/24328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8da8abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8da8a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8da8ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66fc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66fc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66fc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66fc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8da841bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8da841a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8da8268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8da4d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8da4d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66fc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66fc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66fc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8da4d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (2445 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618484d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618484cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618484d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7030449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70304a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7030449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7030431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561848466bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561848466a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056184844b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618480fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618480fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7030432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70304330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70304330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618480faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (2446 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cdb6e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cdb6dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cdb6e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd8c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd8c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd8c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd8c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cdb678bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cdb678a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cdb65d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cdb30ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cdb30cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd8c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd8c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd8c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cdb30ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (2447 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619f59faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619f59f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619f59fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f084b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f084b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f084b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f084b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619f5990bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619f5990a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619f59758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619f5624e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619f5624b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f084b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f084b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f084b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619f5624a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (2448 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fc1c1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fc1c17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fc1c1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39d2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fc1bb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fc1bb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fc1b958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fc1844e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fc1844b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fc1844a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (2449 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | defin
# | ...
# `---data was truncated (10240/13035) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b383af1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b383aeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b383af262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda86305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda8635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda86305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda862ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b383a87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b383a87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b383a6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b38371be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b38371bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda862eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda862ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda862ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b38371ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (2450 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr
# | ...
# `---data was truncated (10240/29319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e13acd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e13acd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e13acda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f032a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f032a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f032a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f032a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e13ac6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e13ac6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e13ac548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e13a903e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e13a903b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f032a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f032a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f032a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e13a903a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (2451 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af3f3bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af3f3b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af3f3bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe20d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe20d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe20d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe20d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af3f352bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af3f352a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af3f3378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af3efe6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af3efe6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe20d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe20d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe20d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af3efe6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (2452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ed205deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ed205ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ed205e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fc3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fc318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fc3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fc311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ed1ff3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ed1ff3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ed1fd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ed1c87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ed1c87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fc311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fc311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fc311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ed1c87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (2453 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056207333eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056207333be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056207333f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b1c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b1c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b1c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b1c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620732d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620732d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620732b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562072f68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562072f68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b1c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b1c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b1c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562072f68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (2454 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555b5290eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555b528de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555b529162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc89049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc890a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc89049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc89031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555b5226bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555b5226a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555b520b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555b4ebae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555b4ebab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc89032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc890330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc890330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555b4ebaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (2455 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %
# | ...
# `---data was truncated (10240/20326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c6353aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c63537e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c6353b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f577201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57720725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f577201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5772003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c634d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c634d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c634b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c63164e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c63164b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5772004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57720050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57720050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c63164a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (2456 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d12bf32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d12bf2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d12bf3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f6ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f6cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f6ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f6ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d12bec8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d12bec8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d12bead8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d12bb5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d12bb5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f6ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f6ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f6ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d12bb5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (2457 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test
# | ...
# `---data was truncated (10240/156773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561726caceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561726ca9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561726cad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcee2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcee278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcee2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcee271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561726c42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561726c42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561726c278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617268d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617268d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcee271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcee271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcee271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617268d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (2458 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592cb590eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592cb58de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592cb59162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae0eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae0eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae0eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae0eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592cb526bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592cb526a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592cb50b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592cb1bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592cb1bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae0eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae0eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae0eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592cb1baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (2459 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 
# | ...
# `---data was truncated (10240/126436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585600eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585600e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585600eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1a1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1a138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1a1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1a131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558560080bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558560080a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585600658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055855fd14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055855fd14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1a131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1a131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1a131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055855fd14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (2460 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558825116eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558825113e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055882511762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c1b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c1b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c1b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c1b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588250acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588250aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588250918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558824d40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558824d40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c1b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c1b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c1b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558824d40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (2461 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/80640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ca5ccdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ca5ccae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ca5cce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3708533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f370858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3708533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f370851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ca5c63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ca5c63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ca5c488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ca58f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ca58f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f370851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f370851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f370851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ca58f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (2462 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp sle i32 %2, %3
# |   %sle.i = zext i1 %4 to i32
# |   ret i32 %sle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp ule i32 %2, %3
# |   %sleu.i = zext i1 %4 to i32
# |   ret i32 %sleu.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = sext i16 %1 to i32
# |   %exths.i = sext i16 %1 to i32
# |   ret i32 %exths.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = zext i16 %1 to i32
# |   %exthz.i = zext i16 %1 to i32
# |   ret i32 %exthz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = sext i8 %1 to i32
# |   %extbs.i = sext i8 %1 to i32
# |   ret i32 %extbs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = zext i8 %1 to i32
# |   %extbz.i = zext i8 %1 to i32
# |   ret i32 %extbz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   st
# | ...
# `---data was truncated (10240/15696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ae7fdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ae7fdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ae7fdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f500ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f500ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f500ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f500ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ae7f74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ae7f74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ae7f598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ae7c08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ae7c08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f500ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f500ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f500ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ae7c08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (2463 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d284bd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d284bcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d284bd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff6c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff6c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff6c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff6c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d284b68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d284b68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d284b4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2847fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2847fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff6c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff6c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff6c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2847fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (2464 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/29371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb9954feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb9954ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb9955062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd89d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd89d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd89d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd89d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb994e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb994e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb994ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb99179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb99179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd89d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd89d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd89d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb99179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (2465 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f1a7ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f1a7e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f1a7ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc51d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc51d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc51d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc51d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f1a781bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f1a781a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f1a7668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f1a415e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f1a415b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc51d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc51d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc51d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f1a415a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (2466 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl
# | ...
# `---data was truncated (10240/27434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055919288deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055919288ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055919288e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3152b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3152b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3152b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3152aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559192823bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559192823a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591928088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591924b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591924b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3152aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3152aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3152aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591924b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (2467 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4f6283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4f6280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4f628462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7685649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7685649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7685631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4f6219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4f6219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4f61fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4f5eade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4f5eadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7685632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76856330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4f5eada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (2468 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb00cceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb00ccbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb00ccf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1d9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1d98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1d9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1d9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb00c64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb00c64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb00c498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb008f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb008f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1d9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1d98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1d98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb008f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (2469 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = l
# | ...
# `---data was truncated (10240/23247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d62506deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d62506ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d62506e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4509733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f450978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4509733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f450971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d625003bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d625003a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d624fe88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d624c97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d624c97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f450971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f450971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f450971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d624c97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (2470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570d1f68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570d1f65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570d1f6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b0e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b0e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b0e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b0e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570d1efebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570d1efea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570d1ee38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570d1b92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570d1b92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b0e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b0e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b0e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570d1b92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (2471 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ace625eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ace622e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ace62662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f288e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f288e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f288e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f288e8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ace5bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ace5bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ace5a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ace24fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ace24fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f288e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f288e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f288e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ace24fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (2472 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %
# | ...
# `---data was truncated (10240/47698) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c02dc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c02dbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c02dc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabfa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabfa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabfa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabfa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c02d58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c02d58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c02d3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c029ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c029ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabfa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabfa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabfa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c029eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (2473 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584f00f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584f00f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584f00f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcaa21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcaa2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcaa21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcaa203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584f008ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584f008ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584f00738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584efd22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584efd22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcaa204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcaa2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcaa2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584efd22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (2474 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5b7af8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5b7af5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5b7af962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86b6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86b6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86b6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86b6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5b7a8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5b7a8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5b7a738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5b7722e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5b7722b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86b6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86b6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86b6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5b7722a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (2475 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vs
# | ...
# `---data was truncated (10240/32206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602447c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602447bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602447c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d97333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d9738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d97333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d9731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560244758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560244758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056024473d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602443ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602443ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d9731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d9731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d9731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602443eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (2476 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_
# | ...
# `---data was truncated (10240/11895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f54a61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f54a5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f54a6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe68961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6896725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe68961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe689603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f549f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f549f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f549dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f5468be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f5468bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe689604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6896050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6896050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f5468ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (2477 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a95c41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a95c3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a95c4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6578333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f657838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6578333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f657831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a95bd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a95bd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a95bbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a9586be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a9586bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f657831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f657831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f657831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a9586ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (2478 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/170497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3903edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3903eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3903ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f751a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f751a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f751a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f751a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f390383bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f390383a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3903688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f390017e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f390017b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f751a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f751a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f751a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f390017a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (2479 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nounwind }
# | attributes #2 = { nounwind memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055572efe7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055572efe4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055572efe862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ca6105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ca615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ca6105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ca60ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055572ef7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055572ef7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055572ef628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055572ec11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055572ec11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ca60eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ca60ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ca60ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055572ec11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (2480 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c5e89eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c5e89be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c5e89f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a5fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a5faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a5fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a5fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c5e834bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c5e834a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c5e8198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c5e4c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c5e4c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a5fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a5fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a5fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c5e4c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (2481 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b253fb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b253fb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b253fb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f04449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f044a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f04449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f04431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b253f4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b253f4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b253f338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b253be2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b253be2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f04432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f044330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f044330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b253be2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (2482 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056198c520eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056198c51de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056198c52162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c6721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c672725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c6721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c67203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056198c4b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056198c4b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056198c49b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056198c14ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056198c14ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c67204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c672050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c672050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056198c14aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (2483 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b54b9f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b54b9f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b54b9f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d64249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d642a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d64249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d64231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b54b989bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b54b989a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b54b96e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b54b61de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b54b61db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d64232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d642330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d642330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b54b61da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (2484 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | 
# | ...
# `---data was truncated (10240/12652) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5de4e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5de4dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5de4e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc11a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc11a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc11a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc11a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5de476bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5de476a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5de45b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5de10ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5de10ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc11a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc11a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc11a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5de10aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (2485 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6e3b04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6e3b01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6e3b0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef09333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef0938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef09333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef0931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6e3a9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6e3a9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6e3a7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6e372ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6e372eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef0931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef0931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef0931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6e372ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (2486 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e6a5e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e6a5e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e6a5e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24b3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24b375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24b3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24b36ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e6a57cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e6a57ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e6a5618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e6a210e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e6a210b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24b36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24b36ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24b36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e6a210a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (2487 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607e5b30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607e5b2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607e5b3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f982ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f982aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f982ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f982ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e5ac6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607e5ac6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607e5aab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607e575ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607e575ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f982ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f982ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f982ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e575aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (2488 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d43a551eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d43a54ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d43a55262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f49505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f4955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f49505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f494ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d43a4e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d43a4e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d43a4cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d43a17be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d43a17bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f494eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f494ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f494ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d43a17ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (2489 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2
# | ...
# `---data was truncated (10240/32198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562829cb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562829cb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562829cba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50f7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50f7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50f7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50f7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562829c4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562829c4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562829c348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628298e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628298e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50f7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50f7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50f7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628298e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (2490 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd097f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd097f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd097f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1372533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f137258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1372533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f137251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd09789bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd09789a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd0976e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd0941de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd0941db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f137251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f137251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f137251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd0941da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (2491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560216ffeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560216ffbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560216fff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe90a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe90a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe90a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe90a4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560216f94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560216f94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560216f798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560216c28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560216c28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe90a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe90a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe90a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560216c28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (2492 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056549f944eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056549f941e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056549f94562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4720933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f472098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4720933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f472091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056549f8dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056549f8daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056549f8bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056549f56ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056549f56eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f472091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f472091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f472091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056549f56ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (2493 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566a07f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566a07f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566a07f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0edf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0edf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0edf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0edf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566a078bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566a078ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566a07708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566a041fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566a041fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0edf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0edf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0edf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566a041fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (2494 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dc8565eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dc8562e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dc856662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55c8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55c818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55c8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55c811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dc84fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dc84fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dc84e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557dc818fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557dc818fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55c811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55c811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55c811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dc818fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (2495 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2d496feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2d496ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2d497062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3af049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3af0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3af049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3af031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2d4905bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2d4905a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2d48ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2d4599e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2d4599b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3af032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3af0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3af0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2d4599a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (2496 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d01c97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d01c94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d01c9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25ea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25ea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25ea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25ea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d01c2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d01c2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d01c128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d018c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d018c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25ea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25ea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25ea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d018c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (2497 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# | 
# | ...
# `---data was truncated (10240/26460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afd4847eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afd4844e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afd484862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c4b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c4b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c4b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c4b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afd47ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afd47dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afd47c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afd4471e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afd4471b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c4b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c4b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c4b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afd4471a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (2498 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056519622beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565196228e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056519622c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a4b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a4b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a4b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a4b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651961c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651961c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651961a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565195e55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565195e55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a4b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a4b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a4b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565195e55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (2499 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e43660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e4365de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e4366162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fa4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fa4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fa4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fa4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e435f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e435f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e435db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e4328ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e4328ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fa4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fa4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fa4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e4328aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (2500 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611ed685eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611ed682e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611ed68662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc66dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc66dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc66dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc66dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611ed61bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611ed61ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611ed6008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611ed2afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611ed2afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc66dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc66dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc66dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611ed2afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (2501 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<
# | ...
# `---data was truncated (10240/11404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d25edceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d25ed9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d25edd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48dda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d25e72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d25e72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d25e578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d25b06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d25b06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48dda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d25b06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (2502 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscal
# | ...
# `---data was truncated (10240/26704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d0548deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d0548ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d0548e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d8df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d8df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d8df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d8deed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d05423bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d05423a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d054088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d050b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d050b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d8deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d8deef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d8deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d050b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (2503 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/11938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559090cfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559090cf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559090cfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbfda1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbfda725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbfda1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbfda03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559090c92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559090c92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559090c778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559090926e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559090926b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbfda04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbfda050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbfda050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559090926a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (2504 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c83d78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c83d75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c83d7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30c4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30c4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30c4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30c4e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c83d0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c83d0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c83cf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c839a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c839a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30c4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30c4e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30c4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c839a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (2505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x 
# | ...
# `---data was truncated (10240/292007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560e6c3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560e6c3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560e6c4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0363849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03638a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0363849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0363831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560e6bd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560e6bd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560e6bba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560e6869e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560e6869b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0363832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03638330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03638330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560e6869a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (2506 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b93c31aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b93c317e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b93c31b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cf4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cf4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cf4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cf4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b93c2b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b93c2b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b93c2958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b93bf44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b93bf44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cf4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cf4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cf4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b93bf44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (2507 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd44e03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd44e00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd44e0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c46333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c4638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c46333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c4631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd44d99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd44d99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd44d7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd44a2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd44a2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c4631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c4631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c4631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd44a2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (2508 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fddcf5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fddcf2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fddcf662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fded1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fded178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fded1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fded171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fddc8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fddc8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fddc708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fdd91fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fdd91fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fded171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fded171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fded171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fdd91fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (2509 of 27910)
******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20       -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone       | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.MyTask = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { ptr }
# | %"struct.std::suspend_always" = type { i8 }
# | %struct.Awaiter = type { ptr }
# | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" }
# | 
# | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15await_transformERKi = comdat any
# | 
# | $_ZN7Awaiter11await_readyEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any
# | 
# | $_ZN7Awaiter12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type13final_suspendEv = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | @g_array = global [32 x i32] zeroinitializer, align 16
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local ptr @_Z6FooBarv() #0 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6
# |   store ptr @_Z6FooBarv.resume, ptr %call, align 8
# |   %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup
# |   %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8
# |   store ptr %0, ptr %destroy.addr, align 8
# |   %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18
# |   %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24
# |   %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32
# |   %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40
# |   %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48
# |   %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56
# |   %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19
# |   %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16
# |   %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call1, ptr %coerce.dive2, align 8
# |   call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   br i1 %call3, label %init.ready, label %CoroSave
# | 
# | CoroSave:                                         ; preds = %entry
# |   %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 0, ptr %index.addr39, align 1
# |   call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | init.ready:                                       ; preds = %entry
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   store ptr @g_array, ptr %__range1.reload.addr, align 8
# |   store ptr @g_array, ptr %__begin1.reload.addr, align 8
# |   store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %init.ready
# |   %1 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %2 = load ptr, ptr %__end1.reload.addr, align 8
# |   %cmp = icmp ne ptr %1, %2
# |   br i1 %cmp, label %for.body, label %coro.final
# | 
# | for.body:                                         ; preds = %for.cond
# |   %3 = load ptr, ptr %__begin1.reload.addr, align 8
# |   store ptr %3, ptr %x.reload.addr, align 8
# |   %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2
# |   %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4)
# |   %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0
# |   store ptr %call5, ptr %coerce.dive6, align 8
# |   %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   br i1 %call7, label %await.ready, label %CoroSave27
# | 
# | CoroSave27:                                       ; preds = %for.body
# |   %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 1, ptr %index.addr40, align 1
# |   %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call)
# |   %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0
# |   %7 = load ptr, ptr %6, align 8
# |   call void %7(ptr %5)
# |   br label %AfterCoroEnd
# | 
# | await.ready:                                      ; preds = %for.body
# |   call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   %cond = icmp eq i32 0, 0
# |   %cond26 = icmp eq i32 0, 0
# |   br i1 %cond26, label %for.inc, label %coro.final
# | 
# | for.inc:                                          ; preds = %await.ready
# |   %8 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1
# |   store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8
# |   br label %for.cond
# | 
# | coro.final:                                       ; preds = %await.ready, %for.cond
# |   call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7
# |   %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   br i1 %call20, label %final.ready, label %CoroSave31
# | 
# | CoroSave31:                                       ; preds = %coro.final
# |   store ptr null, ptr %call, align 8
# |   call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | final.ready:                                      ; preds = %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   %9 = icmp ne ptr %call, null
# |   br i1 %9, label %coro.free, label %AfterCoroEnd
# | 
# | coro.free:                                        ; preds = %final.ready
# |   call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7
# |   br label %AfterCoroEnd
# | 
# | AfterCoroEnd:                                     ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave
# |   %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0
# |   %10 = load ptr, ptr %coerce.dive25, align 8
# |   ret ptr %10
# | }
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %this.addr = alloca ptr, align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call, ptr %coerce.dive2, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false)
# |   %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0
# |   %0 = load ptr, ptr %coerce.dive4, align 8
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret i1 false
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 {
# | entry:
# |   %.addr = alloca ptr, align 8
# |   %.addr1 = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %0, ptr %.addr, align 8
# |   store ptr %1, ptr %.addr1, align 8
# |   %2 = load ptr, ptr %.addr, align 8
# |   %3 = load ptr, ptr %.addr1, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7
# |   
# | ...
# `---data was truncated (10240/37953) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# |  #0 0x0000555ddd5afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ddd5ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ddd5b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b66249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b662a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b66249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b66231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ddd545bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ddd545a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ddd52a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ddd1d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ddd1d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b66232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b662330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b662330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ddd1d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (2510 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p2.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %retval = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %c = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   %coerce4 = alloca <4 x half>, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b1 = load <4 x half>, ptr %b, align 8
# |   store <2 x i32> %c.coerce, ptr %c, align 8
# |   %c2 = load <4 x half>, ptr %c, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b1, ptr %b.addr, align 8
# |   store <4 x half> %c2, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %1, ptr %coerce, align 8
# |   %3 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %2, ptr %coerce3, align 8
# |   %4 = load <2 x i32>, ptr %coerce3, align 8
# |   store <2 x i32> %3, ptr %__p1.i, align 8
# |   %__p11.i = load <4 x half>, ptr %__p1.i, align 8
# |   store <2 x i32> %4, ptr %__p2.i, align 8
# |   %__p22.i = load <4 x half>, ptr %__p2.i, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8
# |   store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %7 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %9, ptr %retval.i, align 8
# |   %10 = load <2 x i32>, ptr %retval.i, align 8
# |   store <2 x i32> %10, ptr %coerce4, align 8
# |   %11 = load <4 x half>, ptr %coerce4, align 8
# |   store <4 x half> %11, ptr %retval, align 8
# |   %12 = load <2 x i32>, ptr %retval, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p2.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %retval = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %c = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   %coerce4 = alloca <8 x half>, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b1 = load <8 x half>, ptr %b, align 16
# |   store <4 x i32> %c.coerce, ptr %c, align 16
# |   %c2 = load <8 x half>, ptr %c, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b1, ptr %b.addr, align 16
# |   store <8 x half> %c2, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %1, ptr %coerce, align 16
# |   %3 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %2, ptr %coerce3, align 16
# |   %4 = load <4 x i32>, ptr %coerce3, align 16
# |   store <4 x i32> %3, ptr %__p1.i, align 16
# |   %__p11.i = load <8 x half>, ptr %__p1.i, align 16
# |   store <4 x i32> %4, ptr %__p2.i, align 16
# |   %__p22.i = load <8 x half>, ptr %__p2.i, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16
# |   store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %7 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7)
# |   store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %9, ptr %retval.i, align 16
# |   %10 = load <4 x i32>, ptr %retval.i, align 16
# |   store <4 x i32> %10, ptr %coerce4, align 16
# |   %11 = load <8 x half>, ptr %coerce4, align 16
# |   store <8 x half> %11, ptr %retval, align 16
# |   %12 = load <4 x i32>, ptr %retval, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %a = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   store <2 x i32> %a.coerce, ptr %a, align 8
# |   %a1 = load <4 x half>, ptr %a, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b2 = load <4 x half>, ptr %b, align 8
# |   store <4 x half> %a1, ptr %a.addr, align 8
# |   store <4 x half> %b2, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %coerce, align 8
# |   %2 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %1, ptr %coerce3, align 8
# |   %3 = load <2 x i32>, ptr %coerce3, align 8
# |   call void @llvm.experimental.noalias.scope.decl(metadata !3)
# |   store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3
# |   %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3
# |   store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3
# |   %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3
# |   store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3
# |   store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3
# |   %6 = bitcast <8 x i8> %4 to <4 x i16>
# |   %7 = bitcast <8 x i8> %5 to <4 x i16>
# |   %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3
# |   %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %a = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   store <4 x i32> %a.coerce, ptr %a, align 16
# |   %a1 = load <8 x half>, ptr %a, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b2 = load <8 x half>, ptr %b, align 16
# |   store <8 x half> %a1, ptr %a.addr, align 16
# |   store <8 x half> %b2, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %coerce, align 16
# |   %2 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %1, ptr %coerce3, align 16
# |   %3 = load <4 x i32>, ptr %coerce3, align 16
# |   call void @llvm.experimental.noalias.scope.decl(metadata !6)
# |   store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6
# |   %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6
# |   store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6
# |   %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6
# |   store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6
# |   store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6
# |   %6 = bitcast <16 x i8> %4 to <8 x i16>
# |   %7 = bitcast <16 x i8> %5 to <8 x i16>
# |   %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6
# |   %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef
# | ...
# `---data was truncated (10240/35874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055defe85feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055defe85ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055defe86062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fd9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fd9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fd9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fd9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055defe7f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055defe7f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055defe7da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055defe489e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055defe489b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fd9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fd9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fd9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055defe489a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (2511 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055693ae15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055693ae12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055693ae1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f547e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f547e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f547e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f547e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055693adabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055693adaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055693ad908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055693aa3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055693aa3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f547e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f547e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f547e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055693aa3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (2512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056053de6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056053de67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056053de6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb78705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb7875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb78705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb786ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056053de00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056053de00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056053dde58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056053da94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056053da94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb786eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb786ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb786ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056053da94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (2513 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc13424eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc13421e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc1342562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46ec449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46ec4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46ec449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46ec431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc133babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc133baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc1339f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc1304ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc1304eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46ec432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46ec4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46ec4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc1304ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (2514 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560813fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560813f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560813fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5900e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5900ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5900e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5900e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556081392bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556081392a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560813778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556081026e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556081026b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5900e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5900e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5900e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556081026a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/builtin-align.c (2515 of 27910)
******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR    -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR    -enable-var-scope '-D$PTRTYPE=i8'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | @aligned_true = global i8 1, align 1
# | @aligned_false = global i8 0, align 1
# | @down_1 = global i32 992, align 4
# | @down_2 = global i32 256, align 4
# | @up_1 = global i32 1024, align 4
# | @up_2 = global i32 256, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @get_type() #0 {
# | entry:
# |   ret ptr null
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %src_addr = ptrtoint ptr %0 to i64
# |   %set_bits = and i64 %src_addr, %mask
# |   %is_aligned = icmp eq i64 %set_bits, 0
# |   ret i1 %is_aligned
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056275b2f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056275b2f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056275b2f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd47c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd47ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd47c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd47c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056275b28bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056275b28ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056275b2708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056275af1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056275af1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd47c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd47c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd47c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056275af1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (2516 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = al
# | ...
# `---data was truncated (10240/41670) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a87eceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a87ecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a87ecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb077649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0776a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb077649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb077631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a87e64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a87e64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a87e498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a87af8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a87af8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb077632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0776330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0776330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a87af8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (2517 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055964dbf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055964dbf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055964dbf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff296b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff296b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff296b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff296b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055964db8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055964db8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055964db738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055964d822e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055964d822b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff296b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff296b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff296b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055964d822a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (2518 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a920243eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a920240e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a92024462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f495b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f495b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f495b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f495b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9201d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9201d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9201be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a91fe6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a91fe6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f495b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f495b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f495b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a91fe6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (2519 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.
# | ...
# `---data was truncated (10240/15486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562018265eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562018262e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056201826662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0e8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0e898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0e8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0e891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620181fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620181fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620181e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562017e8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562017e8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0e891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0e891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0e891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562017e8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (2520 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7be667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7be664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7be66862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bd1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bd158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bd1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bd151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7be5fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7be5fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7be5e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7be291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7be291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bd151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bd151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bd151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7be291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (2521 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609f0608eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609f0605e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609f060962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4c7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609f059ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609f059ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609f05838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609f0232e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609f0232b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4c72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609f0232a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (2522 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aeadc19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aeadc16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aeadc1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff495133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff49518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff495133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff49511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aeadbafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aeadbafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aeadb948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aead843e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aead843b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff49511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff49511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff49511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aead843a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (2523 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e294dbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e294dbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e294dbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d3f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d3f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d3f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d3f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e294d53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e294d53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e294d388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2949e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2949e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d3f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d3f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d3f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2949e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (2524 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d5dbabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d5dba8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d5dbac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedf9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedf9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedf9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedf9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d5db41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d5db41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d5db268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d5d7d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d5d7d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedf9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedf9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedf9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d5d7d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (2525 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636abadbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636abad8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636abadc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff615333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff61538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff615333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff61531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636aba71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636aba71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636aba568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636ab705e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636ab705b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff61531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff61531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff61531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636ab705a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (2526 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055573c512eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055573c50fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055573c51362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac53933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac5398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac53933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac5391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055573c4a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055573c4a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055573c48d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055573c13ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055573c13cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac5391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac5391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac5391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055573c13ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (2527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fff0a22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fff0a1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fff0a2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28fd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28fd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28fd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28fd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fff09b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fff09b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fff099d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fff064ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fff064cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28fd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28fd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28fd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fff064ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (2528 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/95437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056118c707eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056118c704e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056118c70862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3a9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3a90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3a9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3a9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056118c69dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056118c69da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056118c6828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056118c331e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056118c331b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3a9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3a90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3a90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056118c331a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (2529 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ...
# `---data was truncated (10240/14904) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3b77bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3b77bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3b77c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb720c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb720ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb720c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb720c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3b7755bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3b7755a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3b773a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3b73e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3b73e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb720c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb720c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb720c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3b73e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (2530 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055639d7b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055639d7b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055639d7b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0962933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f096298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0962933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f096291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055639d74bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055639d74ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055639d7308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055639d3dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055639d3dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f096291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f096291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f096291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055639d3dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (2531 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e4834ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e48349e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e4834d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7756c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7756ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7756c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7756c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e482e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e482e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e482c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e47f76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e47f76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7756c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7756c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7756c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e47f76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (2532 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056504ba39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056504ba36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056504ba3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98fb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98fb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98fb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98fb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056504b9cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056504b9cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056504b9b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056504b663e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056504b663b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98fb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98fb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98fb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056504b663a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (2533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619ed46ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619ed469e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619ed46d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94ff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94ff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94ff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94ff51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619ed402bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619ed402a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619ed3e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619ed096e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619ed096b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94ff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94ff51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94ff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619ed096a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (2534 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b149f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b149f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b149f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa164849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1648a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa164849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa164831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b1498ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b1498ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b149738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b14622e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b14622b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa164832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1648330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1648330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b14622a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (2535 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c0540deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c0540ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c0540e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f171b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f171b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f171b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f171b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c053a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c053a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c053888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c05037e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c05037b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f171b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f171b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f171b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c05037a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (2536 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e6f979eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e6f976e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e6f97a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe169333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe16938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe169333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe16931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e6f90fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e6f90fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e6f8f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e6f5a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e6f5a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe16931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe16931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe16931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e6f5a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (2537 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf81127eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf81124e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf8112862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4918d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4918d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4918d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4918d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf810bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf810bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf810a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf80d51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf80d51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4918d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4918d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4918d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf80d51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (2538 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ef98feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ef98fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ef98ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4324d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4324d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4324d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4324d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ef9894bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ef9894a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ef98798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ef9528e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ef9528b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4324d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4324d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4324d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ef9528a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (2539 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d69c30feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d69c30ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d69c31062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f481f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f481f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f481f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f481f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d69c2a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d69c2a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d69c28a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d69bf39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d69bf39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f481f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f481f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f481f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d69bf39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (2540 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e2e694eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e2e691e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e2e69562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dd6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dd678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dd6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dd671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e2e62abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e2e62aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e2e60f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e2e2bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e2e2beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0dd671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dd671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dd671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e2e2bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (2541 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e88baceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e88ba9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e88bad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3e2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3e2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3e2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3e2c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e88b42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e88b42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e88b278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e887d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e887d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3e2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3e2c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3e2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e887d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (2542 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b36fc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b36fbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b36fc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc951449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9514a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc951449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc951431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b36f57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b36f57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b36f3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b36bebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b36bebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc951432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9514330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9514330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b36beba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (2543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5d7712eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5d770fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5d771362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaa1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaa1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaa1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaa1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5d76a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5d76a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5d768d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5d733ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5d733cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaa1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaa1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaa1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5d733ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (2544 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570cbd9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570cbd9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570cbda062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4631333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f463138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4631333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f463131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570cbd35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570cbd35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570cbd1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570cb9c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570cb9c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f463131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f463131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f463131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570cb9c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (2545 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557875ae4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557875ae1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557875ae562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6193849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61938a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6193849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6193831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557875a7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557875a7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557875a5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055787570ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055787570eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6193832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61938330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61938330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055787570ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (2546 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ca48e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ca48e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ca48e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab86a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab86aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab86a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab86a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ca487ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ca487ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ca48638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ca4512e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ca4512b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab86a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab86a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab86a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ca4512a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (2547 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i6
# | ...
# `---data was truncated (10240/56171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600aecb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600aecb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600aecb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fbad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fbad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fbad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fbad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600aec4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600aec4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600aec318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600ae8e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600ae8e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fbad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fbad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fbad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600ae8e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (2548 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_viota_m_u16m4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_viota_m_u16m8(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/40411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5ac14beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5ac148e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5ac14c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee2fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee2fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee2fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5ac0e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5ac0e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5ac0c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5abd75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5abd75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee2fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee2fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee2fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5abd75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (2549 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056280dc97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056280dc94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056280dc9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb97849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb97849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb97831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056280dc2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056280dc2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056280dc128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056280d8c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056280d8c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb97832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb978330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056280d8c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (2550 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c8c27eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c8c27be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c8c27f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9dc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9dc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9dc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9dc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c8c214bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c8c214a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c8c1f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c8bea8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c8bea8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9dc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9dc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9dc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c8bea8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (2551 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define 
# | ...
# `---data was truncated (10240/18595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7e6644eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7e6641e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7e664562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d38305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d3835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d38305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d382ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7e65dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7e65daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7e65bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7e626ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7e626eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d382eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d382ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d382ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7e626ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (2552 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638fa593eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638fa590e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638fa59462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc849d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc849d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc849d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc849d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638fa529bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638fa529a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638fa50e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638fa1bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638fa1bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc849d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc849d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc849d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638fa1bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (2553 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561325763eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561325760e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056132576462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bb5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bb595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bb5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bb58ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613256f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613256f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613256de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056132538de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056132538db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bb58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bb58ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bb58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056132538da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (2554 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/205813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555dd0ba5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555dd0ba2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555dd0ba662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6df249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6df2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6df249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6df231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dd0b3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555dd0b3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555dd0b208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555dd07cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555dd07cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6df232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6df2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6df2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dd07cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (2555 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055630a32ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055630a329e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055630a32d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe342933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe34298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe342933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe34291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055630a2c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055630a2c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055630a2a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556309f56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556309f56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe34291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe34291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe34291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556309f56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (2556 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056086be4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056086be47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056086be4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2929933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f292998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2929933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f292991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056086bde0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056086bde0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056086bdc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056086ba74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056086ba74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f292991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f292991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f292991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056086ba74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (2557 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555849ecdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555849ecae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555849ece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8636933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f863698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8636933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f863691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555849e63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555849e63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555849e488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555849af7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555849af7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f863691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f863691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f863691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555849af7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2558 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056090af24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056090af21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056090af2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99e5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99e5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99e5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99e5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056090aebabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056090aebaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056090ae9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056090ab4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056090ab4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99e5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99e5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99e5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056090ab4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (2559 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556579bffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556579bfce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556579c0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cfde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cfdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cfde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cfde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556579b95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556579b95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556579b7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556579829e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556579829b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cfde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cfde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cfde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556579829a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (2560 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b71239eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b71236e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b7123a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3d6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3d6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3d6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3d6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b711cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b711cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b711b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b70e63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b70e63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3d6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3d6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3d6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b70e63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (2561 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e11f7dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e11f7dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e11f7e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9c8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9c8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9c8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9c8ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e11f775bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e11f775a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e11f75a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e11f409e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e11f409b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9c8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9c8cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9c8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e11f409a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (2562 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr
# | ...
# `---data was truncated (10240/44315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a6deef2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6deeefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6deef362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb932f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb932f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb932f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb932f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6dee88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6dee88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6dee6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6deb1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6deb1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb932f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb932f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb932f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6deb1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (2563 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4208feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4208fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4208ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f89933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f8998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f89933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f8991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f420894bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f420894a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4208798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f420528e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f420528b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f8991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f8991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f8991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f420528a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (2564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573dbeceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573dbecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573dbecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30e3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30e338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30e3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30e331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573dbe64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573dbe64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573dbe498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573dbaf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573dbaf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30e331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30e331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30e331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573dbaf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (2565 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 
# | ...
# `---data was truncated (10240/11237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575dfa01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575df9fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575dfa0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73b8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73b8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73b8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73b8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575df997bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575df997a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575df97c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575df62be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575df62bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73b8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73b8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73b8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575df62ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (2566 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local signext i32 @test() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
# |   %conv = trunc i64 %0 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640a5cc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640a5cc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640a5cca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed02249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed022a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed02249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed02231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640a5c5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640a5c5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640a5c448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640a58f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640a58f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed02232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed022330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed022330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640a58f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (2567 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de00b60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de00b5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de00b6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13d6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13d638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13d6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13d631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de00af6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de00af6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de00adb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de0078ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de0078ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13d631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13d631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13d631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de0078aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (2568 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %
# | ...
# `---data was truncated (10240/13690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e15f223eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e15f220e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e15f22462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c32649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c326a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c32649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c32631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e15f1b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e15f1b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e15f19e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e15ee4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e15ee4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c32632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c326330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c326330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e15ee4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (2569 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056004ecf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056004ecefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056004ecf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f874c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f874c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f874c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f874c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056004ec88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056004ec88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056004ec6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056004e91ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056004e91cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f874c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f874c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f874c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056004e91ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (2570 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056443518feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056443518ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056443519062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6db2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6db2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6db2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6db2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564435125bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564435125a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056443510a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564434db9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564434db9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6db2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6db2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6db2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564434db9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (2571 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d1792eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d1792be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d1792f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf4e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf4e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf4e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf4e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d178c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d178c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d178a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d17558e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d17558b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf4e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf4e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf4e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d17558a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (2572 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a919879eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a919876e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a91987a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fb3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fb3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fb3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fb3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a91980fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a91980fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9197f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9194a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9194a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fb3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fb3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fb3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9194a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (2573 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a25079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a25076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a2507a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bc4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bc478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bc4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bc471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a2500fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a2500fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a24ff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a24ca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a24ca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bc471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bc471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bc471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a24ca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (2574 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558637a8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558637a8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558637a9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc13733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc1378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc13733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc1371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558637a25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558637a25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558637a0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586376b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586376b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc1371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc1371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc1371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586376b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (2575 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555594b77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555594b74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555594b7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c82333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c8238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c82333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c8231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555594b0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555594b0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555594af28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555947a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555947a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c8231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c8231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c8231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555947a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (2576 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb258adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb258aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb258ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd183e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd183ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd183e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd183e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb25843bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb25843a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb258288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb254d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb254d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd183e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd183e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd183e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb254d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (2577 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599783f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599783f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599783fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb82c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb82ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb82c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb82c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055997838fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055997838fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599783748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559978023e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559978023b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb82c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb82c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb82c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559978023a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (2578 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bd614eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bd614be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bd614f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff01c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff01c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff01c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff01c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bd60e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bd60e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bd60c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bd5d78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bd5d78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff01c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff01c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff01c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bd5d78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (2579 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638afbeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638afbe9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638afbed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd26c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd26c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd26c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd26c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638afb82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638afb82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638afb678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638af816e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638af816b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd26c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd26c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd26c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638af816a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (2580 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16  -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_812 = alloca <4 x float>, align 16
# |   %__s0_812 = alloca <4 x float>, align 16
# |   %__s1_812 = alloca <8 x bfloat>, align 16
# |   %__s2_812 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <4 x float>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp2 = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0_812, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1_812, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <8 x bfloat> %2, ptr %__s2_812, align 16
# |   %3 = load <4 x float>, ptr %__s0_812, align 16
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 16
# |   %5 = load <4 x float>, ptr %__s2_812, align 16
# |   store <4 x float> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 16
# |   store <4 x float> %8, ptr %__ret, align 16
# |   %9 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %9, ptr %tmp, align 16
# |   %10 = load <4 x float>, ptr %tmp, align 16
# |   store <4 x float> %10, ptr %ref.tmp, align 16
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %15, ptr %__ret.i, align 16
# |   %16 = load <4 x float>, ptr %__ret.i, align 16
# |   store <4 x float> %16, ptr %__ret_812, align 16
# |   %17 = load <4 x float>, ptr %__ret_812, align 16
# |   store <4 x float> %17, ptr %tmp2, align 16
# |   %18 = load <4 x float>, ptr %tmp2, align 16
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>,
# | ...
# `---data was truncated (10240/54685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005630c2719eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630c2716e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630c271a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f367fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f367fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f367fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f367fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630c26afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630c26afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630c26948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630c2343e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630c2343b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f367fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f367fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f367fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630c2343a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (2581 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559534646eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559534643e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055953464762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12ca81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12ca8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12ca81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12ca803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595345dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595345dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595345c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559534270e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559534270b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12ca804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12ca8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12ca8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559534270a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (2582 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056520539eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056520539be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056520539f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50d6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50d618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50d6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50d611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565205334bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565205334a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652053198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565204fc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565204fc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50d611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50d611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50d611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565204fc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (2583 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dd38c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559dd38bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559dd38c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1f4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1f458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1f4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1f451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dd3856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559dd3856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559dd383b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559dd34eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559dd34eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1f451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1f451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1f451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dd34eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (2584 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c10282beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c102828e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c10282c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd296133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd29618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd296133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd29611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1027c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1027c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1027a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c102455e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c102455b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd29611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd29611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd29611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c102455a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (2585 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %v
# | ...
# `---data was truncated (10240/43948) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d6fda4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d6fda1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d6fda562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe57b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe57b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe57b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe57b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d6fd3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d6fd3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d6fd1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d6f9cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d6f9ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe57b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe57b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe57b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d6f9cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (2586 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp uge <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp uge <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp uge <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055683bde9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055683bde6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055683bdea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d79733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d7978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d79733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d7971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055683bd7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055683bd7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055683bd648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055683ba13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055683ba13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d7971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d7971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d7971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055683ba13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (2587 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f77889eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f77886e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f7788a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b59933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b5998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b59933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b5991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f7781fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f7781fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f778048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f774b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f774b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b5991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b5991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b5991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f774b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (2588 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571d8ab4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571d8ab1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571d8ab562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc40fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc40fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc40fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc40faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571d8a4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571d8a4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571d8a2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571d86dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571d86deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc40faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc40faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc40faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571d86dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (2589 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f7bae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f7bae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f7bae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa44a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa44a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa44a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa44a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f7ba79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f7ba79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f7ba5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f7b70de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f7b70db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa44a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa44a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa44a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f7b70da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (2590 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/246614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646c9866eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646c9863e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646c986762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe195133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe19518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe195133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe19511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646c97fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646c97fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646c97e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646c9490e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646c9490b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe19511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe19511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe19511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646c9490a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (2591 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f
# | ...
# `---data was truncated (10240/165246) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055940d02beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055940d028e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055940d02c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4402133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f440218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4402133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f440211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055940cfc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055940cfc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055940cfa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055940cc55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055940cc55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f440211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f440211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f440211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055940cc55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (2592 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i3
# | ...
# `---data was truncated (10240/57708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f130446eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f130443e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f13044762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2106a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2106aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2106a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2106a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1303dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1303dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1303c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f130070e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f130070b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2106a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2106a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2106a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f130070a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (2593 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056343f8c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056343f8c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056343f8c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7ba449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7ba4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7ba449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7ba431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056343f85abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056343f85aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056343f83f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056343f4eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056343f4eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7ba432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7ba4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7ba4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056343f4eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (2594 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e994d92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e994d8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e994d9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f347fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f347fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f347fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f347fe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e994d28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e994d28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e994d0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9949bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9949bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f347fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f347fe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f347fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9949bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (2595 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055876b49feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055876b49ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055876b4a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaa4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaa46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaa4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaa4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055876b435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055876b435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055876b41a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055876b0c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055876b0c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaa4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaa46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaa46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055876b0c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (2596 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559759aa8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559759aa5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559759aa962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff870c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff870ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff870c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff870c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559759a3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559759a3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559759a238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597596d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597596d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff870c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff870c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff870c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597596d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (2597 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c60d46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c60d43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c60d4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4458249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4458249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4458231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c60cdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c60cdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c60cc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c60970e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c60970b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4458232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44582330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c60970a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (2598 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a48312eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a4830fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a4831362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc57ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc57eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc57ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc57ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a482a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a482a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a4828d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a47f3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a47f3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc57ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc57ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc57ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a47f3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (2599 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567a7f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567a7f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567a7f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84fd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84fd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84fd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84fd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567a7f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567a7f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567a7ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567a7ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567a7ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84fd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84fd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84fd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567a7ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (2600 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623f8e01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623f8dfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623f8e0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa838305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa83835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa838305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8382ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623f8d97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623f8d97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623f8d7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623f8a2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623f8a2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8382eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8382ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8382ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623f8a2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/builtins-arm64.c (2601 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load ptr, ptr %b.addr, align 8
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @tp() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbitl(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.bitreverse.i64(i64) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbit64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @hints() #0 {
# | entry:
# |   call void @llvm.aarch64.hint(i32 0)
# |   call void @llvm.aarch64.hint(i32 1)
# |   call void @llvm.aarch64.hint(i32 2)
# |   call void @llvm.aarch64.hint(i32 3)
# |   call void @llvm.aarch64.hint(i32 4)
# |   call void @llvm.aarch64.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.aarch64.hint(i32) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @barriers() #0 {
# | entry:
# |   call void @llvm.aarch64.dmb(i32 1)
# |   call void @llvm.aarch64.dsb(i32 2)
# |   call void @llvm.aarch64.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dmb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dsb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.isb(i32) #5
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch_x() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @read_intent_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch.ir(ptr null)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @jcvt(double noundef %v) #7 {
# | entry:
# |   %v.addr = alloca double, align 8
# |   store double %v, ptr %v.addr, align 8
# |   %0 = load double, ptr %v.addr, align 8
# |   %1 = call i32 @llvm.aarch64.fjcvtzs(double %0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.fjcvtzs(double) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rsr() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = trunc i64 %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i64 @llvm.read_volatile_register.i64(metadata) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rsr64() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @rsrp() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = inttoptr i64 %0 to ptr
# |   ret ptr %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %1 = zext i32 %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nounwind
# | declare void @llvm.write_register.i64(metadata, i64) #8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr64(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   call void @llvm.write_register.i64(metadata !7, i64 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsrp(ptr noundef %v) #0 {
# | entry:
# |   %v.addr = alloca ptr, align 8
# |   store ptr %v, ptr %v.addr, align 8
# |   %0 = load ptr, ptr %v.addr, align 8
# |   %1 = ptrtoint ptr %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cls(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %cls = call i32 @llvm.aarch64.cls(i32 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsl(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls64(i64) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsll(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndr(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndr()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndr() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndrrs()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndrrs() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @trap() #0 {
# | entry:
# |   call void @llvm.aarch64.break(i32 42)
# |   ret void
# | }
# | 
# | ; Function Attrs: cold noreturn nounwind
# | declare void @llvm.aarch64.break(i32 immarg) #10
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca i64, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8
# |   %2 = load ptr, ptr %a.addr, align 8
# |   %3 = load i64, ptr %b.addr, a
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   243 |   __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint
# |       |   ^                                                            ~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type]
# |   305 |   __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type]
# |   306 |   __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type]
# |   307 |   __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH);
# |       |   ^                                                                ~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   308 |   return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5);
# |       |          ^                                                                ~
# | 5 warnings generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e16775eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e16772e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e1677662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ac2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ac2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ac2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ac2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e1670bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e1670ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e166f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e1639fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e1639fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ac2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ac2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ac2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e1639fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (2602 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a75d30beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a75d308e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a75d30c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5831733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f583178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5831733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f583171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a75d2a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a75d2a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a75d2868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a75cf35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a75cf35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f583171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f583171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f583171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a75cf35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (2603 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641c4948eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641c4945e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641c494962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccb4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccb478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccb4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccb471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641c48debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641c48dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641c48c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641c4572e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641c4572b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccb471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccb471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccb471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641c4572a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (2604 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd1ee06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd1ee03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd1ee0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbec2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbec2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbec2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbec2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd1ed9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd1ed9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd1ed818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd1ea30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd1ea30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbec2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbec2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbec2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd1ea30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (2605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604560e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604560dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604560e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15ee81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15ee8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15ee81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15ee803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560456077bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560456077a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056045605c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560455d0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560455d0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15ee804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15ee8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15ee8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560455d0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (2606 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581a3348eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581a3345e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581a334962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc40d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc40d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc40d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc40ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581a32debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581a32dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581a32c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581a2f72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581a2f72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc40ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc40cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc40cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581a2f72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (2607 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565045ea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565045e9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565045ea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f991c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f991c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f991c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f991c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565045e37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565045e37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565045e1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565045acbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565045acbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f991c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f991c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f991c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565045acba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (2608 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c6ad3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c6ad3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c6ad3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dee71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c6acd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c6acd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c6acb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c6a967e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c6a967b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dee71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c6a967a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (2609 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561357dbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561357db8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561357dbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b60b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b60b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b60b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b60b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561357d51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561357d51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561357d368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613579e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613579e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b60b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b60b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b60b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613579e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (2610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/18873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f509a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f509a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f509a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca17649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca176a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca17649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca17631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f5093ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f5093ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f509238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f505d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f505d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca17632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca176330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca176330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f505d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (2611 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b090603eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b090600e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b09060462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9208f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9208f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9208f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9208f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b090599bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b090599a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b09057e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b09022de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b09022db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9208f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9208f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9208f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b09022da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (2612 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a58566eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a58563e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a5856762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3cc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3cc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3cc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3cc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a584fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a584fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a584e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a58190e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a58190b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3cc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3cc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3cc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a58190a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (2613 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c61920eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c61920be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c61920f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aa4305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aa435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aa4305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aa42ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6191a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6191a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6191898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c618e38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c618e38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0aa42eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aa42ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aa42ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c618e38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (2614 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562c4715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562c4712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562c471662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feedff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feedff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feedff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feedfeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562c46abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562c46aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562c46908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562c433fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562c433fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feedfeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feedfeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feedfeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562c433fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (2615 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de1f8a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de1f8a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de1f8a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f767d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f767d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f767d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f767d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de1f83bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de1f83ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de1f8208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de1f4cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de1f4cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f767d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f767d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f767d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de1f4cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (2616 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563737ad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563737ad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563737ada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2aea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2aeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2aea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2aea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563737a6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563737a6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563737a548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563737703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563737703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2aea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2aea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2aea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563737703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (2617 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6d66f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6d66f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6d66f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06f4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06f4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06f4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06f4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6d668cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6d668ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6d66718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6d6320e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6d6320b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06f4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06f4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06f4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6d6320a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (2618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561230eb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561230eb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561230eb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6de9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6de958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6de9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6de951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561230e4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561230e4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561230e308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561230adfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561230adfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6de951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6de951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6de951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561230adfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (2619 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561d01e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561d01e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561d01ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14d4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14d4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14d4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14d4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561d017fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561d017fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561d01648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561cfe13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561cfe13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14d4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14d4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14d4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561cfe13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (2620 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota
# | ...
# `---data was truncated (10240/94681) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056070a9dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056070a9d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056070a9dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb0f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb0f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb0f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb0f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056070a972bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056070a972a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056070a9578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056070a606e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056070a606b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb0f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb0f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb0f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056070a606a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (2621 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570e171feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570e171ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570e172062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9e9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9e9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9e9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9e9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570e16b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570e16b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570e169a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570e1349e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570e1349b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9e9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9e9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9e9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570e1349a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (2622 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef
# | ...
# `---data was truncated (10240/14333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b79a5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b79a5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b79a6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd650133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd65018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd650133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd65011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b799f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b799f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b799da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b79689e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b79689b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd65011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd65011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd65011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b79689a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (2623 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603277b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603277b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603277b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac13049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac130a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac13049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac13031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056032774cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056032774ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603277318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603273e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603273e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac13032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac130330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac130330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603273e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (2624 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcc8e57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcc8e54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcc8e5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78b0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78b038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78b0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78b031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcc8dedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcc8deda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcc8dd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcc8a81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcc8a81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78b031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78b031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78b031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcc8a81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (2625 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %m
# | ...
# `---data was truncated (10240/41661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bdc609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bdc606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bdc60a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effc0c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effc0c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effc0c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effc0c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bdc59fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bdc59fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bdc5848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bdc233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bdc233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effc0c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effc0c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effc0c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bdc233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (2626 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2b6135eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2b6132e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2b613662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa420449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa420449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa420431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2b60cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2b60cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2b60b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2b5d5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2b5d5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa420432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2b5d5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (2627 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8bddb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8bddade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8bddb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa37ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa37ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa37ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa37ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8bdd46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8bdd46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8bdd2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8bd9dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8bd9dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa37ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa37ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa37ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8bd9daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (2628 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567b5f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567b5f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567b5f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cfcc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cfcc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cfcc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cfcc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567b5f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567b5f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567b5ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567b5ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567b5ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cfcc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cfcc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cfcc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567b5ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (2629 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594c881deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594c881ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594c881e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b6d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b6d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b6d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b6d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594c87b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594c87b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594c87988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594c8447e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594c8447b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b6d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b6d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b6d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594c8447a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (2630 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 
# | ...
# `---data was truncated (10240/11881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564925478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564925475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056492547962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7454449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74544a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7454449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7454431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056492540ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056492540ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649253f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649250a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649250a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7454432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74544330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74544330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649250a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (2631 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i
# | ...
# `---data was truncated (10240/120468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c313424eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c313421e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c31342562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec51449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec514a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec51449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec51431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3133babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3133baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c31339f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c31304ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c31304eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec51432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec514330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec514330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c31304ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (2632 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f781720eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f78171de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f78172162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe148649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1486a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe148649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe148631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7816b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7816b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f78169b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f78134ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f78134ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe148632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1486330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1486330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f78134aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (2633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056099351aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560993517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056099351b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b41533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b4158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b41533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b4151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609934b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609934b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609934958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560993144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560993144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b4151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b4151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b4151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560993144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (2634 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i
# | ...
# `---data was truncated (10240/14644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bef0851eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bef084ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bef085262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb90333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb9038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb90333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb9031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bef07e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bef07e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bef07cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bef047be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bef047bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb9031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb9031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb9031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bef047ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (2635 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d28a07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d28a04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d28a0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb7f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb7f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb7f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb7f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d2899dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d2899da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d289828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d28631e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d28631b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb7f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb7f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb7f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d28631a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (2636 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584a1bb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584a1bb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584a1bb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb516649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5166a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb516649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb516631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584a1b4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584a1b4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584a1b338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584a17e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584a17e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb516632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5166330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5166330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584a17e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (2637 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0d8ff0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0d8fede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0d8ff162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d90d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d90d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d90d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d90d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0d8f86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0d8f86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0d8f6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0d8c1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0d8c1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d90d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d90d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d90d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0d8c1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (2638 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b197135eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b197132e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b19713662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f523bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f523bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f523bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f523bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1970cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1970cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1970b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b196d5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b196d5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f523bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f523bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f523bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b196d5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (2639 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("risc
# | ...
# `---data was truncated (10240/14659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cebe4e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cebe4e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cebe4e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf0e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf0e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf0e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf0e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cebe479bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cebe479a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cebe45e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cebe10de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cebe10db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf0e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf0e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf0e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cebe10da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (2640 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055babf1edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055babf1eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055babf1ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4753b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4753b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4753b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4753b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055babf183bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055babf183a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055babf1688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055babee17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055babee17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4753b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4753b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4753b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055babee17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (2641 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557306842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055730683fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055730684362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3760333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f376038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3760333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f376031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573067d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573067d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573067bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055730646ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055730646cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f376031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f376031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f376031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055730646ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (2642 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056020bf74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056020bf71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056020bf7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec38f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec38f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec38f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec38f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056020bf0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056020bf0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056020beef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056020bb9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056020bb9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec38f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec38f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec38f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056020bb9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (2643 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %bas
# | ...
# `---data was truncated (10240/29817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f21052eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f2104fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f2105362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f207e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f207e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f207e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f207e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f20fe8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f20fe8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f20fcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f20c7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f20c7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f207e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f207e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f207e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f20c7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (2644 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612fe126eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612fe123e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612fe12762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bed133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bed18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bed133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bed11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612fe0bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612fe0bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612fe0a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612fdd50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612fdd50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bed11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bed11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bed11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612fdd50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (2645 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056112fdb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056112fdb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056112fdb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c07f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c07f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c07f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c07eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056112fd4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056112fd4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056112fd318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056112f9e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056112f9e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c07eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c07eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c07eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056112f9e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (2646 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea2c23aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea2c237e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea2c23b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69d621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69d62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69d621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69d6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea2c1d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea2c1d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea2c1b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea2be64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea2be64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69d6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69d62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69d62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea2be64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (2647 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056067808feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056067808ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056067809062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf33533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf3358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf33533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf3351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560678025bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560678025a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056067800a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560677cb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560677cb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf3351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf3351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf3351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560677cb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (2648 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x float> @add_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x float>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %b.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store <8 x float> %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load <8 x float>, ptr %b.addr, align 8
# |   %add = fadd <8 x float> %0, %1
# |   store <8 x float> %add, ptr %retval, align 8
# |   %2 = load <8 x float>, ptr %retval,
# | ...
# `---data was truncated (10240/145303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056086e5d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056086e5d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056086e5da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86f111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056086e56fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056086e56fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056086e5548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056086e203e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056086e203b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86f111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056086e203a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (2649 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b520b6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b520b67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b520b6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b5f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b5f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b5f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b5f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b520b00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b520b00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b520ae58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b520794e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b520794b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b5f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b5f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b5f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b520794a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (2650 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb61576eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb61573e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb6157762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01ea133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01ea18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01ea133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01ea11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb6150cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb6150ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb614f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb611a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb611a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01ea11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01ea11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01ea11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb611a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (2651 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c6b2ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c6b2e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c6b2ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa62b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa62b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa62b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa62b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c6b281bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c6b281a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c6b2668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c6af15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c6af15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa62b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa62b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa62b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c6af15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (2652 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src, ptr %src.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %src.addr, align 8
# |   %1 = call <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, i32 1)
# |   ret <vscale x 4 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, <vscale x 4 x i64> %val) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %val.addr = alloca <vscale x 4 x i64>, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, ptr %dest.addr, align 8
# |   store <vscale x 4 x i64> %val, ptr %val.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %dest.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %val.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, <vscale x 4 x i64> %1, i32 1)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), <vscale x 4 x i64>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558235738eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558235735e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055823573962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb929c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb929ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb929c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb929c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582356cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582356cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582356b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558235362e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558235362b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb929c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb929c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb929c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558235362a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (2653 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562c2a7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562c2a79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562c2a7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa908f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa908f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa908f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa908f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562c2a12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562c2a12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562c29f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562c26a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562c26a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa908f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa908f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa908f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562c26a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (2654 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd456cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd456cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd456d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea7b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea7b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea7b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea7b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd45665bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd45665a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd4564a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd452f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd452f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea7b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea7b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea7b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd452f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (2655 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568eedcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568eedc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568eedcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdbb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdbb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdbb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdbb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568eed62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568eed62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568eed478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568ee9f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568ee9f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdbb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdbb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdbb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568ee9f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (2656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9a5747eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9a5744e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9a574862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2777933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f277798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2777933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f277791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9a56ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9a56dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9a56c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9a5371e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9a5371b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f277791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f277791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f277791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9a5371a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (2657 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566826c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566826bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566826c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa07ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa07aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa07ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa07ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556682657bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556682657a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055668263c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566822ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566822ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa07ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa07ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa07ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566822eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (2658 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad273e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad273dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad273e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f986f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f986f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f986f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f986f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad27377bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad27377a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad2735c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad2700be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad2700bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f986f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f986f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f986f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad2700ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (2659 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %ba
# | ...
# `---data was truncated (10240/24100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056220070feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056220070ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056220071062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff828933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff82898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff828933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff82891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622006a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622006a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056220068a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562200339e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562200339b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff82891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff82891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff82891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562200339a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (2660 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cd4cebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cd4ce8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cd4cec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7699d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7699d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7699d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7699d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cd4c81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cd4c81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cd4c668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cd4915e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cd4915b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7699d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7699d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7699d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cd4915a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (2661 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/58334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d947135eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d947132e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d94713662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f1ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f1caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f1ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f1ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9470cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9470cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9470b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d946d5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d946d5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f1ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f1ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f1ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d946d5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (2662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <v
# | ...
# `---data was truncated (10240/28691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2218c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2218c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2218c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff93e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff93e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff93e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff93e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e22185dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e22185da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2218428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2214f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2214f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff93e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff93e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff93e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2214f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (2663 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e365018eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e365015e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e36501962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7207933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f720798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7207933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f720791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e364faebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e364faea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e364f938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e364c42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e364c42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f720791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f720791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f720791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e364c42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (2664 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d62b016eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d62b013e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d62b01762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7056933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f705698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7056933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f705691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d62afacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d62afaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d62af918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d62ac40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d62ac40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f705691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f705691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f705691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d62ac40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (2665 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562117ae9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562117ae6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562117aea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f766f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f766f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f766f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f766f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562117a7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562117a7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562117a648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562117713e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562117713b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f766f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f766f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f766f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562117713a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (2666 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560367553eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560367550e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056036755462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7123b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7123b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7123b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7123aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603674e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603674e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603674ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056036717de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056036717db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7123aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7123aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7123aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056036717da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (2667 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb10895eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb10892e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb1089662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0eeeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0eeeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0eeeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0eeeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb1082bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb1082ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb108108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb104bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb104bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0eeeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0eeeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0eeeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb104bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (2668 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055598ee3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055598ee38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055598ee3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9d7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9d78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9d7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9d7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055598edd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055598edd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055598edb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055598ea65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055598ea65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9d7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9d78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9d78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055598ea65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (2669 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, alig
# | ...
# `---data was truncated (10240/32578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e3c15beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e3c158e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e3c15c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b1c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b1c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b1c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b1c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e3c0f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e3c0f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e3c0d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e3bd85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e3bd85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b1c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b1c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b1c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e3bd85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (2670 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f86f934eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f86f931e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f86f93562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddfbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddfbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddfbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddfbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f86f8cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f86f8caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f86f8af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f86f55ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f86f55eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddfbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddfbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddfbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f86f55ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (2671 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale
# | ...
# `---data was truncated (10240/14485) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e04fd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e04fcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e04fd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca25a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca25aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca25a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca25a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e04f68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e04f68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e04f4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e04bfce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e04bfcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca25a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca25a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca25a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e04bfca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (2672 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dd1a63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559dd1a60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559dd1a6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9614649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9614649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9614631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dd19f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559dd19f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559dd19de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559dd168de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559dd168db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9614632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96146330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dd168da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (2673 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0f74a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0f749fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0f74a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c40449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c404a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c40449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c40431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0f7438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0f7438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0f741d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0f70cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0f70ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c40432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c404330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c404330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0f70cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (2674 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5)
# |   %7 = extractvalue { i32, <4 x i32> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <4 x i32> } %6, 1
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# | 
# | ...
# `---data was truncated (10240/11454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608c9b67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608c9b64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608c9b6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1aa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1aa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1aa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1aa71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608c9afdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608c9afda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608c9ae28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608c9791e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608c9791b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1aa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1aa71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1aa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608c9791a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (2675 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ec4ebeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ec4ebbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ec4ebf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2188049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21880a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2188049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2188031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ec4e54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ec4e54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ec4e398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ec4ae8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ec4ae8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2188032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21880330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21880330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ec4ae8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (2676 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, al
# | ...
# `---data was truncated (10240/169925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599ef80ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599ef809e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599ef80d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca5c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca5c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca5c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca5c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599ef7a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599ef7a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599ef7878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599ef436e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599ef436b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca5c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca5c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca5c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599ef436a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (2677 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569003fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569003f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569003fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f086c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f086c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f086c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f086c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556900391bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556900391a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569003768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556900025e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556900025b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f086c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f086c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f086c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556900025a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (2678 of 27910)
******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c"
# | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128"
# | target triple = "i386-apple-darwin10"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke_copy_to_stack() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 {
# | entry:
# |   %that.addr = alloca ptr, align 4
# |   %methodIndex.addr = alloca i32, align 4
# |   %paramCount.addr = alloca i32, align 4
# |   %params.addr = alloca ptr, align 4
# |   store ptr %that, ptr %that.addr, align 4
# |   store i32 %methodIndex, ptr %methodIndex.addr, align 4
# |   store i32 %paramCount, ptr %paramCount.addr, align 4
# |   store ptr %params, ptr %params.addr, align 4
# |   call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
# | attributes #1 = { nounwind }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"NumRegisterParameters", i32 0}
# | !1 = !{!"clang version 24.0.0"}
# | !2 = !{i64 1623}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# |  #0 0x000055c8fbab5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8fbab2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8fbab662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23aeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23aeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23aeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23aeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8fba4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8fba4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8fba308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8fb6dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8fb6dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23aeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23aeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23aeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8fb6dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (2679 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f4aaf5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f4aaf2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f4aaf662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98a5505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98a555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98a5505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98a54ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f4aa8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f4aa8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f4aa708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f4a71fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f4a71fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98a54eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98a54ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98a54ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f4a71fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (2680 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback 
# | ...
# `---data was truncated (10240/15245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568001f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568001f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568001f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f904a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f904a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f904a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f904a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556800189bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556800189a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055680016e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567ffe1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567ffe1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f904a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f904a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f904a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567ffe1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (2681 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b095ddbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b095dd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b095ddc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2998133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f299818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2998133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f299811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b095d71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b095d71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b095d568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b095a05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b095a05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f299811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f299811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f299811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b095a05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (2682 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614a0b79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614a0b76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614a0b7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e29b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e29b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e29b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e29b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614a0b0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614a0b0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614a0af48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614a07a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614a07a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e29b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e29b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e29b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614a07a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (2683 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e1c176eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e1c173e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e1c17762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5004133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f500418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5004133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f500411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e1c10cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e1c10ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e1c0f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e1bda0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e1bda0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f500411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f500411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f500411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e1bda0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (2684 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac46cc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac46cbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac46cc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fe5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fe5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fe5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fe5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac46c56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac46c56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac46c3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac468eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac468eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fe5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fe5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fe5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac468eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (2685 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a371a7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a371a7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a371a8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8fd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8fd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8fd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8fd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a371a15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a371a15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3719fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3716a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3716a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8fd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8fd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8fd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3716a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2686 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/26702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8e9f52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8e9f4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8e9f5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d12249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d122a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d12249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d12231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8e9ee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8e9ee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8e9ecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8e9b7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8e9b7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d12232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d122330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d122330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8e9b7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (2687 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6e145beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6e1458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6e145c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2ab105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2ab15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2ab105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2ab0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6e13f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6e13f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6e13d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6e1085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6e1085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2ab0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2ab0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2ab0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6e1085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (2688 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560284da7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560284da4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560284da862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2b3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2b36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2b3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2b3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560284d3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560284d3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560284d228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602849d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602849d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2b3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2b36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2b36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602849d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (2689 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594dca35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594dca32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594dca3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71ad305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71ad35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71ad305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71ad2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594dc9cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594dc9cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594dc9b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594dc65fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594dc65fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71ad2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71ad2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71ad2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594dc65fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (2690 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ef8854eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ef8851e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ef885562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b0dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b0dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b0dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b0dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ef87eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ef87eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ef87cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ef847ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ef847eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b0dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b0dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b0dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ef847ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (2691 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7cecf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7cecf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7cecf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe247b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe247b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe247b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe247b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7cec8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7cec8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7cec718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7ce920e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7ce920b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe247b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe247b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe247b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7ce920a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (2692 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637e02a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637e029de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637e02a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2223c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2223ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2223c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2223c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637e0236bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637e0236a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637e021b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637dfecae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637dfecab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2223c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2223c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2223c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637dfecaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (2693 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/14493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fd389feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fd389ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fd38a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98b3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98b3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98b3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98b3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fd3835bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fd3835a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fd381a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fd34c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fd34c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98b3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98b3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98b3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fd34c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (2694 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = sitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = uitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = sitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = uitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptosi <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptosi <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptoui <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptoui <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm
# | ...
# `---data was truncated (10240/37578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b49c71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b49c6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b49c7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff120933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff12098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff120933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff12091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b49c07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b49c07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b49bec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b4989be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b4989bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff12091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff12091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff12091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b4989ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (2695 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056270c128eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056270c125e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056270c12962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe27481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2748725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe27481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe274803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056270c0bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056270c0bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056270c0a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056270bd52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056270bd52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe274804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2748050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2748050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056270bd52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (2696 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623763e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623763e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623763e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5616449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56164a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5616449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5616431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056237637dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056237637da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623763628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562376011e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562376011b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5616432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56164330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56164330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562376011a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (2697 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x
# | ...
# `---data was truncated (10240/58661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631f550feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631f550ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631f551062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f691b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f691b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f691b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f691b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631f54a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631f54a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631f548a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631f5139e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631f5139b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f691b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f691b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f691b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631f5139a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (2698 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562742a42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562742a3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562742a4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f900ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f900ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f900ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f900ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627429d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627429d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627429bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056274266ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056274266cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f900ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f900ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f900ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056274266ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (2699 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fb0779eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561fb0776e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561fb077a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f374b61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f374b6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f374b61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f374b603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fb070fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561fb070fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561fb06f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561fb03a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561fb03a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f374b604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f374b6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f374b6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fb03a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (2700 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557986cfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557986cf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557986cfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f220a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f220a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f220a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f220a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557986c91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557986c91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557986c768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557986925e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557986925b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f220a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f220a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f220a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557986925a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (2701 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055651760deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055651760ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055651760e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c51705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c5175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c51705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c516ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565175a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565175a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565175888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556517237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556517237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c516eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c516ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c516ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556517237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (2702 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/58460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557327bb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557327bb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557327bb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8230049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82300a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8230049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8230031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557327b4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557327b4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557327b338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573277e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573277e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8230032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82300330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82300330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573277e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (2703 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbd49bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbd49b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbd49bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa220b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa220b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa220b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa220b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbd4951bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbd4951a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbd49368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbd45e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbd45e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa220b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa220b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa220b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbd45e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (2704 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ac5d52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ac5d4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ac5d5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa834b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa834b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa834b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa834b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ac5ce8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ac5ce8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ac5ccd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ac597ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ac597cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa834b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa834b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa834b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ac597ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (2705 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp ule <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp ule <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp ule <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e74c8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e74c89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e74c8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3443c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3443c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3443c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3443c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e74c22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e74c22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e74c078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e748b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e748b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3443c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3443c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3443c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e748b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (2706 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643c453ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643c4539e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643c453d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61ca333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61ca38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61ca333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61ca31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643c44d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643c44d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643c44b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643c4166e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643c4166b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61ca31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61ca31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61ca31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643c4166a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (2707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |  
# | ...
# `---data was truncated (10240/28350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056294377ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562943779e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056294377d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f864c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f864c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f864c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f864c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562943712bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562943712a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629436f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629433a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629433a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f864c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f864c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f864c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629433a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (2708 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653a43e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653a43e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653a43e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7079133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f707918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7079133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f707911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653a437abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653a437aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653a435f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653a400ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653a400eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f707911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f707911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f707911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653a400ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (2709 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8ec83deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8ec83ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8ec83e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f5e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f5e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f5e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f5e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8ec7d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8ec7d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8ec7b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8ec467e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8ec467b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f5e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f5e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f5e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8ec467a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (2710 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056536a64deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056536a64ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056536a64e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6469e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6469ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6469e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6469e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056536a5e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056536a5e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056536a5c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056536a277e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056536a277b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6469e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6469e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6469e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056536a277a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (2711 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d21b4d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d21b4d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d21b4d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40e9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40e92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40e9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40e9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d21b46abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d21b46aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d21b44f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d21b0fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d21b0feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40e9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40e92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40e92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d21b0fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (2712 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055600ce00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055600cdfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055600ce0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3c4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3c498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3c4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3c491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055600cd96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055600cd96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055600cd7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055600ca2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055600ca2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3c491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3c491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3c491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055600ca2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (2713 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vs
# | ...
# `---data was truncated (10240/18591) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620cb368eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620cb365e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620cb36962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0e8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0e88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0e8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0e8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620cb2febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620cb2fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620cb2e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620caf92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620caf92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0e8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0e88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0e88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620caf92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (2714 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cae88beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cae888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cae88c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d61333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d6138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d61333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d6131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cae821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cae821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cae8068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cae4b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cae4b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d6131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d6131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d6131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cae4b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (2715 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056021b2c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056021b2c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056021b2ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34c0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34c0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34c0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34c0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056021b25fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056021b25fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056021b2448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056021aef3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056021aef3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34c0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34c0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34c0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056021aef3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (2716 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d48f1a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d48f1a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d48f1a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f94449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f944a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f94449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f94431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d48f13bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d48f13ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d48f1208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d48edcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d48edcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f94432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f944330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f944330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d48edcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (2717 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb7b2cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb7b2cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb7b2d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23f6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23f66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23f6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23f6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb7b265bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb7b265a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb7b24a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb7aef9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb7aef9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23f6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23f66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23f66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb7aef9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (2718 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv
# | ...
# `---data was truncated (10240/165238) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa102dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa102dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa102e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f36533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f3658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f36533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f3651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa10275bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa10275a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa1025a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa0ff09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa0ff09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f3651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f3651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f3651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa0ff09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (2719 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056073b7b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056073b7b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056073b7b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ff0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ff0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ff0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ff0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056073b74cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056073b74ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056073b7318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056073b3e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056073b3e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ff0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ff0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ff0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056073b3e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (2720 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574f5cd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574f5cd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574f5cd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2eda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2edaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2eda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2eda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574f5c6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574f5c6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574f5c518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574f5900e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574f5900b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2eda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2eda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2eda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574f5900a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (2721 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vsc
# | ...
# `---data was truncated (10240/207075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1e7ecfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1e7ecce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1e7ed062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64f9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64f998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64f9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64f991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1e7e65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1e7e65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1e7e4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1e7af9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1e7af9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64f991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64f991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64f991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1e7af9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (2722 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nou
# | ...
# `---data was truncated (10240/25034) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5033e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5033dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5033e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6c5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6c538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6c5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6c531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e503377bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e503377a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e50335c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e50300be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e50300bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6c531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6c531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6c531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e50300ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (2723 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642695ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642695e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642695ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce86e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce86ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce86e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce86e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564269581bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564269581a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642695668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564269215e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564269215b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce86e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce86e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce86e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564269215a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (2724 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056317f62ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056317f629e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056317f62d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd75f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd75f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd75f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd75f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056317f5c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056317f5c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056317f5a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056317f256e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056317f256b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd75f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd75f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd75f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056317f256a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (2725 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f6c750eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f6c74de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f6c75162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a62e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a62ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a62e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a62e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f6c6e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f6c6e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f6c6cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f6c37ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f6c37ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a62e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a62e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a62e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f6c37aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (2726 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f00b1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f00b1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f00b2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48ab049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48ab0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48ab049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48ab031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f00ab5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f00ab5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f00a9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f00749e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f00749b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48ab032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48ab0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48ab0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f00749a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (2727 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1cf678eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1cf675e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1cf67962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f431c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f431c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f431c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f431c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1cf60ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1cf60ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1cf5f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1cf2a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1cf2a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f431c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f431c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f431c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1cf2a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (2728 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr,
# | ...
# `---data was truncated (10240/23056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056243808aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562438087e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056243808b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8439049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84390a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8439049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8439031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562438020bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562438020a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624380058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562437cb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562437cb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8439032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84390330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84390330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562437cb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (2729 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x
# | ...
# `---data was truncated (10240/29379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640547baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640547b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640547bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f9401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f940725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f9401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f94003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564054750bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564054750a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640547358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640543e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640543e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f94004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f940050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f940050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640543e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (2730 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8
# | ...
# `---data was truncated (10240/215036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bef1fe2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bef1fdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bef1fe362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedfb41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedfb4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedfb41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedfb403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bef1f78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bef1f78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bef1f5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bef1c0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bef1c0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedfb404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedfb4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedfb4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bef1c0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (2731 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i
# | ...
# `---data was truncated (10240/23350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055b31beeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b31bee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b31beeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dfc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dfc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dfc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dfc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b31be80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b31be80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b31be658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b31bb14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b31bb14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dfc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dfc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dfc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b31bb14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (2732 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632b22ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632b22cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632b22cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d6eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d6eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d6eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d6eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632b2264bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632b2264a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632b22498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632b1ef8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632b1ef8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d6eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d6eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d6eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632b1ef8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (2733 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efa2366eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efa2363e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efa236762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f122f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f122f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f122f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f122f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efa22fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efa22fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efa22e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efa1f90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efa1f90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f122f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f122f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f122f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efa1f90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (2734 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631f19b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631f19aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631f19b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc46649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc46649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc46631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631f1947bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631f1947a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631f192c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631f15dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631f15dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc46632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc466330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631f15dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (2735 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f2919ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f29199e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f2919d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73b1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73b1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73b1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73b1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f29132bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f29132a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f291178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f28dc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f28dc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73b1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73b1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73b1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f28dc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (2736 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595ef6a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595ef6a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595ef6a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b95849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b958a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b95849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b95831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595ef63dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595ef63da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595ef6228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595ef2d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595ef2d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b95832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b958330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b958330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595ef2d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (2737 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, p
# | ...
# `---data was truncated (10240/33435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583c2b2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583c2b2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583c2b2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c98b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c98b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c98b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c98b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583c2ac3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583c2ac3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583c2aa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583c2757e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583c2757b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c98b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c98b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c98b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583c2757a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (2738 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %low.addr = alloca <4 x half>, align 8
# |   %high.addr = alloca <4 x half>, align 8
# |   store <4 x half> %low, ptr %low.addr, align 8
# |   store <4 x half> %high, ptr %high.addr, align 8
# |   %0 = load <4 x half>, ptr %low.addr, align 8
# |   %1 = load <4 x half>, ptr %high.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 {
# | entry:
# |   %__p0.addr.
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a14655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a14652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a1465662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a145ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a145eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a145d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a1427fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a1427fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05c5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a1427fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (2739 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# | 
# | ...
# `---data was truncated (10240/100521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556094009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556094006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055609400a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f958c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f958c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f958c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f958c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556093f9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556093f9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556093f848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556093c33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556093c33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f958c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f958c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f958c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556093c33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (2740 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056041ab40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056041ab3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056041ab4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f047a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f047a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f047a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f047a2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056041aad6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056041aad6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056041aabb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056041a76ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056041a76ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f047a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f047a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f047a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056041a76aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (2741 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a4a470eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a4a46de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a4a47162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f872f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f872f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f872f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f872f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a4a406bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a4a406a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a4a3eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a4a09ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a4a09ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f872f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f872f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f872f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a4a09aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (2742 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedo
# | ...
# `---data was truncated (10240/30751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056076e8b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056076e8afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056076e8b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9452f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9452f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9452f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9452f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056076e848bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056076e848a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056076e82d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056076e4dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056076e4dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9452f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9452f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9452f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056076e4dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (2743 of 27910)
******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm    /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   %fpext = fpext bfloat %0 to float
# |   %fptrunc = fptrunc float %fpext to half
# |   ret half %fptrunc
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %fpext = fpext half %0 to float
# |   %fptrunc = fptrunc float %fpext to bfloat
# |   ret bfloat %fptrunc
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2d418beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2d4188e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2d418c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba49333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba4938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba49333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba4931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2d4121bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2d4121a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2d41068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2d3db5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2d3db5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba4931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba4931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba4931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2d3db5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (2744 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x_x_v_u64
# | ...
# `---data was truncated (10240/29259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592239d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592239cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592239d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fc0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fc018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fc0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fc011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559223968bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559223968a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055922394d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592235fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592235fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fc011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fc011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fc011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592235fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (2745 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea4100aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea41007e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea4100b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c8a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c8a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c8a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c8a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea40fa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea40fa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea40f858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea40c34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea40c34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c8a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c8a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c8a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea40c34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (2746 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = all
# | ...
# `---data was truncated (10240/41587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e812815eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e812812e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e81281662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55b0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55b04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55b0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55b0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8127abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8127aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8127908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e81243fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e81243fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55b0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55b04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55b04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e81243fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (2747 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/18353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac7e99aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac7e997e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac7e99b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d67c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d67ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d67c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d67c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac7e930bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac7e930a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac7e9158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac7e5c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac7e5c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d67c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d67c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d67c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac7e5c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (2748 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> poison, half %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> poison, half %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> poison, half %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> poison, half %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> poison, half %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> poison, half %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> poison, float %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> poison, float %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> poison, float %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> poison, float %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float> poison, float %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double> poison, double %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double> poison, double %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(<vscale x 4 x double> poison, double %0, i64 %1)
# |   
# | ...
# `---data was truncated (10240/30849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055987afdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055987afdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055987afe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feddc21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feddc2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feddc21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feddc203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055987af75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055987af75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055987af5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055987ac09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055987ac09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feddc204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feddc2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feddc2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055987ac09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (2749 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e815daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e815d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e815db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa745733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa74578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa745733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa74571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e81570bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e81570a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e815558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e81204e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e81204b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa74571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa74571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa74571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e81204a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (2750 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db9948deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db9948ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db9948e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd40c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd40c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd40c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd40c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db99423bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db99423a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db994088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db990b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db990b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd40c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd40c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd40c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db990b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (2751 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560073a58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560073a55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560073a5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2745533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f274558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2745533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f274551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600739eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600739eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600739d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560073682e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560073682b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f274551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f274551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f274551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560073682a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (2752 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b30527eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b30524e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b3052862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb13d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb13d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb13d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb13d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b304bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b304bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b304a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b30151e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b30151b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb13d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb13d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb13d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b30151a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (2753 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | declare void @g(<1 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_cst(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %vecext = extractelement <16 x i8> %0, i32 3
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# |  #0 0x000055f771b1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f771b18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f771b1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9463533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f946358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9463533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f946351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f771ab1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f771ab1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f771a968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f771745e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f771745b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f946351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f946351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f946351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f771745a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (2754 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a8ea58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a8ea55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a8ea5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e15a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e15aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e15a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e15a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a8e9eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a8e9eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a8e9d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a8e682e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a8e682b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e15a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e15a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e15a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a8e682a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (2755 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> po
# | ...
# `---data was truncated (10240/50898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f83807eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f83804e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f8380862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bb3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bb318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bb3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bb311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f8379dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f8379da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f837828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f83431e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f83431b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0bb311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bb311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bb311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f83431a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (2756 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647ee7d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647ee7cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647ee7d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bef01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bef0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bef01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bef003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647ee766bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647ee766a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647ee74b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647ee3fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647ee3fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bef004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bef0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bef0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647ee3faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (2757 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/26996) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac152d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac152d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac152d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a99c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a99ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a99c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a99c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac1526bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac1526ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac152508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac14effe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac14effb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a99c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a99c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a99c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac14effa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (2758 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e0b945eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e0b942e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e0b94662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4958d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4958d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4958d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4958d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e0b8dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e0b8dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e0b8c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e0b56fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e0b56fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4958d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4958d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4958d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e0b56fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (2759 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e1ed01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e1ecfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e1ed0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8f9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8f938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8f9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8f931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e1ec97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e1ec97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e1ec7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e1e92be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e1e92bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8f931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8f931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8f931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e1e92ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (2760 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e768a81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e768a7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e768a8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2422533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f242258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2422533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f242251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e768a17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e768a17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7689fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7686abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7686abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f242251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f242251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f242251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7686aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (2761 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/12680) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649a5a60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649a5a5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649a5a6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb828133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb82818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb828133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb82811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649a59f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649a59f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649a59db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649a568ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649a568ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb82811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb82811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb82811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649a568aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (2762 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583f78d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583f78cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583f78d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3c8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3c8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3c8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3c8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583f7866bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583f7866a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583f784b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583f74fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583f74fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3c8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3c8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3c8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583f74faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (2763 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cd71ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cd71e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cd71ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff06249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff06249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff06231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cd7181bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cd7181a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cd71668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cd6e15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cd6e15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff06232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff062330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cd6e15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (2764 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b2e7aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b2e7a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b2e7ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd27e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd27ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd27e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd27e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b2e740bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b2e740a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b2e7258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b2e3d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b2e3d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd27e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd27e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd27e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b2e3d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (2765 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056221aca9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056221aca6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056221acaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc601849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6018a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc601849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc601831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056221ac3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056221ac3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056221ac248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056221a8d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056221a8d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc601832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6018330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6018330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056221a8d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (2766 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563effe58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563effe55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563effe5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4064933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f406498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4064933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f406491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563effdeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563effdeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563effdd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563effa82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563effa82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f406491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f406491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f406491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563effa82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (2767 of 27910)
******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32-unknown-unknown"
# | 
# | %struct.asc = type { i8, i16, i32, i32, float, double }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %0 = load i32, ptr %argp.next, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16
# |   store ptr %argp.next2, ptr %va, align 4
# |   %2 = load double, ptr %1, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %2
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11
# |   %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load i32, ptr %argp.next, align 8, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0)
# |   store <2 x i64> %call, ptr %r, align 16, !tbaa !9
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr n
# | ...
# `---data was truncated (10240/20646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default<O1>) --expand-variadics-override=optimize -o -
# |  #0 0x000055ef71359eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef71356e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef7135a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f868b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f868b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f868b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f868b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef712efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef712efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef712d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef70f83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef70f83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f868b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f868b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f868b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef70f83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (2768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1,
# | ...
# `---data was truncated (10240/28354) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1ece19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1ece16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1ece1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95fb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95fb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95fb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95fb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1ecdafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1ecdafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1ecd948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1eca43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1eca43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95fb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95fb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95fb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1eca43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (2769 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f27810ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f278109e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f27810d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b53f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b53f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b53f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b53f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2780a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2780a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2780878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f277d36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f277d36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b53f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b53f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b53f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f277d36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (2770 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603bf85feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603bf85ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603bf86062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f877f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f877f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f877f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f877f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603bf7f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603bf7f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603bf7da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603bf489e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603bf489b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f877f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f877f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f877f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603bf489a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (2771 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606720d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606720d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606720d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8766a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8766aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8766a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8766a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056067206ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056067206ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606720538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560671d02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560671d02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8766a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8766a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8766a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560671d02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (2772 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d6950beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d69508e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d6950c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd29c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd29c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd29c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd29c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d694a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d694a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d694868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d69135e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d69135b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd29c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd29c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd29c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d69135a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (2773 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/14699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f10847eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f10844e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f1084862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7a9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7a918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7a9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7a911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f107ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f107dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f107c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f10471e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f10471b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7a911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7a911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7a911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f10471a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (2774 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg
# | ...
# `---data was truncated (10240/20531) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6501feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6501fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6501ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff379a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff379aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff379a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff379a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e650194bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e650194a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6501798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e64fe28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e64fe28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff379a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff379a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff379a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e64fe28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (2775 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 =
# | ...
# `---data was truncated (10240/39218) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a132bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a132b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a132bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0114d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0114d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0114d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0114d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a13251bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a13251a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a132368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a12ee5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a12ee5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0114d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0114d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0114d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a12ee5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (2776 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614540aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614540a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614540ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f338501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33850725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f338501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3385003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561454042bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561454042a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614540278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561453cd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561453cd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3385004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33850050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33850050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561453cd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (2777 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x ha
# | ...
# `---data was truncated (10240/58653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556615673eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556615670e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055661567462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ef3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ef3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ef3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ef3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556615609bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556615609a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566155ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055661529de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055661529db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ef3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ef3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ef3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055661529da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (2778 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055798010eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055798010be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055798010f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05b0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05b058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05b0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05b051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579800a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579800a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579800898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055797fd38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055797fd38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05b051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05b051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05b051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055797fd38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (2779 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566c97c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566c97bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566c97c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1147733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f114778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1147733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f114771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566c9758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566c9758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566c973d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566c93ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566c93ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f114771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f114771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f114771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566c93eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (2780 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056284c44aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056284c447e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056284c44b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a7c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a7c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a7c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a7c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056284c3e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056284c3e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056284c3c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056284c074e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056284c074b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a7c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a7c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a7c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056284c074a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (2781 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   
# | ...
# `---data was truncated (10240/23061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e9d9d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e9d9d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e9d9d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d74133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d7418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d74133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d7411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e9d96abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e9d96aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e9d94f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e9d5fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e9d5feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d7411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d7411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d7411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e9d5fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (2782 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055665d9e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055665d9e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055665d9e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70c1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70c198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70c1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70c191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055665d979bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055665d979a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055665d95e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055665d60de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055665d60db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70c191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70c191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70c191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055665d60da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (2783 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055977b5f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055977b5f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055977b5f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2beb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2beb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2beb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2beb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055977b58ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055977b58ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055977b5738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055977b222e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055977b222b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2beb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2beb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2beb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055977b222a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (2784 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbd77c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbd77c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbd77c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb818249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8182a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb818249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb818231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbd775bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbd775ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbd77408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbd73efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbd73efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb818232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8182330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8182330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbd73efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (2785 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/14832) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d349212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d34920fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d34921362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc817049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8170a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc817049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc817031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3491a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3491a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d34918d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d348e3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d348e3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc817032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8170330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8170330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d348e3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (2786 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7459faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7459f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7459fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7da3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7da318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7da3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7da311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b745990bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b745990a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7459758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b745624e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b745624b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7da311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7da311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7da311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b745624a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (2787 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fec7a5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fec7a5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fec7a5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac8a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac8a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac8a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac8a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fec79f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fec79f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fec79d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fec7688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fec7688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac8a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac8a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac8a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fec7688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (2788 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# |  #0 0x000055e80cf78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e80cf75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e80cf7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb59cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb59cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb59cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb59cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e80cf0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e80cf0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e80cef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e80cba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e80cba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb59cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb59cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb59cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e80cba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (2789 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi    -target-feature +neon -target-feature +bf16 -mfloat-abi soft    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_812 = alloca <4 x float>, align 8
# |   %__s0_812 = alloca <4 x float>, align 8
# |   %__s1_812 = alloca <8 x bfloat>, align 8
# |   %__s2_812 = alloca <8 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x float>, align 8
# |   %__ret = alloca <4 x float>, align 8
# |   %__s0 = alloca <4 x float>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x float>, align 8
# |   %tmp2 = alloca <4 x float>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   store <4 x float> %0, ptr %__s0_812, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   store <8 x bfloat> %1, ptr %__s1_812, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <8 x bfloat> %2, ptr %__s2_812, align 8
# |   %3 = load <4 x float>, ptr %__s0_812, align 8
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 8
# |   %5 = load <4 x float>, ptr %__s2_812, align 8
# |   store <4 x float> %5, ptr %__s0, align 8
# |   %6 = load <16 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 8
# |   store <4 x float> %8, ptr %__ret, align 8
# |   %9 = load <4 x float>, ptr %__ret, align 8
# |   store <4 x float> %9, ptr %tmp, align 8
# |   %10 = load <4 x float>, ptr %tmp, align 8
# |   store <4 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %16, ptr %__ret_812, align 8
# |   %17 = load <4 x float>, ptr %__ret_812, align 8
# |   store <4 x float> %17, ptr %tmp2, align 8
# |   %18 = load <4 x float>, ptr %tmp2, align 8
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_814 = alloca <2 x float>, al
# | ...
# `---data was truncated (10240/54174) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558ab7ff2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ab7fefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ab7ff362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c67649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c67649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c67631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ab7f88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ab7f88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ab7f6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ab7c1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ab7c1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c67632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ab7c1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (2790 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558366a27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558366a24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558366a2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f027341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02734725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f027341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0273403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583669bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583669bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583669a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558366651e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558366651b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0273404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02734050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02734050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558366651a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (2791 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dca6fb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dca6fade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dca6fb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb36c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb36c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb36c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb36c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dca6f46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dca6f46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dca6f2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dca6bdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dca6bdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb36c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb36c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb36c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dca6bdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (2792 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a3a6e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a3a6e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a3a6e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e71933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e7198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e71933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e7191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a3a67ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a3a67ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a3a6638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a3a312e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a3a312b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e7191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e7191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e7191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a3a312a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (2793 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b9adc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b9adbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b9adc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f825841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82584725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f825841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8258403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b9ad58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b9ad58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b9ad3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b9a9ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b9a9ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8258404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82584050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82584050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b9a9eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (2794 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vsc
# | ...
# `---data was truncated (10240/21473) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5e6126eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5e6123e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5e612762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3865705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f386575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3865705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38656ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5e60bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5e60bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5e60a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5e5d50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5e5d50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38656eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38656ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38656ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5e5d50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (2795 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align
# | ...
# `---data was truncated (10240/18311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfa4cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfa4ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfa4cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d04733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d0478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d04733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d0471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfa4c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfa4c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfa4c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfa48fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfa48fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d0471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d0471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d0471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa48faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (2796 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617a74b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617a74b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617a74ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf8e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf8e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf8e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf8e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617a744fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617a744fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617a74348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617a70e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617a70e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf8e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf8e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf8e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617a70e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (2797 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16
# | ...
# `---data was truncated (10240/12536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c134b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c134b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c134b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1127449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11274a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1127449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1127431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c13449bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c13449a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c1342e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c130dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c130ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1127432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11274330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11274330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c130dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (2798 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa957a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa957a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa957a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa647a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa647a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa647a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa647a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa9573cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa9573ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa957218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa953d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa953d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa647a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa647a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa647a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa953d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (2799 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c  -check-prefix=RV32ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608dd522eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608dd51fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608dd52362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f4df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f4df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f4df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f4df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608dd4b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608dd4b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608dd49d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608dd14ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608dd14cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f4df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f4df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f4df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608dd14ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (2800 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9d156ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9d1569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9d156d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc422905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc42295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc422905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4228ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9d1502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9d1502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9d14e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9d1196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9d1196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4228eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4228ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4228ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9d1196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (2801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593749cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593749c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593749cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb98181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9818725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb98181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb981803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559374962bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559374962a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593749478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593745f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593745f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb981804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9818050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9818050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593745f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (2802 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055917bc9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055917bc98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055917bc9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2f5f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2f5f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2f5f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2f5eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055917bc31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055917bc31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055917bc168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055917b8c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055917b8c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2f5eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2f5eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2f5eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055917b8c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (2803 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/26512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056401eaaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056401eaa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056401eaab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f537001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53700725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f537001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5370003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056401ea40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056401ea40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056401ea258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056401e6d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056401e6d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5370004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53700050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53700050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056401e6d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (2804 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564725631eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056472562ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056472563262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f06b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f06b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f06b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f06b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647255c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647255c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647255ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056472525be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056472525bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f06b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f06b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f06b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056472525ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (2805 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv
# | ...
# `---data was truncated (10240/83637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5bc84deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5bc84ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5bc84e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f259d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f259d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f259d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f259d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5bc7e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5bc7e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5bc7c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5bc477e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5bc477b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f259d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f259d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f259d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5bc477a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (2806 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3fb9c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3fb9c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3fb9c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa762733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa76278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa762733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa76271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3fb959bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3fb959a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3fb93e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3fb5ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3fb5edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa76271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa76271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa76271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3fb5eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (2807 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fa462ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fa4629e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fa462d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c46449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c46449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c46431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fa45c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fa45c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fa45a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fa4256e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fa4256b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c46432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c464330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fa4256a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (2808 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595946e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595946e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595946e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f022b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f022b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f022b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f022b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055959467dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055959467da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595946628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559594311e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559594311b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f022b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f022b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f022b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559594311a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (2809 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056010ebdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056010ebdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056010ebe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcec8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcec84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcec8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcec8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056010eb75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056010eb75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056010eb5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056010e809e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056010e809b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcec8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcec84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcec84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056010e809a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (2810 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a74470eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a7446de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a7447162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d9e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d9e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d9e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d9e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a74406bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a74406a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a743eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a7409ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a7409ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d9e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d9e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d9e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a7409aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (2811 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e2733beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e27338e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e2733c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb79533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb7958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb79533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb7951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e272d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e272d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e272b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e26f65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e26f65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb7951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb7951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb7951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e26f65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (2812 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab449adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab449aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab449ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0b8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0b8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0b8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0b8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab44943bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab44943a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab449288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab445d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab445d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0b8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0b8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0b8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab445d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (2813 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c  -check-prefix=RV64ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64es(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64esm(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564922a68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564922a65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564922a6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb765a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb765a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb765a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb765a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649229febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649229fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649229e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564922692e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564922692b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb765a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb765a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb765a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564922692a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (2814 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da0a699eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da0a696e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da0a69a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd332a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd332aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd332a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd332a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da0a62fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da0a62fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da0a6148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da0a2c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da0a2c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd332a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd332a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd332a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da0a2c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (2815 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a32ebb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a32ebb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a32ebb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d5b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d5b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d5b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d5b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a32eb49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a32eb49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a32eb2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a32e7dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a32e7ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d5b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d5b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d5b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a32e7dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (2816 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eda4d24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eda4d21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eda4d2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6873249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6873249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6873231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eda4cbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eda4cbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eda4c9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eda494ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eda494eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6873232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eda494ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (2817 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e03e781eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e03e77ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e03e78262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7897d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7897d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7897d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7897d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e03e717bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e03e717a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e03e6fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e03e3abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e03e3abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7897d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7897d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7897d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e03e3aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (2818 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c653d69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c653d66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c653d6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff42cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff42cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff42cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff42cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c653cffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c653cffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c653ce48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c653993e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c653993b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff42cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff42cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff42cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c653993a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (2819 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8986b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8986afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8986b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9ec533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9ec58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9ec533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9ec51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e898648bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e898648a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e89862d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8982dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8982dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9ec51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9ec51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9ec51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8982dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (2820 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599cb74aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599cb747e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599cb74b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f9b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f9b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f9b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f9b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599cb6e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599cb6e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599cb6c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599cb374e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599cb374b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f9b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f9b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f9b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599cb374a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (2821 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d74691eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d7468ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d7469262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8c0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8c078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8c0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8c071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d74627bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d74627a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d7460c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d742bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d742bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8c071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8c071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8c071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d742bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (2822 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_i8m1_i8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m1_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m2_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m1_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m2_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m4_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 32 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> %0, <vscale x 32 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8>, <vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_u8m1_u8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m1_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m2_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m1_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m2_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m4_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, p
# | ...
# `---data was truncated (10240/54546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bca78f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bca78f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bca78f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f435a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f435a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f435a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f435a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bca788bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bca788ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bca78708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bca751fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bca751fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f435a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f435a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f435a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bca751fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (2823 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebffe38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebffe35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebffe3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f69733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f6978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f69733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f6971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebffdcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebffdcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebffdb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebffa62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebffa62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f6971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f6971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f6971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebffa62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (2824 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f14b2e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f14b2e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f14b2e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3827449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38274a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3827449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3827431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f14b279bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f14b279a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f14b25e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f14af0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f14af0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3827432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38274330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38274330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f14af0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (2825 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617bba0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617bba0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617bba0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd24b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd24b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd24b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd24b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617bb9a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617bb9a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617bb9898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617bb638e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617bb638b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd24b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd24b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd24b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617bb638a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (2826 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vsqrth_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %vsqrt, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %__s2 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load half, ptr %__s0, align 2
# |   %4 = load half, ptr %__s1, align 2
# |   %5 = load half, ptr %__s2, align 2
# |   %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %6, ptr %ref.tmp, align 2
# |   %7 = load half, ptr %ref.tmp, align 2
# |   store half %7, ptr %__ret, align 2
# |   %8 = load half, ptr %__ret, align 2
# |   store half %8, ptr %tmp, align 2
# |   %9 = load half, ptr %tmp, align 2
# |   ret half %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# |  #0 0x0000555ab92fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ab92f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ab92fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ebf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ebf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ebf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ebf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ab9292bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ab9292a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ab92778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ab8f26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ab8f26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ebf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ebf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ebf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ab8f26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (2827 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_
# | ...
# `---data was truncated (10240/10440) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056472a927eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056472a924e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056472a92862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69cec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69ceca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69cec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69cec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056472a8bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056472a8bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056472a8a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056472a551e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056472a551b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69cec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69cec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69cec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056472a551a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (2828 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599f5c72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599f5c6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599f5c7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff92f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff92f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff92f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff92f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599f5c08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599f5c08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599f5bed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599f589ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599f589cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff92f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff92f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff92f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599f589ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (2829 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #
# | ...
# `---data was truncated (10240/26584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4a75bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4a75b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4a75bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaaa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaaa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaaa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaaa431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4a7552bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4a7552a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4a75378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4a71e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4a71e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faaaa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaaa4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaaa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4a71e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (2830 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f0956ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f09569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f0956d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3984049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39840a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3984049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3984031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f09502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f09502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f094e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f09196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f09196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3984032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39840330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39840330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f09196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (2831 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f59da9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f59da6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f59daa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f858fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f858fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f858fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f858fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f59d3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f59d3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f59d248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f599d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f599d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f858fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f858fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f858fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f599d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (2832 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# |  #0 0x00005645fa0faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645fa0f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645fa0fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba97a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba97aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba97a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba97a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645fa090bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645fa090a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645fa0758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645f9d24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645f9d24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba97a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba97a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba97a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645f9d24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (2833 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz
# | ...
# `---data was truncated (10240/58675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617f0e79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617f0e76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617f0e7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5c3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5c36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5c3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5c3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617f0e0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617f0e0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617f0df48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617f0aa3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617f0aa3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5c3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5c36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5c36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617f0aa3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (2834 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <v
# | ...
# `---data was truncated (10240/50890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563845f5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563845f58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563845f5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dc5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dc518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dc5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dc511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563845ef1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563845ef1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563845ed68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563845b85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563845b85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9dc511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dc511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dc511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563845b85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (2835 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595406c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595406bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595406c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53a1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53a158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53a1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53a151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559540656bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559540656a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055954063b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595402eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595402eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53a151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53a151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53a151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595402eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (2836 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645b3d6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645b3d6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645b3d6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8365049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83650a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8365049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8365031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645b3d03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645b3d03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645b3ce88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645b3997e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645b3997b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8365032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83650330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83650330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645b3997a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (2837 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <v
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561504c61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561504c5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561504c6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aac449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aac4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aac449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aac431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561504bf7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561504bf7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561504bdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056150488be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056150488bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4aac432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aac4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aac4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056150488ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/cx-complex-range.c (2838 of 27910)
******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %coerce.real, ptr %retval.realp, align 4
# |   store float %coerce.imag, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__divsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %coerce.real, ptr %.realp1, align 4
# |   store float %coerce.imag, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul_ac = fmul float %a.real, %b.real
# |   %mul_bd = fmul float %a.imag, %b.imag
# |   %mul_ad = fmul float %a.real, %b.imag
# |   %mul_bc = fmul float %a.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %real_mul_phi, ptr %retval.realp, align 4
# |   store float %imag_mul_phi, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__mulsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul_ac = fmul float %.real, %b.real
# |   %mul_bd = fmul float %.imag, %b.imag
# |   %mul_ad = fmul float %.real, %b.imag
# |   %mul_bc = fmul float %.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %real_mul_phi, ptr %.realp2, align 4
# |   store float %imag_mul_phi, ptr %.imagp3, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b = alloca { double, double }, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %2, align 8
# |   %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %3, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load doub
# | ...
# `---data was truncated (10240/29171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000564cd4e52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cd4e4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cd4e5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cd7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cd7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cd7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cd7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cd4de8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cd4de8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cd4dcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cd4a7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cd4a7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cd7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cd7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cd7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cd4a7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (2839 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558abfe0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558abfe0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558abfe1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff437649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff437649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff437631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558abfda5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558abfda5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558abfd8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558abfa39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558abfa39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff437632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4376330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558abfa39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (2840 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b980917eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b980914e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b98091862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67cd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67cd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67cd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67cd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9808adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9808ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9808928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b980541e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b980541b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67cd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67cd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67cd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b980541a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (2841 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056262395ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562623959e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056262395d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa635333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa63538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa635333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa63531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626238f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626238f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626238d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562623586e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562623586b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa63531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa63531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa63531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562623586a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (2842 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d817657eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d817654e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d81765862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8df533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8df58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8df533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8df51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8175edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8175eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8175d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d817281e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d817281b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8df51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8df51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8df51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d817281a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (2843 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   
# | ...
# `---data was truncated (10240/17236) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec911c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec911c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec911c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febd8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febd818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febd8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febd811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec9115abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec9115aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec9113f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec90deee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec90deeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febd811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febd811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febd811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec90deea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (2844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601a4f20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601a4f1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601a4f2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb436733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb43678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb436733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb43671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601a4eb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601a4eb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601a4e9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601a4b4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601a4b4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb43671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb43671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb43671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601a4b4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (2845 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055817f737eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055817f734e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055817f73862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efde4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efde418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efde4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efde411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055817f6cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055817f6cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055817f6b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055817f361e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055817f361b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efde411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efde411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efde411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055817f361a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (2846 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e6a14feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e6a14ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e6a15062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45cd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45cd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45cd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45cd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e6a0e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e6a0e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e6a0ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e69d79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e69d79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45cd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45cd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45cd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e69d79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (2847 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055662a4daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055662a4d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055662a4db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaa2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaa258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaa2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaa251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055662a470bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055662a470a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055662a4558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055662a104e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055662a104b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaa251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaa251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaa251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055662a104a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (2848 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e8fc8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e8fc88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e8fc8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0997333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f099738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0997333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f099731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e8fc21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e8fc21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e8fc068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e8f8b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e8f8b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f099731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f099731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f099731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e8f8b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (2849 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563640404eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563640401e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056364040562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5875933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f587598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5875933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f587591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056364039abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056364039aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056364037f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056364002ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056364002eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f587591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f587591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f587591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056364002ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (2850 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/135345) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dd9bafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562dd9bace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562dd9bb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d2701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d270725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d2701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d27003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dd9b45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562dd9b45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562dd9b2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562dd97d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562dd97d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d27004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d270050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d270050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dd97d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (2851 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557932e81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557932e7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557932e8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90aa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90aa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90aa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90aa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557932e17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557932e17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557932dfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557932aabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557932aabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90aa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90aa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90aa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557932aaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (2852 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64
# | ...
# `---data was truncated (10240/29175) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056286cddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056286cdd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056286cddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10e8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10e86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10e8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10e8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056286cd72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056286cd72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056286cd578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056286ca06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056286ca06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10e8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10e86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10e86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056286ca06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (2853 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d19e1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d19e18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d19e1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a50d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a50d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a50d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a50d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d19db1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d19db1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d19d968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d19a45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d19a45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a50d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a50d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a50d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d19a45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (2854 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c186aeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c186ae9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c186aed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6cd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6cd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6cd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6cd831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c186a82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c186a82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c186a678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c186716e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c186716b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6cd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6cd8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6cd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c186716a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (2855 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558323882eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055832387fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055832388362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39fa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39fa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39fa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39fa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558323818bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558323818a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583237fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583234ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583234acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39fa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39fa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39fa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583234aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (2856 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c41be7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c41be77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c41be7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa973a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa973a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa973a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa973a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c41be10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c41be10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c41bdf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c41baa4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c41baa4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa973a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa973a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa973a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c41baa4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (2857 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e175a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e175a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e175a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ada133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ada18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ada133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ada11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e1753ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e1753ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e175238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e171d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e171d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ada11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ada11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ada11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e171d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (2858 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055babbc96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055babbc93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055babbc9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe381a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe381aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe381a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe381a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055babbc2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055babbc2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055babbc118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055babb8c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055babb8c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe381a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe381a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe381a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055babb8c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (2859 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7af748eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7af745e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7af74962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a54049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a540a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a54049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a54031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7af6debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7af6dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7af6c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7af372e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7af372b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a54032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a540330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a540330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7af372a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (2860 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055559683deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055559683ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055559683e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccd5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccd58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccd5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccd5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555967d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555967d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555967b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555596467e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555596467b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccd5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccd58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccd58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555596467a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (2861 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055811d604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055811d601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055811d60562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e7ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e7ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e7ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e7ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055811d59abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055811d59aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055811d57f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055811d22ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055811d22eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e7ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e7ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e7ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055811d22ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (2862 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.ad
# | ...
# `---data was truncated (10240/13903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558518eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558518e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558518eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7a5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7a58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7a5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7a5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555851880bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555851880a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558518658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555851514e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555851514b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7a5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7a58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7a58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555851514a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (2863 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bc504feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bc504ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bc505062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb3ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb3ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb3ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb3ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bc4fe5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bc4fe5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bc4fca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bc4c79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bc4c79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb3ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb3ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb3ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bc4c79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (2864 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e37149feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e37149ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3714a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1cec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1ceca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1cec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1cec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e371435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e371435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e37141a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3710c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3710c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1cec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1cec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1cec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3710c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (2865 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579a9e68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579a9e65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579a9e6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5fed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5fed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5fed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5fed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579a9dfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579a9dfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579a9de38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579a9a92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579a9a92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5fed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5fed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5fed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579a9a92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (2866 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce5c2a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce5c2a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce5c2a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe81b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe81b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe81b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe81b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce5c23cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce5c23ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce5c2218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce5bed0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce5bed0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe81b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe81b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe81b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce5bed0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (2867 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc97e7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc97e7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc97e7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe18a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe18a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe18a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe18a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc97e13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc97e13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc97df88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc97aa7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc97aa7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe18a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe18a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe18a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc97aa7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (2868 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c  -check-prefix=RV32ZBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @orc_b_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @ctz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cpop_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctpop.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.orc.b.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctpop.i32(i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631f4843eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631f4840e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631f484462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f249b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f249b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f249b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f249b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631f47d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631f47d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631f47be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631f446de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631f446db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f249b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f249b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f249b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631f446da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (2869 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_v
# | ...
# `---data was truncated (10240/29273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557585b5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557585b5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557585b6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0b0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0b0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0b0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0b0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557585af5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557585af5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557585ada8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557585789e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557585789b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0b0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0b0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0b0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557585789a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (2870 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# |  #0 0x000056426782eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056426782be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056426782f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d0c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d0c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d0c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d0c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642677c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642677c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642677a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564267458e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564267458b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d0c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d0c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d0c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564267458a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (2871 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c95e47ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c95e479e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c95e47d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff538505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff53855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff538505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5384ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c95e412bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c95e412a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c95e3f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c95e0a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c95e0a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5384eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5384ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5384ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c95e0a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (2872 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d724ee4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d724ee1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d724ee562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f821cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f821cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f821cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f821cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d724e7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d724e7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d724e5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d724b0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d724b0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f821cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f821cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f821cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d724b0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (2873 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load ptr, ptr %carry.addr, align 4
# |   %4 = load i32, ptr %3, align 4
# |   %5 = shl i32 %4, 29
# |   %6 = load i16, ptr %p.addr, align 2
# |   %7 = zext i16 %6 to i32
# |   %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7)
# |   %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8)
# |   %10 = extractvalue { <4 x i32>, i32 } %9, 1
# |   %11 = lshr i32 %10, 29
# |   %12 = and i32 1, %11
# |   store i32 %12, ptr %3, align 4
# |   %13 = extractvalue { <4 x i32>, i32 } %9, 0
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>,
# | ...
# `---data was truncated (10240/14775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5ff7fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5ff7f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5ff7fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e85e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e85ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e85e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e85e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5ff792bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5ff792a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5ff7778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5ff426e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5ff426b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e85e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e85e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e85e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5ff426a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (2874 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd6643eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd6643be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd6643f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1395449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13954a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1395449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1395431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd663d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd663d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd663b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd66068e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd66068b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1395432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13954330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13954330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd66068a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (2875 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf69d98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf69d95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf69d9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55c6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55c6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55c6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55c6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf69d2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf69d2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf69d138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf699c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf699c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55c6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55c6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55c6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf699c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (2876 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564dc05beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564dc05bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564dc05bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f501b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f501b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f501b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f501b8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564dc0554bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564dc0554a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564dc05398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564dc01e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564dc01e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f501b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f501b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f501b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564dc01e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (2877 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b67bb8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b67bb87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b67bb8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f958581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95858725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f958581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9585803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b67bb20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b67bb20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b67bb058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b67b7b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b67b7b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9585804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95858050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95858050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b67b7b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (2878 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, 
# | ...
# `---data was truncated (10240/60217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566ba31feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566ba31ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566ba32062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cdf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cdf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cdf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cdf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566ba2b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566ba2b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566ba29a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566b9f49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566b9f49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cdf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cdf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cdf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566b9f49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (2879 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b36a16ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b36a169e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b36a16d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6be5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6be5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6be5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6be5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b36a102bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b36a102a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b36a0e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b369d96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b369d96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6be5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6be5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6be5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b369d96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (2880 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7fcabaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7fcab7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7fcabb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77b7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77b7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77b7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77b7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7fca50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7fca50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7fca358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7fc6e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7fc6e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77b7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77b7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77b7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7fc6e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (2881 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055667857eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055667857be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055667857f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f112ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f112ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f112ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f112ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556678514bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556678514a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566784f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566781a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566781a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f112ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f112ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f112ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566781a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (2882 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056047df02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056047deffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056047df0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d13f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d13f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d13f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d13f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056047de98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056047de98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056047de7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056047db2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056047db2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d13f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d13f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d13f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056047db2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (2883 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055daadfa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055daadfa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055daadfa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4148133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f414818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4148133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f414811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daadf3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055daadf3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055daadf218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055daadbd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055daadbd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f414811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f414811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f414811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daadbd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (2884 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca50256eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca50253e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca5025762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f27305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f2735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f27305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f272ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca501ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca501eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca501d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca4fe80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca4fe80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f272eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f272ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f272ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca4fe80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (2885 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afc0b33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afc0b30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afc0b3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21c9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21c918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21c9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21c911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afc0ac9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afc0ac9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afc0aae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afc075de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afc075db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21c911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21c911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21c911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afc075da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (2886 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629cb142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629cb13fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629cb14362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f5c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f5c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f5c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f5c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629cb0d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629cb0d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629cb0bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629cad6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629cad6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f5c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f5c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f5c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629cad6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (2887 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055880cd3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055880cd3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055880cd3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd987c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd987ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd987c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd987c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055880ccd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055880ccd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055880ccb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055880c968e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055880c968b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd987c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd987c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd987c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055880c968a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (2888 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056179d9e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056179d9e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056179d9e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff843649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8436a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff843649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff843631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056179d97ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056179d97ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056179d9638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056179d612e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056179d612b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff843632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8436330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8436330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056179d612a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (2889 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/25279) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ec4815eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ec4812e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ec481662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5766049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5766049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5766031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ec47abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ec47aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ec47908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ec443fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ec443fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5766032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57660330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ec443fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (2890 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3d4e8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3d4e89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3d4e8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02a8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02a8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02a8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02a8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3d4e22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3d4e22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3d4e078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3d4ab6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3d4ab6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02a8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02a8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02a8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3d4ab6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (2891 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607b5f34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607b5f31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607b5f3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f418bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f418bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f418bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f418bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607b5ecabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607b5ecaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607b5eaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607b5b5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607b5b5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f418bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f418bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f418bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607b5b5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (2892 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559449df1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559449deee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559449df262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe722a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe722aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe722a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe722a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559449d87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559449d87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559449d6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559449a1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559449a1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe722a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe722a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe722a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559449a1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (2893 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d274e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d274e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d274e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e5d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e5d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e5d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e5d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d2747cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d2747ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d274618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d27110e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d27110b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e5d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e5d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e5d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d27110a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (2894 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f9cebeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f9cebbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f9cebf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d05b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d05b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d05b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d05b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f9ce54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f9ce54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f9ce398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f9cae8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f9cae8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d05b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d05b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d05b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f9cae8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (2895 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, 
# | ...
# `---data was truncated (10240/24959) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056506fd4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056506fd47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056506fd4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff74b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff74b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff74b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff74b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056506fce0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056506fce0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056506fcc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056506f974e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056506f974b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff74b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff74b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff74b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056506f974a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (2896 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056377dc6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056377dc67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056377dc6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f699f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f699f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f699f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f699f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056377dc00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056377dc00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056377dbe58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056377d894e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056377d894b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f699f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f699f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f699f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056377d894a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (2897 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5b55eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5b55e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5b55eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa99ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa99ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa99ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa99ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5b5580bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5b5580a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5b55658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5b5214e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5b5214b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa99ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa99ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa99ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5b5214a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (2898 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target
# | ...
# `---data was truncated (10240/23439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cce3b2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cce3b2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cce3b2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9490333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f949038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9490333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f949031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cce3ac3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cce3ac3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cce3aa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cce3757e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cce3757b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f949031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f949031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f949031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cce3757a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (2899 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale 
# | ...
# `---data was truncated (10240/215486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056070b6bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056070b6b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056070b6bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6d3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6d3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6d3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6d3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056070b651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056070b651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056070b6368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056070b2e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056070b2e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6d3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6d3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6d3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056070b2e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (2900 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562319c49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562319c46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562319c4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2908b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2908b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2908b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2908b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562319bdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562319bdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562319bc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562319873e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562319873b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2908b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2908b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2908b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562319873a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (2901 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7efb7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7efb77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7efb7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc69c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc69c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc69c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc69c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7efb10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7efb10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7efaf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7ef7a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7ef7a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc69c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc69c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc69c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7ef7a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (2902 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg)
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056470c9e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056470c9e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056470c9ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd1cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd1cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd1cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd1cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056470c97fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056470c97fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056470c9648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056470c613e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056470c613b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd1cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd1cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd1cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056470c613a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (2903 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed61d9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed61d9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed61d9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93c8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93c858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93c8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93c851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed61d34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed61d34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed61d198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed619c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed619c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93c851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93c851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93c851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed619c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (2904 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c4bac6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c4bac3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c4bac762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fbeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fbeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fbeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fbeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c4ba5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c4ba5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c4ba418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c4b6f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c4b6f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fbeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fbeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fbeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c4b6f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (2905 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f3c114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f3c111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f3c11562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f203a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f203a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f203a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f203a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f3c0aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f3c0aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f3c08f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f3bd3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f3bd3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f203a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f203a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f203a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f3bd3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (2906 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d48b27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d48b24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d48b2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94b1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94b198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94b1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94b191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d48abdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d48abda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d48aa28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d48751e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d48751b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94b191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94b191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94b191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d48751a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (2907 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3a2996eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3a2993e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3a299762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa066449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0664a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa066449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa066431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3a292cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3a292ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3a29118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3a25c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3a25c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa066432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0664330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0664330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3a25c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (2908 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcd4b50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcd4b4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcd4b5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34b8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34b80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34b8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34b8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcd4ae6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcd4ae6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcd4acb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcd477ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcd477ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34b8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34b80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34b80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcd477aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (2909 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = or <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = or <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = or <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = or <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32
# | ...
# `---data was truncated (10240/10897) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561759a2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561759a27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561759a2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9feb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9feb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9feb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9feb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617599c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617599c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617599a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561759654e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561759654b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9feb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9feb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9feb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561759654a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (2910 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bbfeceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bbfecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bbfecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb51ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb51aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb51ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb51ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bbfe64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bbfe64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bbfe498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bbfaf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bbfaf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb51ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb51ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb51ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bbfaf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (2911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632bf7dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632bf7dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632bf7e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fde933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fde98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fde933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fde91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632bf775bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632bf775a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632bf75a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632bf409e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632bf409b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fde91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fde91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fde91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632bf409a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (2912 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a35516eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a35513e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a3551762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5586d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5586d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5586d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5586d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a354acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a354aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a354918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a35140e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a35140b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5586d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5586d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5586d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a35140a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (2913 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c  -check-prefix=RV32ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cca1b1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cca1b18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cca1b1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fa1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fa178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fa1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fa171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cca1ab1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cca1ab1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cca1a968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cca1745e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cca1745b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fa171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fa171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fa171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cca1745a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (2914 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056307098aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563070987e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056307098b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bec81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bec8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bec81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bec803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563070920bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563070920a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630709058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630705b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630705b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bec804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bec8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bec8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630705b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (2915 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634d1b6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634d1b6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634d1b7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c1c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c1c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c1c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c1c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634d1b05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634d1b05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634d1aea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634d1799e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634d1799b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c1c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c1c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c1c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634d1799a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (2916 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# |  #0 0x000055802472ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558024729e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055802472d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf7b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf7b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf7b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf7b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580246c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580246c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580246a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558024356e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558024356b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf7b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf7b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf7b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558024356a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (2917 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596a4d50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596a4d4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596a4d5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f641621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64162725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f641621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6416203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596a4ce6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596a4ce6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596a4ccb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596a497ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596a497ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6416204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64162050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64162050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596a497aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (2918 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056269118beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562691188e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056269118c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51a9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51a92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51a9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51a9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562691121bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562691121a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626911068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562690db5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562690db5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51a9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51a92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51a92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562690db5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (2919 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vs
# | ...
# `---data was truncated (10240/10886) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055592c88beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055592c888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055592c88c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe00a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe00a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe00a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe00a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055592c821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055592c821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055592c8068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055592c4b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055592c4b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe00a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe00a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe00a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055592c4b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (2920 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559002c23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559002c20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559002c2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb39049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb390a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb39049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb39031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559002bb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559002bb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559002b9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055900284de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055900284db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb39032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb390330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb390330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055900284da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (2921 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8b1dadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8b1daae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8b1dae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61c4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61c40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61c4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61c4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8b1d43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8b1d43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8b1d288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8b19d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8b19d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61c4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61c40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61c40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8b19d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (2922 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577b1fb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577b1fb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577b1fb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee85e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee85ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee85e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee85e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577b1f4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577b1f4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577b1f338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577b1be2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577b1be2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee85e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee85e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee85e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577b1be2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (2923 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/26764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebae63feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebae63ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebae64062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f5c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f5c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f5c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f5c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebae5d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebae5d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebae5ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebae269e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebae269b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f5c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f5c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f5c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebae269a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (2924 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/26984) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e4f9caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e4f9c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e4f9cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdd0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdd078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdd0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdd071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e4f960bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e4f960a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e4f9458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e4f5f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e4f5f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdd071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdd071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdd071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e4f5f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (2925 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056125a648eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056125a645e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056125a64962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff20ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff20cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff20ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff20ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056125a5debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056125a5dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056125a5c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056125a272e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056125a272b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff20ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff20ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff20ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056125a272a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (2926 of 27910)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.funcref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601dce5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601dce5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601dce5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff314449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff314449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff314431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601dcdf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601dcdf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601dcdd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601dca87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601dca87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff314432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3144330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601dca87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (2927 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574c558eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574c558be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574c558f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f60933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f6098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f60933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f6091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574c5524bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574c5524a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574c55098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574c51b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574c51b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f6091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f6091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f6091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574c51b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (2928 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noin
# | ...
# `---data was truncated (10240/25042) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a96884eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a96881e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a9688562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6c1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6c158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6c1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6c151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a9681abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a9681aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a967ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a964aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a964aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6c151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6c151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6c151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a964aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (2929 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584cc5f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584cc5eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584cc5f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dc6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dc6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dc6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dc6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584cc587bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584cc587a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584cc56c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584cc21be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584cc21bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dc6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dc6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dc6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584cc21ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (2930 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>
# | ...
# `---data was truncated (10240/51185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055635339ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556353399e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055635339d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ee2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ee255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ee2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ee24ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556353332bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556353332a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563533178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556352fc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556352fc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ee24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ee24ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ee24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556352fc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (2931 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %o
# | ...
# `---data was truncated (10240/76627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9b483feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9b483ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9b484062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f346c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f346c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9b47d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9b47d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9b47ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9b4469e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9b4469b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f346c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9b4469a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (2932 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa80ebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa80eb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa80ebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff72905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff7295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff72905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff728ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa80e51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa80e51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa80e368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa80ae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa80ae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff728eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff728ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff728ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa80ae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (2933 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, al
# | ...
# `---data was truncated (10240/13263) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056008982aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560089827e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056008982b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18c4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18c4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18c4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18c4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600897c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600897c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600897a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560089454e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560089454b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18c4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18c4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18c4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560089454a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (2934 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d6e8d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d6e8d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d6e8d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa342733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa34278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa342733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa34271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d6e86cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d6e86ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d6e8518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d6e500e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d6e500b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa34271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa34271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa34271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d6e500a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (2935 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562957c68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562957c65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562957c6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce01449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce014a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce01449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce01431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562957bfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562957bfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562957be38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562957892e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562957892b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce01432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce014330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce014330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562957892a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (2936 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e701a2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e701a2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e701a3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86cbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86cbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86cbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86cbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7019c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7019c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7019aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e701659e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e701659b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86cbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86cbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86cbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e701659a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (2937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7792b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7792b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7792b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a83305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a8335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a83305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a832ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d77924cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d77924ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7792318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d778ee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d778ee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a832eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a832ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a832ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d778ee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/neon-extract.c (2938 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
# |   store <8 x i8> %vext, ptr %ref.tmp, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %4, ptr %__ret, align 8
# |   %5 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %5, ptr %tmp, align 8
# |   %6 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   %5 = bitcast <8 x i8> %3 to <4 x i16>
# |   %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
# |   store <4 x i16> %vext, ptr %ref.tmp, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %6, ptr %__ret, align 8
# |   %7 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %7, ptr %tmp, align 8
# |   %8 = load <4 x i16>, ptr %tmp, align 8
# |   ret <4 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %__s1 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <2 x i32>
# |   %5 = bitcast <8 x i8> %3 to <2 x i32>
# |   %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i32> %vext, ptr %ref.tmp, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %6, ptr %__ret, align 8
# |   %7 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %7, ptr %tmp, align 8
# |   %8 = load <2 x i32>, ptr %tmp, align 8
# |   ret <2 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer
# |   store <1 x i64> %vext, ptr %ref.tmp, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %6, ptr %__ret, align 8
# |   %7 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %7, ptr %tmp, align 8
# |   %8 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca <16 x i8>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
# |   store <16 x i8> %vext, ptr %ref.tmp, align 16
# |   %4 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %4, ptr %__ret, align 16
# |   %5 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %5, ptr %tmp, align 16
# |   %6 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x i16>
# |   %5 = bitcast <16 x i8> %3 to <8 x i16>
# |   %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
# |   store <8 x i16> %vext, ptr %ref.tmp, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %6, ptr %__ret, align 16
# |   %7 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %7, ptr %tmp, align 16
# |   %8 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <4 x i32>
# |   %5 = bitcast <16 x i8> %3 to <4 x i32>
# |   %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
# |   store <4 x i32> %vext, ptr %ref.tmp, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %6, ptr %__ret, align 16
# |   %7 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %7, ptr %tmp, align 16
# |   %8 = load <4 x i32>, ptr %tmp, align 16
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i64> %vext, ptr %ref.tmp, align 16
# |   %6 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %6, ptr %__ret, align 16
# |   %7 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %7, ptr %tmp, align 16
# |   %8 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8>
# | ...
# `---data was truncated (10240/29598) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005628b18c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628b18c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628b18c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaa1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaa1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaa1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaa1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628b185abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628b185aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628b183f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628b14eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628b14eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faaa1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaa1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaa1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628b14eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (2939 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565236d58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565236d55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565236d5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3028e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3028ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3028e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3028e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565236ceebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565236ceea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565236cd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565236982e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565236982b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3028e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3028e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3028e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565236982a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (2940 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055645fd60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055645fd5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055645fd6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04f4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04f4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04f4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04f4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055645fcf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055645fcf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055645fcdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055645f98ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055645f98ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04f4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04f4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04f4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055645f98aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (2941 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055827d6c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055827d6bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055827d6c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f093a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f093a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f093a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f093a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055827d657bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055827d657a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055827d63c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055827d2ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055827d2ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f093a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f093a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f093a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055827d2eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (2942 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/24990) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555dfd11ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555dfd119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555dfd11d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb951849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9518a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb951849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb951831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dfd0b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555dfd0b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555dfd0978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555dfcd46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555dfcd46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb951832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9518330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9518330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dfcd46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (2943 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |  
# | ...
# `---data was truncated (10240/15969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056495d2beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056495d2bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056495d2bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9932933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f993298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9932933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f993291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056495d254bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056495d254a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056495d2398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056495cee8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056495cee8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f993291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f993291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f993291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056495cee8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (2944 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d133fb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d133fb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d133fb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f602cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f602cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f602cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f602cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d133f4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d133f4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d133f338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d133be2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d133be2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f602cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f602cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f602cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d133be2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (2945 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.
# | ...
# `---data was truncated (10240/18641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557706396eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557706393e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055770639762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcff0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcff058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcff0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcff051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055770632cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055770632ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577063118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557705fc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557705fc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcff051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcff051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcff051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557705fc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (2946 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055566cda8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055566cda5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055566cda962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2164b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2164b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2164b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2164b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055566cd3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055566cd3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055566cd238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055566c9d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055566c9d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2164b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2164b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2164b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055566c9d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (2947 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d113612eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d11360fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d11361362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbcdd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbcdd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbcdd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbcdced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1135a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1135a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d11358d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d11323ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d11323cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbcdceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbcdcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbcdcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d11323ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (2948 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055592e29feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055592e29ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055592e2a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5920049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59200a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5920049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5920031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055592e235bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055592e235a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055592e21a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055592dec9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055592dec9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5920032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59200330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59200330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055592dec9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (2949 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llv
# | ...
# `---data was truncated (10240/18669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556537954eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556537951e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055653795562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565378eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565378eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565378cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055653757ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055653757eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055653757ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (2950 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557eb6f1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557eb6f1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557eb6f1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0edaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0edaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0edaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0edaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557eb6eb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557eb6eb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557eb6e998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557eb6b48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557eb6b48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0edaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0edaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0edaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557eb6b48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (2951 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d143f57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d143f54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d143f5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8af533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8af58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8af533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8af51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d143eedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d143eeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d143ed28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d143b81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d143b81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8af51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8af51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8af51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d143b81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (2952 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557507b13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557507b10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557507b1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef60705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef6075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef60705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef606ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557507aa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557507aa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557507a8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055750773de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055750773db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef606eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef606ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef606ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055750773da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (2953 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa7968feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa7968ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa7969062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc149e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc149ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc149e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc149e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa79625bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa79625a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa7960a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa792b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa792b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc149e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc149e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc149e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa792b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (2954 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d675acfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d675acce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d675ad062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f433201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43320725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f433201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4332003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d675a65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d675a65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d675a4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6756f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6756f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4332004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43320050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43320050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6756f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (2955 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, a
# | ...
# `---data was truncated (10240/30276) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055653d0c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055653d0bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055653d0c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f970f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f970f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f970f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f970f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055653d057bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055653d057a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055653d03c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055653ccebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055653ccebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f970f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f970f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f970f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055653cceba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-cde-gpr.c (2956 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 {
# | entry:
# |   %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567)
# |   %1 = extractvalue { i32, i32 } %0, 1
# |   %2 = zext i32 %1 to i64
# |   %3 = shl i64 %2, 32
# |   %4 = extractvalue { i32, i32 } %0, 0
# |   %5 = zext i32 %4 to i64
# |   %6 = or i64 %3, %5
# |   ret i64 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33)
# |   %2 = extractvalue { i32, i32 } %1, 1
# |   %3 = zext i32 %2 to i64
# |   %4 = shl i64 %3, 32
# |   %5 = extractvalue { i32, i32 } %1, 0
# |   %6 = zext i32 %5 to i64
# |   %7 = or i64 %4, %6
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3)
# |   %3 = extractvalue { i32, i32 } %2, 1
# |   %4 = zext i32 %3 to i64
# |   %5 = shl i64 %4, 32
# |   %6 = extractvalue { i32, i32 } %2, 0
# |   %7 = zext i32 %6 to i64
# |   %8 = or i64 %5, %7
# |   ret i64 %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = load i32, ptr %m.addr, align 4
# |   %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b720efceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b720ef9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b720efd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc440d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc440d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc440d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc440d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b720e92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b720e92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b720e778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b720b26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b720b26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc440d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc440d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc440d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b720b26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (2957 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556463584eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556463581e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055646358562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4028d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4028d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4028d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4028d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055646351abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055646351aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564634ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564631aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564631aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4028d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4028d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4028d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564631aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (2958 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f1573eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f1573be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f1573f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3504c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3504ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3504c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3504c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f156d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f156d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f156b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f15368e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f15368b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3504c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3504c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3504c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f15368a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (2959 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557877579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557877576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055787757a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f014f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f014f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f014f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f014f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055787750fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055787750fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578774f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578771a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578771a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f014f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f014f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f014f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578771a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (2960 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee69753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee69750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee6975462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9856449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98564a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9856449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9856431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee696e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee696e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee696ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee6937de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee6937db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9856432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98564330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98564330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee6937da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (2961 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e3a970eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e3a96de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e3a97162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6854c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6854ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6854c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6854c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e3a906bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e3a906a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e3a8eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e3a59ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e3a59ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6854c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6854c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6854c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e3a59aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (2962 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d65833eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d65830e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d6583462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6927f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6927f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6927f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6927eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d657c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d657c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d657ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d6545de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d6545db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6927eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6927eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6927eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d6545da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (2963 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d289eaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d289ea7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d289eab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb59049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb590a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb59049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb59031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d289e40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d289e40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d289e258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d289ad4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d289ad4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb59032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb590330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb590330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d289ad4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (2964 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/24982) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b92e2ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b92e2cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b92e2cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa871049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8710a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa871049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa871031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b92e264bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b92e264a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b92e2498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b92def8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b92def8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa871032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8710330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8710330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b92def8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (2965 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e324542eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e32453fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e32454362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb944b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb944b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb944b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb944b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3244d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3244d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3244bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e32416ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e32416cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb944b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb944b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb944b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e32416ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (2966 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3be2e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3be2e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3be2e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f888db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f888db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f888db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f888daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3be27cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3be27ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3be2618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3bdf10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3bdf10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f888daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f888daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f888daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3bdf10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (2967 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1b526feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1b526ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1b527062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c64049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c640a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c64049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c64031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1b5205bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1b5205a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1b51ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1b4e99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1b4e99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c64032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c640330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c640330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1b4e99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (2968 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055709ba14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055709ba11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055709ba1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faba5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faba558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faba5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faba551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055709b9aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055709b9aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055709b98f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055709b63ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055709b63eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faba551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faba551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faba551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055709b63ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (2969 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c  -check-prefix=RV32ZBKC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b0db48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b0db45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b0db4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a1db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a1db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a1db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a1daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b0dadebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b0dadea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b0dac38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b0d772e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b0d772b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a1daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a1daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a1daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b0d772a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (2970 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c10b54beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c10b548e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c10b54c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaef533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaef58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaef533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaef51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c10b4e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c10b4e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c10b4c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c10b175e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c10b175b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaef51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaef51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaef51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c10b175a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (2971 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557390dfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557390dfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557390dff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f179ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f179ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f179ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f179ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557390d94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557390d94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557390d798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557390a28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557390a28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f179ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f179ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f179ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557390a28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (2972 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056473fba9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056473fba6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056473fbaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd476e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd476e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd476e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd476e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056473fb3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056473fb3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056473fb248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056473f7d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056473f7d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd476e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd476e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd476e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056473f7d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (2973 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/12648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611c3507eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611c3504e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611c350862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56f0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56f0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56f0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56f0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611c349dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611c349da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611c34828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611c3131e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611c3131b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56f0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56f0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56f0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611c3131a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (2974 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560440169eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560440166e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056044016a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b2c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b2c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b2c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b2c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604400ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604400ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604400e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056043fd93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056043fd93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b2c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b2c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b2c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056043fd93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (2975 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x 
# | ...
# `---data was truncated (10240/11632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d650cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d650c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d650cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6009333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f600938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6009333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f600931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d65061bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d65061a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d650468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d64cf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d64cf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f600931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f600931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f600931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d64cf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (2976 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f116d33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f116d30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f116d3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f466e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f466e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f466e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f466e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f116cc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f116cc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f116cae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f11695de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f11695db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f466e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f466e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f466e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f11695da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (2977 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c49b90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c49b8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c49b9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88b0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88b02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88b0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88b0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c49b26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c49b26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c49b0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c497bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c497bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88b0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88b02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88b02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c497baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (2978 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056296e3a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056296e3a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056296e3a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3625649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36256a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3625649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3625631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056296e339bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056296e339a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056296e31e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056296dfcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056296dfcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3625632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36256330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36256330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056296dfcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (2979 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f58ad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f58ad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f58ada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff59241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5924725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff59241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff592403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f58a6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f58a6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f58a548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f58703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f58703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff592404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5924050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5924050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f58703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (2980 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffc4304eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffc4301e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffc430562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0187849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01878a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0187849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0187831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffc429abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffc429aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffc427f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffc3f2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffc3f2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0187832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01878330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01878330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffc3f2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (2981 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,10
# | ...
# `---data was truncated (10240/48393) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557250a32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557250a2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557250a3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff686133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff68618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff686133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff68611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572509c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572509c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572509ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055725065ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055725065cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff68611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff68611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff68611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055725065ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (2982 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4bab7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4bab78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4bab7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fb9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fb98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fb9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fb9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4bab11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4bab11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4baaf68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4ba7a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4ba7a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fb9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fb98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fb98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4ba7a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (2983 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603db4efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603db4ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603db4f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2a3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2a38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2a3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2a3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603db485bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603db485a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603db46a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603db119e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603db119b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2a3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2a38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2a38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603db119a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (2984 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634c5893eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634c5890e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634c589462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40bfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40bfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40bfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40bfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634c5829bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634c5829a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634c580e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634c54bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634c54bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40bfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40bfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40bfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634c54bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (2985 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/12389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa57c66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa57c63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa57c6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cb1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cb138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cb1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cb131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa57bfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa57bfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa57be18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa57890e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa57890b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cb131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cb131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cb131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa57890a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (2986 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.ris
# | ...
# `---data was truncated (10240/12914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562824986eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562824983e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056282498762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb15d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb15d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb15d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb15d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056282491cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056282491ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628249018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628245b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628245b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb15d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb15d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb15d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628245b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (2987 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618a3355eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618a3352e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618a335662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2de333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2de38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2de333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2de31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618a32ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618a32eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618a32d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618a2f7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618a2f7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2de31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2de31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2de31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618a2f7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (2988 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d02492deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d02492ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d02492e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf22a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf22a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf22a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf22a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0248c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0248c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0248a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d024557e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d024557b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf22a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf22a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf22a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d024557a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (2989 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, a
# | ...
# `---data was truncated (10240/13410) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7a107beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7a1078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7a107c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a5d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a5d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a5d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a5d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7a1011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7a1011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7a0ff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7a0ca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7a0ca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a5d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a5d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a5d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7a0ca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (2990 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557786104eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557786101e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055778610562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c8d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c8d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c8d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c8d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055778609abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055778609aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055778607f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557785d2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557785d2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c8d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c8d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c8d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557785d2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (2991 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6f8353eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6f8350e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6f835462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc74f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc74f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc74f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc74f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6f82e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6f82e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6f82ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6f7f7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6f7f7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc74f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc74f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc74f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6f7f7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (2992 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056224cbf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056224cbf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056224cbfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaff431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056224cb8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056224cb8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056224cb748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056224c823e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056224c823b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaff4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056224c823a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (2993 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571989b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571989afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571989b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81eda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81edaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81eda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81eda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557198948bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557198948a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055719892d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571985dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571985dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81eda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81eda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81eda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571985dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (2994 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/11958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fe26deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fe26dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fe26df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fa2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fa275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fa2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fa26ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fe2674bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fe2674a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fe26598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fe2308e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fe2308b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fa26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fa26ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fa26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fe2308a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (2995 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = or <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = or <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = or <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = or <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, al
# | ...
# `---data was truncated (10240/11056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614e34e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614e34e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614e34ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0761133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f076118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0761133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f076111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614e347fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614e347fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614e34648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614e3113e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614e3113b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f076111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f076111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f076111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614e3113a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (2996 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565304d9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565304d9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565304da062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3469133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3469133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565304d35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565304d35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565304d1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653049c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653049c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f346911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653049c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (2997 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e218b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e218ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e218b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ef421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ef42725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ef421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ef4203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e21846bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e21846a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e2182b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e214dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e214dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ef4204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ef42050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ef42050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e214daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (2998 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b05a62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b05a5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b05a6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7bf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7bf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7bf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7bf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b059f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b059f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b059dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b0568ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b0568cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7bf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7bf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7bf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b0568ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (2999 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654aa212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654aa20fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654aa21362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5225b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5225b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5225b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5225b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654aa1a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654aa1a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654aa18d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654a9e3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654a9e3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5225b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5225b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5225b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654a9e3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (3000 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582c3e57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582c3e54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582c3e5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d13d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d13d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d13d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d13d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582c3dedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582c3deda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582c3dd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582c3a81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582c3a81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d13d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d13d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d13d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582c3a81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (3001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <v
# | ...
# `---data was truncated (10240/65080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561500f71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561500f6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561500f7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ede133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ede18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ede133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ede11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561500f07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561500f07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561500eec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561500b9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561500b9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ede11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ede11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ede11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561500b9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (3002 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b3d197eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b3d194e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b3d19862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5614533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f561458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5614533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f561451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b3d12dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b3d12da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b3d1128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b3cdc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b3cdc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f561451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f561451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f561451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b3cdc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (3003 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a06cc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a06cbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a06cc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd298905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd29895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd298905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2988ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a06c57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a06c57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a06c3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a068ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a068ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2988eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2988ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2988ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a068eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (3004 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsli
# | ...
# `---data was truncated (10240/14908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562107233eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562107230e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056210723462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71d3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71d30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71d3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71d3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621071c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621071c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621071ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562106e5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562106e5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71d3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71d30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71d30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562106e5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (3005 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vundefined_bf16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vundefined_bf16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vundefined_bf16m1() #0 {
# | entry:
# |   ret <vscale x 4 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vundefined_bf16m2() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vundefined_bf16m4() #0 {
# | entry:
# |   ret <vscale x 16 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vundefined_bf16m8() #0 {
# | entry:
# |   ret <vscale x 32 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vundefined_bf16mf4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vundefined_bf16mf4x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vundefined_bf16mf4x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vundefined_bf16mf4x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vundefined_bf16mf4x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vundefined_bf16mf4x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vundefined_bf16mf4x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vundefined_bf16mf2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vundefined_bf16mf2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vundefined_bf16mf2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vundefined_bf16mf2x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vundefined_bf16mf2x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vundefined_bf16mf2x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vundefined_bf16mf2x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vundefined_bf16m1x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vundefined_bf16m1x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vundefined_bf16m1x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vundefined_bf16m1x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vundefined_bf16m1x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vundefined_bf16m1x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vundefined_bf16m1x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vundefined_bf16m2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vundefined_bf16m2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vundefined_bf16m2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vundefined_bf16m4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a25f1d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a25f1d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a25f1d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb029533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb02958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb029533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb02951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a25f16abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a25f16aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a25f14f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a25edfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a25edfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb02951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb02951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb02951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a25edfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (3006 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563915bdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563915bdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563915bdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b8eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b8eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b8eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b8eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563915b74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563915b74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563915b598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563915808e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563915808b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b8eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b8eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b8eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563915808a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (3007 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5e7674eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5e7671e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5e767562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9785333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f978538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9785333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f978531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5e760abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5e760aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5e75ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5e729ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5e729eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f978531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f978531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f978531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5e729ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto-multi-module.ll (3008 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# |  #0 0x00005599bb6f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599bb6efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599bb6f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c03505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c0355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c03505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c034ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599bb688bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599bb688a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599bb66d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599bb31ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599bb31cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c034eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c034ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c034ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599bb31ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (3009 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc7448beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc74488e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc7448c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82c6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82c6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82c6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82c6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc74421bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc74421a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc744068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc740b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc740b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82c6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82c6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82c6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc740b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (3010 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstrid
# | ...
# `---data was truncated (10240/17118) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582c48f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582c48f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582c48f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bcb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bcb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bcb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bcb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582c488bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582c488ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582c48708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582c451fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582c451fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bcb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bcb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bcb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582c451fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (3011 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c33c19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c33c16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c33c1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5fe71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c33bafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c33bafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c33b948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c33843e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c33843b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c33843a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (3012 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple,
# | ...
# `---data was truncated (10240/27986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d90a42ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d90a429e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d90a42d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50a851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d90a3c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d90a3c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d90a3a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d90a056e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d90a056b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50a851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d90a056a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (3013 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cc24b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cc24b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cc24ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f715f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f715f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f715f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f715f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cc244fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cc244fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cc24348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cc20e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cc20e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f715f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f715f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f715f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cc20e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (3014 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fa3313eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fa3310e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fa331462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d7021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d702725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d7021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d70203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fa32a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fa32a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fa328e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fa2f3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fa2f3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d70204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d702050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d702050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fa2f3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (3015 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d7c885eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d7c882e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d7c88662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa02f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa02f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa02f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa02f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d7c81bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d7c81ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d7c8008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d7c4afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d7c4afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa02f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa02f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa02f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d7c4afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (3016 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.r
# | ...
# `---data was truncated (10240/33423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e338e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e338e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e338e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27e3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27e36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27e3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27e3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e3387abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e3387aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e3385f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e3350ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e3350eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27e3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27e36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27e36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e3350ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (3017 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055611033deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055611033ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055611033e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8759933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f875998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8759933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f875991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561102d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561102d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561102b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055610ff67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055610ff67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f875991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f875991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f875991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055610ff67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (3018 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9dcd73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9dcd70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9dcd7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76be533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76be58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76be533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76be51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9dcd09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9dcd09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9dccee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9dc99de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9dc99db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76be51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76be51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76be51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9dc99da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (3019 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df5e441eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df5e43ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df5e44262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2d6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2d618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2d6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2d611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df5e3d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df5e3d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df5e3bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df5e06be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df5e06bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2d611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2d611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2d611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df5e06ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (3020 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec6b4ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec6b4fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec6b50062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30f7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30f758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30f7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30f751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec6b495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec6b495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec6b47a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec6b129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec6b129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30f751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30f751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30f751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec6b129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (3021 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652377e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652377e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652377e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7633305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f763335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7633305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76332ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056523777dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056523777da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652377628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565237411e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565237411b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76332eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76332ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76332ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565237411a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (3022 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 =
# | ...
# `---data was truncated (10240/19190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559f3f03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559f3f00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559f3f0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b75c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b75c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b75c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b75c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559f3e99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559f3e99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559f3e7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559f3b2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559f3b2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b75c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b75c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b75c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559f3b2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (3023 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a763596eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a763593e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a76359762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec04249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec042a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec04249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec04231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a76352cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a76352ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7635118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7631c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7631c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec04232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec042330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec042330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7631c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (3024 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vsc
# | ...
# `---data was truncated (10240/41425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d48c2f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d48c2ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d48c2f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69d2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69d2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69d2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69d2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d48c286bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d48c286a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d48c26b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d48bf1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d48bf1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69d2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69d2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69d2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d48bf1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (3025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe3dbdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe3dbdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe3dbdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb20649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb206a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb20649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb20631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe3db74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe3db74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe3db598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe3d808e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe3d808b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb20632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb206330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb206330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe3d808a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (3026 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 
# | ...
# `---data was truncated (10240/26572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628267ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628267e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628267ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb52be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb52bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb52be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb52be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562826781bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562826781a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628267668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562826415e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562826415b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb52be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb52be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb52be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562826415a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (3027 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056341628deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056341628ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056341628e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc554849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5548a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc554849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc554831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563416223bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563416223a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634162088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563415eb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563415eb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc554832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5548330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5548330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563415eb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (3028 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1f3bf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1f3bf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1f3bf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe168a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe168aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe168a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe168a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1f3b8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1f3b8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1f3b738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1f3822e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1f3822b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe168a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe168a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe168a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1f3822a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (3029 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc57af3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc57af0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc57af462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb4681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb468725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb4681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb46803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc57a89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc57a89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc57a6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc5771de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc5771db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb46804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb468050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb468050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc5771da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (3030 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acc7269eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055acc7266e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055acc726a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81e1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81e1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81e1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81e1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acc71ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055acc71ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055acc71e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055acc6e93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055acc6e93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81e1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81e1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81e1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acc6e93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (3031 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055800bb9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055800bb99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055800bb9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1242a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1242a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1242a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1242a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055800bb32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055800bb32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055800bb178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055800b7c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055800b7c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1242a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1242a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1242a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055800b7c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (3032 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dcd763eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dcd760e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dcd76462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d6b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d6b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d6b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d6b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dcd6f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dcd6f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dcd6de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557dcd38de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557dcd38db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d6b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d6b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d6b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dcd38da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (3033 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c0fafeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c0fafbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c0faff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61c6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61c6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61c6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61c6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c0fa94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c0fa94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c0fa798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c0f728e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c0f728b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61c6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61c6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61c6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c0f728a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (3034 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a716efdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a716efae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a716efe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b3d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b3d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b3d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b3d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a716e93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a716e93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a716e788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a716b27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a716b27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b3d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b3d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b3d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a716b27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (3035 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056401ba4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056401ba4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056401ba4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4be8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4be838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4be8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4be831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056401b9e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056401b9e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056401b9c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056401b678e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056401b678b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4be831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4be831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4be831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056401b678a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (3036 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056301c4c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056301c4c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056301c4c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd100049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1000a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd100049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd100031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056301c45bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056301c45ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056301c4408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056301c0efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056301c0efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd100032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1000330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1000330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056301c0efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (3037 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055682f42feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055682f42ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055682f43062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6166c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6166ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6166c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6166c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055682f3c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055682f3c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055682f3aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055682f059e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055682f059b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6166c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6166c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6166c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055682f059a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (3038 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fed2d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fed2cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fed2d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38a6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38a60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38a6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38a6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fed266bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fed266a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fed24b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fecefae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fecefab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38a6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38a60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38a60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fecefaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (3039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c  -check-prefix=RV32ZKSED
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksed1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa0c4aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa0c4a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa0c4ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bfa049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bfa0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bfa049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bfa031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa0c440bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa0c440a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa0c4258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa0c0d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa0c0d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bfa032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bfa0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bfa0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa0c0d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (3040 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563562826eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563562823e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056356282762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fb4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fb458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fb4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fb451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635627bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635627bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635627a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563562450e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563562450b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fb451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fb451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fb451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563562450a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (3041 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641dffc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641dffc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641dffc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9360e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9360e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9360e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9360e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641dff5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641dff5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641dff418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641dfbf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641dfbf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9360e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9360e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9360e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641dfbf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (3042 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/88436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557caf311eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557caf30ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557caf31262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d9a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d9a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d9a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d9a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557caf2a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557caf2a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557caf28c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557caef3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557caef3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d9a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d9a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d9a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557caef3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (3043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055731589beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557315898e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055731589c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f683c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f683c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f683c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f683c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557315831bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557315831a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573158168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573154c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573154c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f683c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f683c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f683c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573154c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (3044 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcb6fdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fcb6fdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fcb6fe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5162733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f516278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5162733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f516271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcb6f75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fcb6f75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fcb6f5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fcb6c09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fcb6c09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f516271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f516271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f516271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcb6c09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (3045 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5822c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5822c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5822c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb52d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb52d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb52d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb52d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b58225ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b58225ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5822438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b581ef2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b581ef2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb52d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb52d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb52d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b581ef2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (3046 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison
# | ...
# `---data was truncated (10240/18569) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560af0167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560af0164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560af016862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb81849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb818a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb81849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb81831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560af00fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560af00fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560af00e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560aefd91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560aefd91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb81832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb818330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb818330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560aefd91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (3047 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fac7dfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fac7df7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fac7dfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83f6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83f695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83f6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83f68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fac7d90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fac7d90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fac7d758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fac7a24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fac7a24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83f68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83f68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83f68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fac7a24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (3048 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595d9890eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595d988de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595d989162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdeb6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdeb6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdeb6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdeb6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595d9826bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595d9826a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595d980b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595d94bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595d94bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdeb6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdeb6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdeb6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595d94baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (3049 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec95c01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec95bfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec95c0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f699b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f699b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f699b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f699b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec95b97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec95b97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec95b7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec9582be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec9582bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f699b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f699b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f699b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec9582ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (3050 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -252)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 -243)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 195)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 8978432)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 27391)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 -5570561)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 -18689)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 1023410175)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -11265)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -13893633)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -37)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -1644167169)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 13568)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 654311424)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 175)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 89)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8ebe08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8ebe05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8ebe0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3b9e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3b9e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3b9e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3b9e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8ebd9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8ebd9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8ebd838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8eba32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8eba32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3b9e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3b9e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3b9e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8eba32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (3051 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635ed8a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635ed89fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635ed8a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9acad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9acad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9acad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9acad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635ed838bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635ed838a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635ed81d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635ed4cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635ed4ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9acad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9acad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9acad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635ed4cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (3052 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9b3bf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9b3beee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9b3bf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2706333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f270638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2706333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f270631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9b3b87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9b3b87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9b3b6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9b381be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9b381bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f270631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f270631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f270631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9b381ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (3053 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %v
# | ...
# `---data was truncated (10240/11349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c04e1c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c04e1c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c04e1ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f339b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f339b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f339b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f339b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c04e15fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c04e15fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c04e1448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c04ddf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c04ddf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f339b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f339b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f339b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c04ddf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-arm.c (3054 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-unknown-unknown-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @f0() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   %b.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load ptr, ptr %b.addr, align 4
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf0(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtr.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf1(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtru.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd0(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtr.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd1(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtru.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 0, ptr %res, align 4
# |   store volatile i32 1, ptr %res, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_barrier() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   call void @llvm.arm.dsb(i32 2)
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch(i32 noundef %i) #0 {
# | entry:
# |   %i.addr = alloca i32, align 4
# |   store i32 %i, ptr %i.addr, align 4
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp() #0 {
# | entry:
# |   call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp2() #0 {
# | entry:
# |   call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc2() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr2(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_lo
# | ...
# `---data was truncated (10240/15632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df06579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df06576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df0657a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd19c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd19c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd19c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd19c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df0650fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df0650fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df064f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df061a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df061a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd19c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd19c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd19c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df061a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (3055 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/69542) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056067ef1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056067ef18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056067ef1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce0e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce0e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce0e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce0e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056067eeb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056067eeb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056067ee968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056067eb45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056067eb45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce0e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce0e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce0e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056067eb45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (3056 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ab4581eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ab457ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ab458262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b69533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b6958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b69533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b6951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ab4517bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ab4517a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ab44fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ab41abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ab41abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b6951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b6951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b6951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ab41aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (3057 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560df4760eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560df475de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560df476162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0488d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0488d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0488d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0488d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560df46f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560df46f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560df46db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560df438ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560df438ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0488d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0488d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0488d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560df438aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (3058 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055571303deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055571303ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055571303e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe53d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe53d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe53d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe53d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555712fd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555712fd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555712fb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555712c67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555712c67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe53d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe53d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe53d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555712c67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (3059 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562824489eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562824486e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056282448a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17bdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17bdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17bdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17bdc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056282441fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056282441fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628244048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628240b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628240b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17bdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17bdc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17bdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628240b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (3060 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf636c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf636c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf636c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9de9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9de998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9de9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9de991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf6365dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf6365da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf636428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf632f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf632f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9de991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9de991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9de991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf632f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (3061 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/27055) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ae49bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ae49bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ae49c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f28249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f282a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f28249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f28231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ae4955bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ae4955a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ae493a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ae45e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ae45e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f28232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f282330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f282330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ae45e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (3062 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a037d5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a037d57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a037d5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feee9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feee998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feee9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feee991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a037cf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a037cf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a037cd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a037984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a037984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feee991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feee991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feee991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a037984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (3063 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/54488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7a9c2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7a9c27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7a9c2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0dd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7a9bc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7a9bc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7a9ba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7a9854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7a9854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7a9854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (3064 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643603e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643603e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643603e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f175f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f175f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f175f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f175f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056436037bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056436037ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643603608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056436000fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056436000fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f175f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f175f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f175f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056436000fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (3065 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640b8886eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640b8883e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640b888762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8e8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8e86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8e8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8e8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640b881cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640b881ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640b88018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640b84b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640b84b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8e8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8e86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8e86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640b84b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (3066 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a9e832eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a9e82fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a9e83362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76e1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76e155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76e1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76e14ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a9e7c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a9e7c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a9e7ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a9e45ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a9e45cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76e14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76e14ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76e14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a9e45ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (3067 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556704aaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556704aabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556704aaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0ca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0ca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0ca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0ca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556704a44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556704a44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556704a298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567046d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567046d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0ca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0ca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0ca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567046d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (3068 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 
# | ...
# `---data was truncated (10240/26333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560159a1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560159a1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560159a2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15f7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15f775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15f7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15f76ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601599b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601599b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056015999a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560159649e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560159649b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15f76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15f76ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15f76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560159649a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (3069 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563685954eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563685951e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056368595562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa891333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa89138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa891333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa89131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636858eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636858eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636858cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056368557ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056368557eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa89131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa89131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa89131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056368557ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (3070 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633e9a5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633e9a5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633e9a6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96f4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96f46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96f4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96f4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633e99f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633e99f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633e99da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633e9689e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633e9689b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96f4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96f46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96f46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633e9689a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (3071 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573a6e6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573a6e6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573a6e6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e9b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e9b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e9b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e9b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573a6e04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573a6e04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573a6de98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573a6a98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573a6a98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e9b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e9b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e9b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573a6a98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (3072 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bf23a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bf23a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bf23a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda35f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda35f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda35f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda35f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bf233abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bf233aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bf231f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bf1fcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bf1fceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda35f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda35f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda35f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bf1fcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (3073 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2b730deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2b730ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2b730e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c1de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c1de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c1de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c1de03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2b72a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2b72a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2b72888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2b6f37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2b6f37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c1de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c1de050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c1de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2b6f37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (3074 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560890e63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560890e60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560890e6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb89a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb89a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb89a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb89a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560890df9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560890df9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560890dde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560890a8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560890a8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb89a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb89a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb89a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560890a8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (3075 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcb76c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcb76c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcb76c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cd1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cd1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cd1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cd1e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcb765abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcb765aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcb763f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcb72eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcb72eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cd1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cd1e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cd1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcb72eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (3076 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629f1381eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629f137ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629f138262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3024333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f302438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3024333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f302431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629f1317bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629f1317a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629f12fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629f0fabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629f0fabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f302431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f302431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f302431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629f0faba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (3077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623bee4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623bee49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623bee4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaacd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaacd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaacd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaacced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623bede2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623bede2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623bedc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623bea76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623bea76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaacceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaaccef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaaccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623bea76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (3078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | 
# | ...
# `---data was truncated (10240/40891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b0426eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b0426be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b0426f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f539a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f539a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f539a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f539a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b04204bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b04204a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b041e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b03e98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b03e98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f539a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f539a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f539a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b03e98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (3079 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr.i = alloca bfloat, align 2
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   store bfloat %0, ptr %bf.addr.i, align 2
# |   %1 = load bfloat, ptr %bf.addr.i, align 2
# |   %2 = fpext bfloat %1 to float
# |   ret float %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr.i = alloca float, align 4
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   store float %0, ptr %sf.addr.i, align 4
# |   %1 = load float, ptr %sf.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   ret bfloat %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056329f7a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056329f7a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056329f7aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e06733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e0678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e06733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e0671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056329f73fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056329f73fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056329f7248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056329f3d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056329f3d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e0671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e0671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e0671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056329f3d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (3080 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <v
# | ...
# `---data was truncated (10240/12083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3a7625eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3a7622e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3a762662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcc621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcc62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcc621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcc6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3a75bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3a75bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3a75a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3a724fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3a724fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcc6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcc62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcc62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3a724fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (3081 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64 noundef
# | ...
# `---data was truncated (10240/29167) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d318faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d318f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d318fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd75ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd75eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd75ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd75ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d31890bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d31890a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d318758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d31524e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d31524b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd75ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd75ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd75ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d31524a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (3082 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4e9508eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4e9505e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4e950962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b4d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b4d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b4d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b4d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4e949ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4e949ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4e94838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4e9132e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4e9132b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b4d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b4d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b4d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4e9132a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (3083 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba8f147eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba8f144e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba8f14862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f7261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f726725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f7261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f72603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba8f0ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba8f0dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba8f0c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba8ed71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba8ed71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f72604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f726050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f726050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba8ed71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (3084 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsca
# | ...
# `---data was truncated (10240/24214) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636abd3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636abd3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636abd3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f992c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f992c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f992c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f992c8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636abcd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636abcd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636abcb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636ab967e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636ab967b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f992c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f992c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f992c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636ab967a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (3085 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563752ab1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563752aaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563752ab262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf88533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf8858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf88533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf8851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563752a47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563752a47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563752a2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637526dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637526dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf8851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf8851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf8851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637526dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (3086 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7fc82ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7fc829e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7fc82d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bfb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bfb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bfb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bfb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7fc7c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7fc7c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7fc7a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7fc456e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7fc456b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bfb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bfb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bfb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7fc456a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (3087 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqr
# | ...
# `---data was truncated (10240/28170) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056390659eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056390659be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056390659f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac8e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac8e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac8e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac8e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563906534bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563906534a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639065198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639061c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639061c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac8e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac8e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac8e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639061c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (3088 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, flo
# | ...
# `---data was truncated (10240/34773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c2c19aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c2c197e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c2c19b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb45d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb45d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb45d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb45d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c2c130bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c2c130a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c2c1158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c2bdc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c2bdc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb45d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb45d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb45d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c2bdc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (3089 of 27910)
******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.annotated_flex = type { i64, i8, [0 x i8] }
# | 
# | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8
# | @sink = external global i64, align 8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_fam(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %2 = ptrtoint ptr %arraydecay to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %3 = icmp sgt i64 %flexible_array_member_size, -1
# |   %4 = select i1 %3, i64 %flexible_array_member_size, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_subscript(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2
# |   %2 = ptrtoint ptr %arrayidx to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 2
# |   %3 = icmp sgt i64 %result, -1
# |   %4 = and i1 true, %3
# |   %5 = select i1 %4, i64 %result, i64 0
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_addrof(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %2 = ptrtoint ptr %fam to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_fam() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %0 = icmp sgt i64 %flexible_array_member_size, -1
# |   %1 = select i1 %0, i64 %flexible_array_member_size, i64 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_subscript() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %0 = icmp sgt i64 %result, -1
# |   %1 = and i1 true, %0
# |   %2 = select i1 %1, i64 %result, i64 0
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_addrof() #0 {
# | entry:
# |   %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_fam(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %2 = icmp sgt i64 %flexible_array_member_size, -1
# |   %3 = select i1 %2, i64 %flexible_array_member_size, i64 0
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %2 = icmp sgt i64 %result, -1
# |   %3 = and i1 true, %2
# |   %4 = select i1 %3, i64 %result, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f8c6fd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8c6fcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8c6fd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f864b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f864b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f864b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f864b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8c6f67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8c6f67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8c6f4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8c6bfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8c6bfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f864b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f864b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f864b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8c6bfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (3090 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056489c5eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056489c5e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056489c5ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1d5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1d54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1d5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1d5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056489c582bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056489c582a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056489c5678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056489c216e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056489c216b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1d5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1d54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1d54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056489c216a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (3091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b47ff8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b47ff8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b47ff8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f796b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f796b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f796b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f796b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b47ff23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b47ff23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b47ff088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b47fbb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b47fbb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f796b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f796b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f796b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b47fbb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (3092 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6e714aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6e7147e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6e714b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfde933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfde98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfde933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfde91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6e70e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6e70e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6e70c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6e6d74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6e6d74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfde91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfde91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfde91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6e6d74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (3093 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600a4cc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600a4cc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600a4cc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fba133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fba18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fba133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fba11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600a4c59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600a4c59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600a4c3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600a48ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600a48edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fba11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fba11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fba11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600a48eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (3094 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055680ca50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055680ca4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055680ca5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5aeab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5aeab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5aeab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5aeab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055680c9e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055680c9e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055680c9cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055680c67ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055680c67ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5aeab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5aeab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5aeab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055680c67aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (3095 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf68ccaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf68cc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf68ccb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4e9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4e90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4e9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4e9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf68c60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf68c60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf68c458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf688f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf688f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4e9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4e90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4e90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf688f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (3096 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb9266ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb92669e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb9266d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e8ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e8ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e8ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e8ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb92602bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb92602a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb925e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb92296e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb92296b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e8ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e8ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e8ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb92296a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (3097 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593e38c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593e38c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593e38c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40f4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40f4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40f4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40f4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593e385abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593e385aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593e383f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593e34eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593e34eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40f4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40f4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40f4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593e34eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/packed-structure.c (3098 of 27910)
******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | %struct.s0 = type { i32, i32 }
# | %struct.s1 = type { i32, i32 }
# | %struct.s2 = type { i32, i32 }
# | %struct.s3 = type <{ i16, i32, [10 x i8] }>
# | 
# | @s0_align_x = global i32 4, align 4
# | @s0_align_y = global i32 1, align 4
# | @s0_align = global i32 4, align 4
# | @s1_align_x = global i32 1, align 4
# | @s1_align_y = global i32 1, align 4
# | @s1_align = global i32 1, align 4
# | @s2_align_x = global i32 2, align 4
# | @s2_align_y = global i32 2, align 4
# | @s2_align = global i32 2, align 4
# | @s3_1 = global i32 1, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @test3(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %anInt, align 2
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# |  #0 0x000055b9acfc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9acfc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9acfca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a9f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a9f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a9f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a9f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9acf5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9acf5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9acf448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9acbf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9acbf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a9f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a9f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a9f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9acbf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (3099 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e161e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e161dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e161e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff69d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff69d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff69d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff69d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e16178bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e16178a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e1615d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e15e0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e15e0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff69d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff69d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff69d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e15e0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (3100 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558744f69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558744f66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558744f6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f145bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f145bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f145bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f145baed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558744effbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558744effa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558744ee48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558744b93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558744b93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f145baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f145baef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f145baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558744b93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (3101 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583bc315eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583bc312e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583bc31662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f834ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f834aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f834ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f834ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583bc2abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583bc2aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583bc2908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583bbf3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583bbf3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f834ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f834ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f834ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583bbf3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (3102 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cbf3f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cbf3ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cbf3f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdfa649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdfa6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdfa649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdfa631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cbf386bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cbf386a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cbf36b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cbf01ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cbf01ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdfa632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdfa6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdfa6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cbf01aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (3103 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/17403) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c50ffe4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c50ffe1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c50ffe562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54e5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54e515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54e5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54e50ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c50ff7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c50ff7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c50ff5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c50fc0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c50fc0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54e50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54e50ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54e50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c50fc0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (3104 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2be9d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2be9cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2be9d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff598249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5982a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff598249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff598231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2be968bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2be968a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2be94d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2be5fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2be5fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff598232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5982330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5982330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2be5fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (3105 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e58c995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e58c992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e58c99662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3ee049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3ee0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3ee049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3ee031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e58c92bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e58c92ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e58c9108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e58c5bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e58c5bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3ee032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3ee0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3ee0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e58c5bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (3106 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1a2b20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1a2b1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1a2b2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9806049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98060a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9806049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9806031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1a2ab6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1a2ab6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1a2a9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1a274ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1a274ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9806032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98060330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98060330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1a274aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (3107 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592f33caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592f33c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592f33cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6e9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6e94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6e9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6e9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592f3360bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592f3360a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592f33458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592f2ff4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592f2ff4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6e9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6e94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6e94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592f2ff4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (3108 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @ll
# | ...
# `---data was truncated (10240/47728) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc4bbddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc4bbdae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc4bbde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0732b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0732b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0732b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0732b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc4bb73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc4bb73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc4bb588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc4b807e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc4b807b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0732b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0732b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0732b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc4b807a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (3109 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0b3831eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0b382ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0b383262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b7dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b7dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b7dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b7dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0b37c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0b37c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0b37ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0b345be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0b345bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b7dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b7dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b7dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0b345ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (3110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c  -check-prefix=RV64XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %not = xor i64 %0, -1
# |   %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056252caceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056252cacbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056252cacf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14a171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056252ca64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056252ca64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056252ca498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056252c6f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056252c6f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14a171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056252c6f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (3111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588919e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588919e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588919e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4664733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f466478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4664733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f466471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558891979bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558891979a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055889195e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055889160de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055889160db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f466471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f466471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f466471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055889160da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (3112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.a
# | ...
# `---data was truncated (10240/38299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2f541ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2f5419e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2f541d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aee133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aee18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aee133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aee11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2f53b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2f53b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2f53978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2f5046e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2f5046b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3aee11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aee11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aee11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2f5046a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (3113 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64
# | ...
# `---data was truncated (10240/32186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfa1b0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfa1b07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfa1b0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f332d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f332d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f332d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f332d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfa1aa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfa1aa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfa1a858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfa1734e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfa1734b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f332d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f332d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f332d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa1734a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (3114 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-none-elf"
# | 
# | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any
# | 
# | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any
# | 
# | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any
# | 
# | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{i32 1, !5}
# | !5 = !{!"aarch64.mem_hint", i32 0}
# | !6 = !{i32 1, !7}
# | !7 = !{!"aarch64.mem_hint", i32 1}
# | !8 = !{i32 0, !9}
# | !9 = !{!"aarch64.mem_hint", i32 3}
# | !10 = !{i32 0, !11}
# | !11 = !{!"aarch64.mem_hint", i32 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b3ebd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b3ebd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b3ebd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa76e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa76e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa76e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa76e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b3eb6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b3eb6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b3eb538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b3e802e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b3e802b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa76e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa76e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa76e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b3e802a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (3115 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/63177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fb1776eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fb1773e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fb177762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cc0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cc098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cc0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cc091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fb170cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fb170ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fb16f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fb13a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fb13a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cc091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cc091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cc091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fb13a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (3116 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6c86dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6c86dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6c86e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd284649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2846a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd284649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd284631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6c8675bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6c8675a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6c865a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6c8309e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6c8309b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd284632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2846330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2846330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6c8309a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (3117 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/34589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6ebe13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6ebe10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6ebe1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac0ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac0eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac0ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac0ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6ebda9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6ebda9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6ebd8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6eba3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6eba3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac0ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac0ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac0ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6eba3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (3118 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a495575eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a495572e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a49557662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e4d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e4d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e4d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e4d003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a49550bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a49550ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4954f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a49519fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a49519fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e4d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e4d0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e4d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a49519fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (3119 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558839115eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558839112e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055883911662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b35b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b35b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b35b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b35b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588390abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588390aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588390908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558838d3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558838d3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b35b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b35b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b35b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558838d3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (3120 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e61d32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e61d2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e61d3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cc2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cc2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cc2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cc2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e61cc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e61cc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e61cad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e6195ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e6195cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cc2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cc2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cc2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e6195ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (3121 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8303f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8303f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8303f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84be049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84be0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84be049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84be031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a83038dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a83038da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8303728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a830021e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a830021b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84be032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84be0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84be0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a830021a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (3122 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056476fea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056476fe9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056476fea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eec133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eec18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eec133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eec11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056476fe37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056476fe37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056476fe1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056476facbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056476facbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2eec11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eec11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eec11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056476facba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (3123 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = c
# | ...
# `---data was truncated (10240/41433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a03330eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a0332de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a0333162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f170f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f170f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f170f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f170f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a032c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a032c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a032ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a02f5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a02f5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f170f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f170f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f170f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a02f5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (3124 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e4af62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e4af5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e4af6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1668849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1668849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1668831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e4aef8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e4aef8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e4aedd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e4ab8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e4ab8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1668832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e4ab8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (3125 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i6
# | ...
# `---data was truncated (10240/18619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ccf6e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ccf6dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ccf6e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2ee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2ee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2ee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2ee51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ccf678bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ccf678a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ccf65d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ccf30ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ccf30cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2ee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2ee51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2ee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ccf30ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (3126 of 27910)
******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type { ptr, ptr, %struct.A }
# | %struct.A = type { i32 }
# | 
# | $_ZTV1B = comdat any
# | 
# | $_ZTI1B = comdat any
# | 
# | $_ZTS1B = comdat any
# | 
# | $_ZTI1A = comdat any
# | 
# | $_ZTS1A = comdat any
# | 
# | @y = local_unnamed_addr global i8 2, align 1
# | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8
# | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8
# | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8
# | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr]
# | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1
# | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8
# | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr]
# | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x0000557bfbd75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bfbd72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bfbd7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb425c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb425ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb425c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb425c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bfbd0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bfbd0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bfbcf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bfb99fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bfb99fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb425c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb425c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb425c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bfb99fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (3127 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630112c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630112bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630112c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa905733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa90578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa905733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa90571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563011256bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563011256a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056301123b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563010eeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563010eeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa90571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa90571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa90571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563010eeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (3128 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | ...
# `---data was truncated (10240/12457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df4d14beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df4d148e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df4d14c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb52333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb5238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb52333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb5231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df4d0e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df4d0e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df4d0c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df4cd75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df4cd75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb5231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb5231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb5231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df4cd75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (3129 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555f3a56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555f3a53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555f3a5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdbfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdbfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdbfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdbfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555f39ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555f39eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555f39d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555f3680e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555f3680b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdbfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdbfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdbfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555f3680a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (3130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560983abceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560983ab9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560983abd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafa8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafa86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafa8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafa8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560983a52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560983a52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560983a378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609836e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609836e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafa8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafa86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafa86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609836e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (3131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f46f579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f46f576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f46f57a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf2f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf2f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf2f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf2f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f46f50fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f46f50fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f46f4f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f46f1a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f46f1a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf2f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf2f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf2f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f46f1a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (3132 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055772fffbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055772fff8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055772fffc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f0801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f080725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f0801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f08003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772ff91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055772ff91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055772ff768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055772fc25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055772fc25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f08004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f080050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f080050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055772fc25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (3133 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055894833ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558948339e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055894833d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99a7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99a7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99a7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99a7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589482d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589482d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589482b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558947f66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558947f66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99a7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99a7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99a7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558947f66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (3134 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d567ac4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d567ac1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d567ac562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe219e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe219e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe219e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe219e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d567a5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d567a5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d567a3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5676eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5676eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe219e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe219e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe219e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5676eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (3135 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/32694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649a0f89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649a0f86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649a0f8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649a0f1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649a0f1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649a0f048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649a0bb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649a0bb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42e7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649a0bb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (3136 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %
# | ...
# `---data was truncated (10240/29809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611ff48aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611ff487e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611ff48b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e03733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e0378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e03733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e0371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611ff420bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611ff420a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611ff4058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611ff0b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611ff0b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e0371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e0371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e0371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611ff0b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (3137 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2f1435eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2f1432e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2f143662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f3ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f3ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f3ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f3ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2f13cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2f13cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2f13b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2f105fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2f105fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f3ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f3ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f3ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2f105fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (3138 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575bbcfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575bbcf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575bbcfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b64305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b6435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b64305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b642ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575bbc90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575bbc90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575bbc758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575bb924e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575bb924b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b642eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b642ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b642ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575bb924a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (3139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ed0830eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ed082de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ed083162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf32d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf32d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf32d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf32d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ed07c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ed07c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ed07ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ed045ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ed045ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf32d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf32d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf32d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ed045aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (3140 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/15211) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a31757eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a31754e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a3175862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aa5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aa50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aa5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aa5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a316edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a316eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a316d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a31381e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a31381b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2aa5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aa50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aa50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a31381a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (3141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627fed5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627fed58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627fed5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f648b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f648b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f648b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f648b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627fecf1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627fecf1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627fecd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627fe985e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627fe985b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f648b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f648b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f648b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627fe985a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (3142 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b7e584eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b7e581e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b7e58562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f291a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f291a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f291a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f291a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b7e51abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b7e51aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b7e4ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b7e1aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b7e1aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f291a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f291a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f291a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b7e1aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (3143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe9034deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe9034ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe9034e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1f1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1f14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1f1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1f1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe902e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe902e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe902c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe8ff77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe8ff77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1f1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1f14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1f14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe8ff77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (3144 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c  -check-prefix=RV32ZBKX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkx1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a138aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a138abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a138af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d28333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d2838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d28333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d2831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a13844bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a13844a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a138298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a134d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a134d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d2831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d2831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d2831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a134d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (3145 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621e5694eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621e5691e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621e569562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf0061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf006725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf0061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf00603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621e562abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621e562aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621e560f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621e52bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621e52beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf00604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf006050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf006050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621e52bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (3146 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558152a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055581529de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558152a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71d2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71d2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71d2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71d2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555815236bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555815236a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055581521b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555814ecae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555814ecab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71d2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71d2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71d2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555814ecaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (3147 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055786ef86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055786ef83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055786ef8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2886b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2886b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2886b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2886b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055786ef1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055786ef1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055786ef018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055786ebb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055786ebb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2886b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2886b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2886b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055786ebb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (3148 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f76ab0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f76aade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f76ab162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa19bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa19bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa19bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa19bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f76a46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f76a46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f76a2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f766dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f766dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa19bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa19bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa19bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f766daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (3149 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8caa2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8caa2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8caa2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fe5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fe598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fe5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fe591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8ca9c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8ca9c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8ca9a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8ca658e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8ca658b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fe591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fe591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fe591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8ca658a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (3150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vlse16_v_
# | ...
# `---data was truncated (10240/35087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556596138eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556596135e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055659613962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45c8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45c82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45c8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45c8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565960cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565960cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565960b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556595d62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556595d62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45c8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45c82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45c82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556595d62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-vget.c (3151 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -target-abi apcs-gnu    -target-cpu cortex-a8    -mfloat-abi soft    -target-feature +soft-float-abi    -ffreestanding    -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x float> @low_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr
# | ...
# `---data was truncated (10240/15571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e203b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e203b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e203b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2d2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2d2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2d2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2d2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e2034abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e2034aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e2032f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e1ffdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e1ffdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2d2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2d2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2d2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e1ffdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (3152 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558863dd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558863dd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558863dd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd68b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd68b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd68b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd68b0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558863d6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558863d6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558863d518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558863a00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558863a00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd68b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd68b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd68b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558863a00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (3153 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9c8e82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9c8e7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9c8e8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8121733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f812178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8121733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f812171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9c8e18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9c8e18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9c8dfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9c8aace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9c8aacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f812171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f812171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f812171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9c8aaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (3154 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9e272aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9e2727e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9e272b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad8f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad8f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad8f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad8f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9e26c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9e26c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9e26a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9e2354e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9e2354b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad8f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad8f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad8f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9e2354a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (3155 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/41102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5b4a53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5b4a50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5b4a5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1926305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f192635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1926305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19262ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5b49e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5b49e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5b49ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5b467de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5b467db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19262eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19262ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19262ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5b467da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (3156 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale x 16 x 
# | ...
# `---data was truncated (10240/156463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558cca00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558cc9fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558cca0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0c461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0c46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0c461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0c4603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558cc996bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558cc996a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558cc97b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558cc62ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558cc62ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0c4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0c46050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0c46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558cc62aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (3157 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce34a3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce34a3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce34a3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f865d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f865d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f865d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f865d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce349d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce349d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce349b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce34668e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce34668b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f865d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f865d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f865d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce34668a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (3158 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ba283beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ba2838e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ba283c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b49249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b492a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b49249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b49231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ba27d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ba27d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ba27b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ba2465e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ba2465b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b49232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b492330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b492330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ba2465a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (3159 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d43748eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d43745e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d4374962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa420b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa420b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa420b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa420b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d436debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d436dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d436c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d43372e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d43372b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa420b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa420b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa420b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d43372a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (3160 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c  -check-prefix=RV32ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614f173eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614f173be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614f173f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee42f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee42f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee42f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee42f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614f16d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614f16d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614f16b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614f1368e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614f1368b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee42f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee42f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee42f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614f1368a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (3161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/33772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dcc75aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559dcc757e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559dcc75b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd17d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd17d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd17d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd17d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dcc6f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559dcc6f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559dcc6d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559dcc384e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559dcc384b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd17d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd17d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd17d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dcc384a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (3162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b40a95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b40a92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b40a9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb807733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb80778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb807733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb80771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b40a2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b40a2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b40a108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b406bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b406bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb80771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb80771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb80771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b406bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (3163 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# |  #0 0x00005593e39ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593e39e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593e39ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfb2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfb258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfb2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfb251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593e3981bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593e3981a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593e39668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593e3615e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593e3615b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfb251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfb251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfb251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593e3615a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (3164 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/64349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fe4fdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fe4fd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fe4fdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa035e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa035ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa035e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa035e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fe4f70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fe4f70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fe4f558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fe4c04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fe4c04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa035e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa035e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa035e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fe4c04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (3165 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7c06ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7c06e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7c06ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efea2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efea238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efea2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efea231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7c0681bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7c0681a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7c06668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7c0315e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7c0315b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efea231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efea231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efea231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7c0315a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (3166 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr 
# | ...
# `---data was truncated (10240/26240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ce21eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ce21e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ce21ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6160733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f616078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6160733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f616071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ce2182bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ce2182a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ce21678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ce1e16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ce1e16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f616071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f616071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f616071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ce1e16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (3167 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600fd4b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600fd4b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600fd4b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb79733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb7978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb79733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb7971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600fd44ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600fd44ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600fd4338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600fd0e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600fd0e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb7971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb7971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb7971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600fd0e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (3168 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2
# | ...
# `---data was truncated (10240/32570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8c7d10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8c7d0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8c7d1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91c5e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91c5e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91c5e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91c5e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8c7ca6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8c7ca6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8c7c8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8c793ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8c793ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91c5e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91c5e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91c5e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8c793aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (3169 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# |  #0 0x000055e892004eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e892001e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e89200562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c01d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c01d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c01d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c01ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e891f9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e891f9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e891f7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e891c2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e891c2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c01ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c01cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c01cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e891c2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (3170 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a4d784eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a4d781e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a4d78562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1080133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f108018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1080133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f108011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a4d71abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a4d71aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a4d6ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a4d3aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a4d3aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f108011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f108011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f108011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a4d3aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (3171 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb86f68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb86f65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb86f6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a71305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a7135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a71305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a712ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb86efebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb86efea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb86ee38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb86b92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb86b92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a712eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a712ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a712ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb86b92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (3172 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e196d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e196d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e196d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe155733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe15578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe155733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe15571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e1966abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e1966aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e1964f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e192fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e192feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe15571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe15571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe15571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e192fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (3173 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 
# | ...
# `---data was truncated (10240/24206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6c659ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6c6599e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6c659d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43b1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43b14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43b1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43b1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6c6532bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6c6532a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6c65178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6c61c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6c61c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43b1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43b14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43b14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6c61c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (3174 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d27d0f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d27d0f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d27d0f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88c4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88c40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88c4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88c4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d27d08bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d27d08ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d27d0708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d27cd1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d27cd1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88c4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88c40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88c40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d27cd1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (3175 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# |  #0 0x000055b004268eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b004265e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b00426962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19e7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19e7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19e7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19e7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0041febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0041fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0041e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b003e92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b003e92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19e7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19e7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19e7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b003e92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (3176 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>,
# | ...
# `---data was truncated (10240/16521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4b09abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4b09a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4b09ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bae71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4b0941bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4b0941a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4b09268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4b05d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4b05d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bae71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4b05d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (3177 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8607adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8607aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8607ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f4a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f4a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f4a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f4a2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b860743bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b860743a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8607288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8603d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8603d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f4a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f4a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f4a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8603d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (3178 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, a
# | ...
# `---data was truncated (10240/43486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e1bd71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e1bd6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e1bd7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb84933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb8498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb84933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb8491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e1bd07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e1bd07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e1bcec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e1b99be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e1b99bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb8491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb8491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb8491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e1b99ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (3179 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   
# | ...
# `---data was truncated (10240/17536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ea1d20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ea1d1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ea1d2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d70b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d70b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d70b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d70b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea1cb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ea1cb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ea1c9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ea194ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ea194ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d70b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d70b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d70b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea194aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (3180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646a27d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646a27d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646a27d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9004e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9004ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9004e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9004e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646a2769bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646a2769a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646a274e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646a23fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646a23fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9004e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9004e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9004e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646a23fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (3181 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc2c371eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc2c36ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc2c37262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02be533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02be58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02be533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02be51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc2c307bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc2c307a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc2c2ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc2bf9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc2bf9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02be51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02be51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02be51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc2bf9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (3182 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600e302deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600e302ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600e302e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0842049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0842049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0842031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600e2fc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600e2fc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600e2fa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600e2c57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600e2c57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0842032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600e2c57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (3183 of 27910)
******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default<O0>,default<O2>' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.wrapper = type { %struct.task }
# | %struct.task = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" }
# | %"struct.std::coroutine_handle.0" = type { ptr }
# | %"struct.task::promise_type" = type { i8 }
# | %"struct.std::suspend_always" = type { i8 }
# | 
# | $_ZN4task12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN4task12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN4task12promise_type11return_voidEv = comdat any
# | 
# | $_ZN4task12promise_type13final_suspendEv = comdat any
# | 
# | $_ZN7wrapperC1EO4task = comdat any
# | 
# | $_ZN4taskD1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZN7wrapperC2EO4task = comdat any
# | 
# | $_ZN4taskC1EOS_ = comdat any
# | 
# | $_ZN4taskC2EOS_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEaSEDn = comdat any
# | 
# | $_ZN4taskD2Ev = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any
# | 
# | ; Function Attrs: mustprogress nounwind presplitcoroutine
# | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %gro.active = alloca i1, align 1
# |   %__promise = alloca %"struct.task::promise_type", align 1
# |   %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6
# |   %ref.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %ref.tmp2 = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null)
# |   %1 = call i1 @llvm.coro.alloc(token %0)
# |   br i1 %1, label %coro.alloc, label %coro.init
# | 
# | coro.alloc:                                       ; preds = %entry
# |   %2 = call i64 @llvm.coro.size.i64()
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14
# |   br label %coro.init
# | 
# | coro.init:                                        ; preds = %coro.alloc, %entry
# |   %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ]
# |   %4 = call ptr @llvm.coro.begin(token %0, ptr %3)
# |   store i1 false, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %__promise) #9
# |   call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9
# |   call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   store i1 true, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9
# |   call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br i1 %call1, label %init.ready, label %init.suspend
# | 
# | init.suspend:                                     ; preds = %coro.init
# |   %5 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9
# |   %6 = call i8 @llvm.coro.suspend(token %5, i1 false)
# |   switch i8 %6, label %pre.gvo.conv [
# |     i8 0, label %init.ready
# |     i8 1, label %init.cleanup
# |   ]
# | 
# | init.cleanup:                                     ; preds = %init.suspend
# |   br label %cleanup
# | 
# | init.ready:                                       ; preds = %init.suspend, %coro.init
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %init.ready, %init.cleanup
# |   %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9
# |   switch i32 %cleanup.dest.slot.0, label %unreachable [
# |     i32 0, label %cleanup.cont
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | cleanup.cont:                                     ; preds = %cleanup
# |   call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   br label %coro.final
# | 
# | coro.final:                                       ; preds = %cleanup.cont
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9
# |   call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br i1 %call4, label %final.ready, label %final.suspend
# | 
# | final.suspend:                                    ; preds = %coro.final
# |   %7 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9
# |   %8 = call i8 @llvm.coro.suspend(token %7, i1 true)
# |   switch i8 %8, label %pre.gvo.conv [
# |     i8 0, label %final.ready
# |     i8 1, label %final.cleanup
# |   ]
# | 
# | final.cleanup:                                    ; preds = %final.suspend
# |   br label %cleanup5
# | 
# | final.ready:                                      ; preds = %final.suspend, %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br label %cleanup5
# | 
# | cleanup5:                                         ; preds = %final.ready, %final.cleanup
# |   %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9
# |   switch i32 %cleanup.dest.slot.1, label %unreachable [
# |     i32 0, label %pre.gvo.conv
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | pre.gvo.conv:                                     ; preds = %cleanup5, %final.suspend, %init.suspend
# |   %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ]
# |   %InRamp = call i1 @llvm.coro.is_in_ramp()
# |   br i1 %InRamp, label %gro.conv, label %after.gro.conv
# | 
# | gro.conv:                                         ; preds = %pre.gvo.conv
# |   call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9
# |   %cleanup.is_active = load i1, ptr %gro.active, align 1
# |   br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done
# | 
# | cleanup.action:                                   ; preds = %gro.conv
# |   call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9
# |   br label %cleanup.done
# | 
# | cleanup.done:                                     ; preds = %cleanup.action, %gro.conv
# |   br label %after.gro.conv
# | 
# | after.gro.conv:                                   ; preds = %cleanup.done, %pre.gvo.conv
# |   br i1 %9, label %cleanup.cont7, label %coro.ret
# | 
# | cleanup.cont7:                                    ; preds = %after.gro.conv
# |   br label %coro.cleanup
# | 
# | coro.cleanup:                                     ; preds = %cleanup.cont7, %cleanup5, %cleanup
# |   call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9
# |   call void @llvm.lifetime.end.p0(ptr %__promise) #9
# |   %10 = call ptr @llvm.coro.free(token %0, ptr %4)
# |   %11 = icmp ne ptr %10, null
# |   br i1 %11, label %coro.free, label %after.coro.free
# | 
# | coro.free:                                        ; preds = %coro.cleanup
# |   %12 = call i64 @llvm.coro.size.i64()
# |   call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9
# |   br label %after.coro.free
# | 
# | after.coro.free:                                  ; preds = %coro.cleanup, %coro.free
# |   call void @llvm.coro.dead(ptr %4)
# |   br label %coro.ret
# | 
# | coro.ret:                                         ; preds = %after.coro.free, %after.gro.conv
# |   call void @llvm.coro.end(ptr null, i1 false, token none)
# |   ret void
# | 
# | unreachable:                                      ; preds = %cleanup5, %cleanup
# |   unreachable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i1 @llvm.coro.alloc(token) #2
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #3
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i64 @llvm.coro.size.i64() #2
# | 
# | ; Function Attrs: nounwind memory(argmem: readwrite)
# | declare ptr @llvm.coro.begin(token, ptr writeonly) #4
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5
# | 
# | ; Function Attrs: mustprogress nounwind
# | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %this.addr = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8, !tbaa !7
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"s
# | ...
# `---data was truncated (10240/31146) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default<O0>,default<O2>' -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default<O0>,default<O2> -S
# |  #0 0x000055b7eea4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7eea4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7eea4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4757e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4757ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4757e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4757e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7ee9e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7ee9e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7ee9c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7ee677e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7ee677b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4757e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4757e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4757e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7ee677a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (3184 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055734b517eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055734b514e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055734b51862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3eeb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3eeb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3eeb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3eeb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055734b4adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055734b4ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055734b4928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055734b141e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055734b141b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3eeb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3eeb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3eeb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055734b141a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-loongarch.c (3185 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "loongarch32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 4, ptr %res, align 4
# |   store volatile i32 5, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eae4091eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eae408ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eae409262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04b1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04b1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04b1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04b1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eae4027bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eae4027a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eae400c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eae3cbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eae3cbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04b1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04b1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04b1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eae3cbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (3186 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560062f4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560062f47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560062f4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d61905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d6195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d61905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d618ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560062ee0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560062ee0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560062ec58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560062b74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560062b74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d618eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d618ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d618ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560062b74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (3187 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bb4bc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bb4bbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bb4bc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6305e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6305ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6305e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6305e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bb4b56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bb4b56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bb4b3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bb47eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bb47eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6305e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6305e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6305e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bb47eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (3188 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa016aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa016abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa016af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bec849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bec8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bec849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bec831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa01644bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa01644a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa016298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa012d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa012d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bec832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bec8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bec8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa012d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (3189 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b6c9cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b6c9cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b6c9d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82a3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82a32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82a3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82a3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b6c965bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b6c965a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b6c94a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b6c5f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b6c5f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82a3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82a32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82a32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b6c5f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (3190 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a8974ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a89749e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a8974d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecbcc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecbcc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecbcc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecbcc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a896e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a896e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a896c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a89376e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a89376b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecbcc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecbcc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecbcc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a89376a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (3191 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c2b04eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c2b04be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c2b04f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0512649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05126a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0512649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0512631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c2afe4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c2afe4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c2afc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c2ac78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c2ac78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0512632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05126330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05126330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c2ac78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (3192 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c014a6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c014a67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c014a6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a6de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a6dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a6de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a6de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c014a00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c014a00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0149e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c014694e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c014694b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a6de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a6de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a6de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c014694a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (3193 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x 
# | ...
# `---data was truncated (10240/59787) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ceb2f16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ceb2f13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ceb2f1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f030be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f030bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f030be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f030be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ceb2eacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ceb2eaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ceb2e918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ceb2b40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ceb2b40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f030be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f030be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f030be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ceb2b40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (3194 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x bfloa
# | ...
# `---data was truncated (10240/12528) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4756d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4756d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4756d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0272c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0272ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0272c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0272c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f47566dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f47566da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4756528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f475301e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f475301b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0272c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0272c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0272c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f475301a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (3195 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nx
# | ...
# `---data was truncated (10240/25567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc1286eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc1286be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc1286f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00dd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc12804bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc12804a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc127e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc12498e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc12498b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc12498a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (3196 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584f7a41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584f7a3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584f7a4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c73933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c7398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c73933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c7391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584f79d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584f79d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584f79bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584f766be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584f766bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c7391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c7391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c7391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584f766ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (3197 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, pt
# | ...
# `---data was truncated (10240/32402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056127e654eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056127e651e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056127e65562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61f0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61f06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61f0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61f0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056127e5eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056127e5eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056127e5cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056127e27ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056127e27eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61f0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61f06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61f06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056127e27ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (3198 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f0c49beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f0c498e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f0c49c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa759e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa759ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa759e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa759e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f0c431bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f0c431a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f0c4168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f0c0c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f0c0c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa759e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa759e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa759e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f0c0c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (3199 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# |  #0 0x0000558799b02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558799affe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558799b0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac9e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac9e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac9e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac9e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558799a98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558799a98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558799a7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055879972ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055879972cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac9e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac9e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac9e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055879972ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (3200 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c827a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c8279ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c827a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5d6b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5d6b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5d6b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5d6aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c82737bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c82737a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c8271c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c823cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c823cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5d6aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5d6aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5d6aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c823cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (3201 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056035561aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560355617e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056035561b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe99b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe99b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe99b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe99b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603555b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603555b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603555958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560355244e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560355244b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe99b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe99b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe99b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560355244a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (3202 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a5e3d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a5e3cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a5e3d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3e7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3e778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3e7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3e771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a5e368bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a5e368a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a5e34d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a5dffce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a5dffcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3e771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3e771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3e771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a5dffca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (3203 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ef316beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ef3168e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ef316c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faae4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faae4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faae4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faae4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ef3101bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ef3101a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ef30e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ef2d95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ef2d95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faae4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faae4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faae4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ef2d95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (3204 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613d84d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613d84d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613d84da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb49733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb4978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb49733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb4971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613d846fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613d846fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613d84548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613d8103e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613d8103b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb4971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb4971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb4971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613d8103a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (3205 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559563fc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559563fc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559563fc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc04fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc04fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc04fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc04fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559563f59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559563f59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559563f3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559563bede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559563bedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc04fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc04fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc04fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559563beda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (3206 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fd75cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fd75c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fd75cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4976849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49768a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4976849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4976831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fd7561bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fd7561a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fd75468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fd71f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fd71f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4976832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49768330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49768330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fd71f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (3207 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562caeb41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562caeb3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562caeb4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff17bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff17bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff17bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff17bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562caead7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562caead7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562caeabc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cae76be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cae76bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff17bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff17bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff17bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cae76ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (3208 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |  
# | ...
# `---data was truncated (10240/43478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd62025eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd62022e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd6202662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faee1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faee1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faee1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faee1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd61fbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd61fbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd61fa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd61c4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd61c4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faee1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faee1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faee1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd61c4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (3209 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056495c859eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056495c856e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056495c85a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97a6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97a62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97a6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97a6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056495c7efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056495c7efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056495c7d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056495c483e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056495c483b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97a6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97a62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97a62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056495c483a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (3210 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>
# | ...
# `---data was truncated (10240/47764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ef58d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ef58cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ef58d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b6a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b6a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b6a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b6a4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ef5867bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ef5867a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ef584c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ef54fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ef54fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b6a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b6a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b6a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ef54fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (3211 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055854bac6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055854bac3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055854bac762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3691133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f369118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3691133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f369111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055854ba5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055854ba5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055854ba418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055854b6f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055854b6f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f369111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f369111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f369111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055854b6f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (3212 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabi"
# | 
# | %struct.Simple = type { i8, i8 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldrex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldaex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_strex(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %res = alloca i32, align 4
# |   %var = alloca %struct.Simple, align 1
# |   %tmp = alloca i64, align 8
# |   %tmp8 = alloca double, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i32 0, ptr %res, align 4
# |   call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false)
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0)
# |   %1 = load i32, ptr %res, align 4
# |   %or = or i32 %1, %strex
# |   store i32 %or, ptr %res, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2)
# |   %3 = load i32, ptr %res, align 4
# |   %or2 = or i32 %3, %strex1
# |   store i32 %or2, ptr %res, align 4
# |   %4 = load ptr, ptr %addr.addr, align 4
# |   %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4)
# |   %5 = load i32, ptr %res, align 4
# |   %or4 = or i32 %5, %strex3
# |   store i32 %or4, ptr %res, align 4
# |   store i64 42, ptr %tmp, align 8
# |   %6 = load { i32, i32 }, ptr %tmp, align 8
# |   %7 = extractvalue { i32, i32 } %6, 0
# |   %8 = extractvalue { i32, i32 } %6, 1
# |   %9 = load ptr, ptr %addr.addr, align 4
# |   %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9)
# |   %10 = load i32, ptr %res, align 4
# |   %or5 = or i32 %10, %strexd
# |   store i32 %or5, ptr %res, align 4
# |   %11 = load ptr, ptr %addr.addr, align 4
# |   %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11)
# |   %12 = load i32, ptr %res, align 4
# |   %or7 = or i32 %12, %strex6
# |   store i32 %or7, ptr %res, align 4
# |   store double 3.141590e+00, ptr %tmp8, align 8
# |   %13 = load { i32, i32 }, ptr %tmp8, align 8
# |   %14 = extractvalue { i32, i32 } %13, 0
# |   %15 = extractvalue { i32, i32 } %13, 1
# |   %16 = load ptr, ptr %addr.addr, align 4
# |   %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16)
# |   %17 = load i32, ptr %res, align 4
# |   %or10 = or i32 %17, %strexd9
# |   store i32 %or10, ptr %res, align 4
# |   %18 = load ptr, ptr %addr.addr, ali
# | ...
# `---data was truncated (10240/16971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606b1e06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606b1e03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606b1e0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bc5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bc5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bc5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bc5aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606b1d9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606b1d9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606b1d818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606b1a30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606b1a30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bc5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bc5aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bc5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606b1a30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (3213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d6afcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d6afc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d6afcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fd7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fd70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fd7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fd7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d6af60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d6af60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d6af458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d6abf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d6abf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fd7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fd70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fd70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d6abf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (3214 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bbf2ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bbf2fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bbf30062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc27bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc27bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc27bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc27bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bbf295bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bbf295a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bbf27a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bbef29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bbef29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc27bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc27bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc27bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bbef29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (3215 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625745c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625745c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625745c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f692e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f692e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f692e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f692e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056257455cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056257455ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625745418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625741f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625741f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f692e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f692e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f692e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625741f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (3216 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double
# | ...
# `---data was truncated (10240/29119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0e4d15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0e4d12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0e4d1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3c3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3c3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3c3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3c3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0e4cabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0e4caba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0e4c908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0e493fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0e493fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3c3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3c3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3c3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0e493fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (3217 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b2d935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b2d932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b2d93662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7799c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7799c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7799c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7799c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b2d8cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b2d8cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b2d8b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b2d55fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b2d55fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7799c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7799c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7799c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b2d55fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (3218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603678dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603678dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603678e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa31d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa31d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa31d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa31d203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560367875bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560367875a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056036785a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560367509e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560367509b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa31d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa31d2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa31d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560367509a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (3219 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vsc
# | ...
# `---data was truncated (10240/41579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b549f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b549f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b549fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4b1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4b1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4b1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4b1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b5498fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b5498fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b549748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b54623e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b54623b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4b1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4b1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4b1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b54623a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (3220 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c114ab2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c114aafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c114ab362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a3c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a3c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a3c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a3c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c114a48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c114a48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c114a2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1146dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1146dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a3c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a3c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a3c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1146dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (3221 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556af7e1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556af7e17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556af7e1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1662c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1662ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1662c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1662c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556af7db0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556af7db0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556af7d958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556af7a44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556af7a44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1662c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1662c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1662c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556af7a44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (3222 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad6869feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad6869ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad686a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f16b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f16b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f16b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f16b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad68635bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad68635a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad6861a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad682c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad682c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f16b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f16b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f16b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad682c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (3223 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc097a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc097a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc097a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bc4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bc438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bc4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bc431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc0973abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc0973aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc0971f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc093cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc093ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bc431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bc431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bc431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc093cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (3224 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %
# | ...
# `---data was truncated (10240/27994) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623cff92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623cff8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623cff9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdbc01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdbc0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdbc01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdbc003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623cff28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623cff28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623cff0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623cfbbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623cfbbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdbc004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdbc0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdbc0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623cfbbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (3225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055905586ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559055869e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055905586d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3a8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3a82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3a8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3a8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559055802bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559055802a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590557e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559055496e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559055496b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3a8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3a82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3a82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559055496a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (3226 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vtdiscard() #0 {
# | entry:
# |   call void @llvm.riscv.sf.vtdiscard()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtdiscard() #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617bacdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617bacdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617bace062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabd5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabd5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabd5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabd5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617bac75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617bac75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617bac5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617ba909e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617ba909b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabd5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabd5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabd5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617ba909a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (3227 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | 
# | ...
# `---data was truncated (10240/34641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055feac912eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055feac90fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055feac91362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb5d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb5d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb5d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb5d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feac8a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055feac8a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055feac88d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055feac53ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055feac53cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb5d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb5d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb5d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055feac53ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (3228 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8d8593eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8d8590e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8d859462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f181641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18164725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f181641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1816403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8d8529bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8d8529a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8d850e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8d81bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8d81bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1816404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18164050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18164050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8d81bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (3229 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599675d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599675cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599675d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f837fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f837faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f837fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f837fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559967568bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559967568a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055996754d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599671fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599671fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f837fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f837fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f837fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599671fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (3230 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055befe76aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055befe767e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055befe76b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6d1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6d1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6d1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6d1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055befe700bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055befe700a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055befe6e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055befe394e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055befe394b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6d1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6d1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6d1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055befe394a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (3231 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db0e4a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db0e49fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db0e4a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3cf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3cf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3cf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3cf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db0e438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db0e438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db0e41d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db0e0cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db0e0ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3cf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3cf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3cf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db0e0cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (3232 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.
# | ...
# `---data was truncated (10240/14900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591e3613eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591e3610e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591e361462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3d2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3d238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3d2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3d231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591e35a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591e35a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591e358e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591e323de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591e323db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3d231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3d231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3d231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591e323da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (3233 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e558d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e558d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e558d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2781905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f278195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2781905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27818ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e5586bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e5586ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e558508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e554ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e554ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27818eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27818ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27818ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e554ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (3234 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557607d44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557607d41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557607d4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cecf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cecf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cecf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ceceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557607cdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557607cdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557607cbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055760796ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055760796eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ceceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ceceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ceceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055760796ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (3235 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606a42d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606a42d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606a42d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac56533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac5658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac56533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac5651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606a426abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606a426aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606a424f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606a3efee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606a3efeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac5651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac5651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac5651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606a3efea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (3236 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 
# | ...
# `---data was truncated (10240/39417) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562aef9eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562aef9e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562aef9eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9205449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92054a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9205449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9205431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aef980bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562aef980a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562aef9658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562aef614e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562aef614b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9205432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92054330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92054330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562aef614a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (3237 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b183f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b183f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b183f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8421133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f842118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8421133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f842111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b18389bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b18389a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b1836e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b1801de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b1801db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f842111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f842111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f842111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b1801da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (3238 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570bca94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570bca91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570bca9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90d9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90d94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90d9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90d9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570bca2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570bca2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570bca0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570bc6bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570bc6beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90d9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90d94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90d94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570bc6bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (3239 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# |  #0 0x00005653ed7b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653ed7b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653ed7ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37e6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37e62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37e6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37e6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653ed74fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653ed74fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653ed7348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653ed3e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653ed3e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37e6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37e62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37e62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653ed3e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (3240 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a461270eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a46126de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a46127162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bb5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bb515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bb5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bb50ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a461206bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a461206a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4611eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a460e9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a460e9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bb50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bb50ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bb50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a460e9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (3241 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f111cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f111c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f111cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc917733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc91778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc917733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc91771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f11162bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f11162a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f111478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f10df6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f10df6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc91771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc91771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc91771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f10df6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (3242 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0fe46beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0fe468e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0fe46c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a60049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a600a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a60049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a60031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0fe401bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0fe401a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0fe3e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0fe095e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0fe095b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a60032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a600330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a600330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0fe095a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (3243 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d68ed5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d68ed5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d68ed6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faecd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faecd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faecd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faecd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d68ecf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d68ecf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d68ecda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d68e989e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d68e989b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faecd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faecd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faecd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d68e989a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (3244 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ad32aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ad32a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ad32ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6ebd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6ebd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6ebd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6ebd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ad3242bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ad3242a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ad32278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ad2ed6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ad2ed6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6ebd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6ebd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6ebd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ad2ed6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (3245 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055725ff3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055725ff39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055725ff3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f047ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f047ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f047ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f047ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055725fed2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055725fed2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055725feb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055725fb66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055725fb66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f047ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f047ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f047ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055725fb66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (3246 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df23e2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df23e27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df23e2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe127d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe127d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe127d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe127ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df23dc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df23dc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df23da58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df23a54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df23a54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe127ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe127cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe127cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df23a54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (3247 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579f029aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579f0297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579f029b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f974c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f974c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f974c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f974c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579f0230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579f0230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579f02158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579efec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579efec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f974c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f974c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f974c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579efec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/X86/sse.c (3248 of 27910)
******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b403f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b403f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b403f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f032f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f032f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f032f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f032f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b4038ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b4038ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b403738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b40022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b40022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f032f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f032f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f032f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b40022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (3249 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590f946feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590f946ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590f947062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f802bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f802bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f802bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f802bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590f9405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590f9405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590f93ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590f9099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590f9099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f802bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f802bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f802bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590f9099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (3250 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b2c26eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b2c26be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b2c26f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0983d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0983d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0983d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0983d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b2c204bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b2c204a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b2c1e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b2be98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b2be98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0983d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0983d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0983d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b2be98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (3251 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aed1bb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aed1bb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aed1bb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2fdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2fdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2fdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2fdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aed1b49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aed1b49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aed1b2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aed17dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aed17ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2fdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2fdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2fdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aed17dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (3252 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# |  #0 0x000055cf6e30beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf6e308e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf6e30c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88a7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88a7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88a7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88a7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf6e2a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf6e2a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf6e2868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf6df35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf6df35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88a7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88a7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88a7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf6df35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (3253 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c9db05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c9db02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c9db0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b54a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b54a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b54a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b54a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c9da9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c9da9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c9da808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c9d72fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c9d72fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b54a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b54a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b54a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c9d72fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (3254 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %
# | ...
# `---data was truncated (10240/15051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa48715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa48712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa4871662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c4d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c4d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c4d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c4d0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa486abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa486aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa486908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa4833fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa4833fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c4d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c4d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c4d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa4833fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (3255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620744c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620744c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620744ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd610f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd610f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd610f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd610f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056207445fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056207445fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620744448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620740f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620740f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd610f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd610f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd610f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620740f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (3256 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563050c46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563050c43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563050c4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f860f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f860f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f860f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f860f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563050bdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563050bdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563050bc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563050870e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563050870b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f860f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f860f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f860f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563050870a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (3257 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/34633) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a82a5d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a82a5cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a82a5d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6a5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6a578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6a5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6a571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a82a566bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a82a566a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a82a54b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a82a1fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a82a1fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6a571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6a571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6a571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a82a1faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (3258 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   %1 = fpext bfloat %0 to float
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   %1 = fptrunc float %0 to bfloat
# |   ret bfloat %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055761f94deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055761f94ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055761f94e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91e2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91e24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91e2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91e2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055761f8e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055761f8e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055761f8c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055761f577e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055761f577b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91e2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91e24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91e24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055761f577a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (3259 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c697c28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c697c25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c697c2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca9ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca9aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca9ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca9ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c697bbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c697bbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c697ba38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c697852e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c697852b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca9ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca9ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca9ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c697852a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (3260 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c15c49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c15c46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c15c4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe183733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe18378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe183733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe18371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c15bdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c15bdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c15bc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c15873e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c15873b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe18371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe18371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe18371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c15873a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (3261 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3a5714eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3a5711e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3a571562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4948d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4948d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4948d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4948d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3a56aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3a56aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3a568f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3a533ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3a533eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4948d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4948d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4948d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3a533ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (3262 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0efd11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0efd0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0efd1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f201fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f201fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f201fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f201fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0efca7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0efca7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0efc8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0ef93be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0ef93bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f201fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f201fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f201fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0ef93ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (3263 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %1, <vsc
# | ...
# `---data was truncated (10240/12290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055989933deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055989933ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055989933e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d5cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d5cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d5cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d5cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598992d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598992d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598992b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559898f67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559898f67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d5cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d5cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d5cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559898f67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (3264 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e05a208eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e05a205e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e05a20962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36ba21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36ba2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36ba21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36ba203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e05a19ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e05a19ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e05a1838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e059e32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e059e32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36ba204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36ba2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36ba2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e059e32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (3265 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572f67a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572f67a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572f67a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0936b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0936b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0936b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0936aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572f673bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572f673ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572f67208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572f63cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572f63cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0936aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0936aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0936aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572f63cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (3266 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @or_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %or = or <32 x i8> %0, %1
# |   store <32 x i8> %or, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 
# | ...
# `---data was truncated (10240/30877) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005637ed57deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637ed57ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637ed57e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c3c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637ed513bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637ed513a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637ed4f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637ed1a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637ed1a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87c3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c3c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637ed1a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (3267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f360748eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f360745e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f36074962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdde0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdde0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdde0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdde0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3606debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3606dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3606c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f360372e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f360372b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdde0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdde0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdde0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f360372a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (3268 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.
# | ...
# `---data was truncated (10240/24951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563724962eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056372495fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056372496362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd74133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd7418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd74133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd7411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637248f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637248f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637248dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056372458ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056372458cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd7411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd7411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd7411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056372458ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (3269 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588d5994eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588d5991e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588d599562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f825b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f825b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f825b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f825b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588d592abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588d592aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588d590f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588d55bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588d55beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f825b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f825b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f825b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588d55bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (3270 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c369953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c369950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c36995462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38fe933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38fe98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38fe933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38fe91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3698e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3698e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3698ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c36957de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c36957db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38fe91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38fe91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38fe91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c36957da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (3271 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556112034eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556112031e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055611203562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b07249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b072a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b07249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b07231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556111fcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556111fcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556111faf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556111c5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556111c5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b07232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b072330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b072330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556111c5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (3272 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556270b29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556270b26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556270b2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc785049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7850a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc785049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc785031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556270abfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556270abfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556270aa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556270753e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556270753b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc785032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7850330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7850330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556270753a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (3273 of 27910)
******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | @con_unify_unimap_p1 = global ptr null, align 8
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @con_unify_unimap_q1() #0 {
# | entry:
# |   %p.addr.i = alloca ptr, align 8
# |   %q.addr.i = alloca ptr, align 8
# |   %size.addr.i = alloca i64, align 8
# |   %0 = load ptr, ptr @con_unify_unimap_p1, align 8
# |   store ptr %0, ptr %p.addr.i, align 8
# |   store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8
# |   store i64 4, ptr %size.addr.i, align 8
# |   %1 = load ptr, ptr %p.addr.i, align 8
# |   %2 = load ptr, ptr %q.addr.i, align 8
# |   %3 = load i64, ptr %size.addr.i, align 8
# |   %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2
# |   ret i32 %call.i
# | }
# | 
# | ; Function Attrs: alwaysinline nobuiltin nounwind
# | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #2 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# |  #0 0x0000561aad6d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561aad6d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561aad6d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7265b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7265b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7265b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7265b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aad66bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561aad66ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561aad6508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561aad2ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561aad2ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7265b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7265b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7265b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aad2ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (3274 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d81960eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d8195de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d8196162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc05533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc0558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc05533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc0551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d818f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d818f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d818db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d8158ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d8158ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc0551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc0551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc0551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d8158aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (3275 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ab805aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ab8057e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ab805b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f753e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f753e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f753e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f753e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ab7ff0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ab7ff0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ab7fd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ab7c84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ab7c84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f753e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f753e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f753e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ab7c84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (3276 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/11849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a6bf73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a6bf70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a6bf7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e47649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e476a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e47649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e47631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a6bf09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a6bf09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a6beee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a6bb9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a6bb9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e47632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e476330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e476330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a6bb9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-endianness.c (3277 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-arm-none-eabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 2
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 3
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 1
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# |  #0 0x000055ae6e61beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae6e618e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae6e61c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff15d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff15d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff15d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff15d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae6e5b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae6e5b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae6e5968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae6e245e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae6e245b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff15d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff15d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff15d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae6e245a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (3278 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3ef0c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3ef0c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3ef0ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f680cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f680cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f680cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f680cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3ef05fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3ef05fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3ef0448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3eecf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3eecf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f680cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f680cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f680cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3eecf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (3279 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a40b3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a40b38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a40b3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d69505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d6955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d69505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d694ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a40ad1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a40ad1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a40ab68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a40765e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a40765b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d694eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d694ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d694ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a40765a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (3280 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561463293eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561463290e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056146329462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc575933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc57598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc575933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc57591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561463229bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561463229a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056146320e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561462ebde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561462ebdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc57591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc57591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc57591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561462ebda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (3281 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563146129eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563146126e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056314612a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71b0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71b098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71b0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71b091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631460bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631460bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631460a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563145d53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563145d53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71b091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71b091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71b091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563145d53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (3282 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651a2384eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651a2381e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651a238562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fade7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fade7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fade7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fade7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651a231abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651a231aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651a22ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651a1faee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651a1faeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fade7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fade7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fade7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651a1faea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (3283 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c0260feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c0260ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c0261062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a01d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a01d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a01d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a01d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c025a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c025a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c0258a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c02239e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c02239b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a01d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a01d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a01d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c02239a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (3284 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e4be0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e4be0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e4be1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9586333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f958638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9586333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f958631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e4bda5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e4bda5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e4bd8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e4ba39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e4ba39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f958631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f958631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f958631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e4ba39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (3285 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e32d8cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e32d8c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e32d8cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9992f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9992f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9992f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9992f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e32d861bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e32d861a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e32d8468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e32d4f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e32d4f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9992f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9992f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9992f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e32d4f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (3286 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056499f0d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056499f0d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056499f0d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f593f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f593f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f593f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f593f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056499f06bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056499f06ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056499f0508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056499ecffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056499ecffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f593f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f593f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f593f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056499ecffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (3287 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e3b9dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e3b9d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e3b9dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35f0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35f058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35f0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35f051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e3b971bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e3b971a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e3b9568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e3b605e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e3b605b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35f051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35f051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35f051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e3b605a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (3288 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626f5d67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626f5d64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626f5d6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06c6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06c6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06c6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06c6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626f5cfdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626f5cfda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626f5ce28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626f5991e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626f5991b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06c6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06c6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06c6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626f5991a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (3289 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @ll
# | ...
# `---data was truncated (10240/20090) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbd4864eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbd4861e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbd486562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff81e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff81e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff81e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff81e0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbd47fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbd47faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbd47df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbd448ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbd448eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff81e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff81e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff81e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbd448ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (3290 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align
# | ...
# `---data was truncated (10240/29111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609da54eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609da54be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609da54f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4f4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4f438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4f4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4f431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609da4e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609da4e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609da4c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609da178e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609da178b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4f431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4f431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4f431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609da178a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (3291 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558426a77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558426a74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558426a7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a9f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a9f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a9f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a9f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558426a0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558426a0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584269f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584266a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584266a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a9f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a9f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a9f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584266a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (3292 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055560b3feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055560b3fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055560b3ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96ab449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96ab4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96ab449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96ab431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055560b394bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055560b394a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055560b3798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055560b028e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055560b028b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96ab432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96ab4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96ab4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055560b028a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (3293 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/34581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d9d00aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d9d007e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d9d00b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef69649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef696a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef69649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef69631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d9cfa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d9cfa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d9cf858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d9cc34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d9cc34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef69632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef696330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef696330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d9cc34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (3294 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f5a4afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f5a4ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f5a4b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f627eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f627eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f627eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f627eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f5a445bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f5a445a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f5a42a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f5a0d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f5a0d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f627eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f627eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f627eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f5a0d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (3295 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d50cb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d50cb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d50cb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79c9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79c938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79c9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79c931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d50c4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d50c4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d50c2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d508dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d508deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79c931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79c931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79c931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d508dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (3296 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i6
# | ...
# `---data was truncated (10240/11946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdfb67ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdfb679e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdfb67d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08ba133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08ba18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08ba133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08ba11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdfb612bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdfb612a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdfb5f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdfb2a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdfb2a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08ba11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08ba11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08ba11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdfb2a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (3631 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639ba021eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639ba01ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639ba02262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6b3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6b318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6b3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6b311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639b9fb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639b9fb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639b9f9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639b9c4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639b9c4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6b311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6b311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6b311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639b9c4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90..
********************
Failed Tests (3297):
  Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c
  Clang :: CodeGen/2005-09-24-AsmUserPrefix.c
  Clang :: CodeGen/2008-07-17-no-emit-on-error.c
  Clang :: CodeGen/AArch64/atomic-hint-template.cpp
  Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c
  Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c
  Clang :: CodeGen/AArch64/fp8-cast.c
  Clang :: CodeGen/AArch64/fp8-extract.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/neon-2velem.c
  Clang :: CodeGen/AArch64/neon-3v.c
  Clang :: CodeGen/AArch64/neon-dot-product.c
  Clang :: CodeGen/AArch64/neon-extract.c
  Clang :: CodeGen/AArch64/neon-fma.c
  Clang :: CodeGen/AArch64/neon-fp16fml.c
  Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon-intrinsics.c
  Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c
  Clang :: CodeGen/AArch64/neon-misc-constrained.c
  Clang :: CodeGen/AArch64/neon-misc.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c
  Clang :: CodeGen/AArch64/neon-shifts.c
  Clang :: CodeGen/AArch64/neon-tbl.c
  Clang :: CodeGen/AArch64/neon-vcmla.c
  Clang :: CodeGen/AArch64/neon-vcombine.c
  Clang :: CodeGen/AArch64/neon-vget-hilo.c
  Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c
  Clang :: CodeGen/AArch64/neon/add.c
  Clang :: CodeGen/AArch64/neon/bf16-getset.c
  Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c
  Clang :: CodeGen/AArch64/neon/f16-getset.c
  Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiply.c
  Clang :: CodeGen/AArch64/neon/getset.c
  Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon/intrinsics.c
  Clang :: CodeGen/AArch64/neon/load.c
  Clang :: CodeGen/AArch64/neon/perm.c
  Clang :: CodeGen/AArch64/neon/rounding-v8.5.c
  Clang :: CodeGen/AArch64/neon/rounding.c
  Clang :: CodeGen/AArch64/neon/store.c
  Clang :: CodeGen/AArch64/neon/subtraction.c
  Clang :: CodeGen/AArch64/neon/vpaddl.c
  Clang :: CodeGen/AArch64/neon/widen.c
  Clang :: CodeGen/AArch64/poly128.c
  Clang :: CodeGen/AArch64/poly64.c
  Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
  Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
  Clang :: CodeGen/AArch64/sve-vector-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vector-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vector-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c
  Clang :: CodeGen/AArch64/sve-vls-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vls-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vls-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c
  Clang :: CodeGen/AArch64/sve/addv.c
  Clang :: CodeGen/AArch64/sve/andv.c
  Clang :: CodeGen/AArch64/sve/dup.c
  Clang :: CodeGen/AArch64/sve/eorv.c
  Clang :: CodeGen/AArch64/sve/len.c
  Clang :: CodeGen/AArch64/sve/maxnmv.c
  Clang :: CodeGen/AArch64/sve/maxv.c
  Clang :: CodeGen/AArch64/sve/minnmv.c
  Clang :: CodeGen/AArch64/sve/minv.c
  Clang :: CodeGen/AArch64/sve/nand.c
  Clang :: CodeGen/AArch64/sve/nor.c
  Clang :: CodeGen/AArch64/sve/orn.c
  Clang :: CodeGen/AArch64/sve/orv.c
  Clang :: CodeGen/AArch64/sve/pfalse.c
  Clang :: CodeGen/AArch64/sve/recpe.c
  Clang :: CodeGen/AArch64/sve/recps.c
  Clang :: CodeGen/AArch64/sve/rsqrte.c
  Clang :: CodeGen/AArch64/sve/rsqrts.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
  Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
  Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
  Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/builtin-cpu-is.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c
  Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c
  Clang :: CodeGen/RISCV/riscv-xcvalu.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c
  Clang :: CodeGen/RISCV/rvp-intrinsics.c
  Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/SystemZ/zvector.c
  Clang :: CodeGen/WebAssembly/builtins-table-externref.c
  Clang :: CodeGen/WebAssembly/builtins-table-funcref.c
  Clang :: CodeGen/X86/avx-cmp-builtins.c
  Clang :: CodeGen/X86/avx-shuffle-builtins.c
  Clang :: CodeGen/X86/bfloat16-convert-half.c
  Clang :: CodeGen/X86/sse.c
  Clang :: CodeGen/aapcs-bitfield.c
  Clang :: CodeGen/arm-bf16-convert-intrinsics.c
  Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c
  Clang :: CodeGen/arm-bf16-params-returns.c
  Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/arm-cde-gpr.c
  Clang :: CodeGen/arm-cde-reinterpret.c
  Clang :: CodeGen/arm-cde-vec.c
  Clang :: CodeGen/arm-cde-vfp.c
  Clang :: CodeGen/arm-crc32.c
  Clang :: CodeGen/arm-mfp8.c
  Clang :: CodeGen/arm-mve-intrinsics/absneg.c
  Clang :: CodeGen/arm-mve-intrinsics/admin.c
  Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/compare.c
  Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp
  Clang :: CodeGen/arm-mve-intrinsics/dup.c
  Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c
  Clang :: CodeGen/arm-mve-intrinsics/idup.c
  Clang :: CodeGen/arm-mve-intrinsics/load-store.c
  Clang :: CodeGen/arm-mve-intrinsics/predicates.c
  Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c
  Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c
  Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c
  Clang :: CodeGen/arm-mve-intrinsics/ternary.c
  Clang :: CodeGen/arm-mve-intrinsics/vabavq.c
  Clang :: CodeGen/arm-mve-intrinsics/vabdq.c
  Clang :: CodeGen/arm-mve-intrinsics/vadc.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddv.c
  Clang :: CodeGen/arm-mve-intrinsics/vandq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbicq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vclz.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c
  Clang :: CodeGen/arm-mve-intrinsics/veorq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vld24.c
  Clang :: CodeGen/arm-mve-intrinsics/vldr.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminvq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovl.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vornq.c
  Clang :: CodeGen/arm-mve-intrinsics/vorrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrev.c
  Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrnd.c
  Clang :: CodeGen/arm-mve-intrinsics/vshlc.c
  Clang :: CodeGen/arm-mve-intrinsics/vsubq.c
  Clang :: CodeGen/arm-neon-directed-rounding-constrained.c
  Clang :: CodeGen/arm-neon-directed-rounding.c
  Clang :: CodeGen/arm-neon-dot-product.c
  Clang :: CodeGen/arm-neon-endianness.c
  Clang :: CodeGen/arm-neon-fma.c
  Clang :: CodeGen/arm-neon-numeric-maxmin.c
  Clang :: CodeGen/arm-neon-shifts.c
  Clang :: CodeGen/arm-neon-vcadd.c
  Clang :: CodeGen/arm-neon-vcvtX.c
  Clang :: CodeGen/arm-neon-vget.c
  Clang :: CodeGen/arm-neon-vld.c
  Clang :: CodeGen/arm-neon-vst.c
  Clang :: CodeGen/arm-poly-add.c
  Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c
  Clang :: CodeGen/arm-vector_type-params-returns.c
  Clang :: CodeGen/arm64-crc32.c
  Clang :: CodeGen/arm64-lanes.c
  Clang :: CodeGen/arm64_vcopy.c
  Clang :: CodeGen/arm64_vcreate.c
  Clang :: CodeGen/arm64_vdupq_n_f64.c
  Clang :: CodeGen/arm_acle.c
  Clang :: CodeGen/arm_acle_swp.c
  Clang :: CodeGen/arm_neon_intrinsics.c
  Clang :: CodeGen/attr-counted-by-issue200014.c
  Clang :: CodeGen/builtin-align.c
  Clang :: CodeGen/builtins-arm-exclusive.c
  Clang :: CodeGen/builtins-arm.c
  Clang :: CodeGen/builtins-arm64.c
  Clang :: CodeGen/builtins-loongarch.c
  Clang :: CodeGen/builtins-riscv.c
  Clang :: CodeGen/cx-complex-range-real.c
  Clang :: CodeGen/cx-complex-range.c
  Clang :: CodeGen/distributed-thin-lto/backend-skip.ll
  Clang :: CodeGen/distributed-thin-lto/basic.ll
  Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll
  Clang :: CodeGen/distributed-thin-lto/cfi.ll
  Clang :: CodeGen/distributed-thin-lto/newpm.ll
  Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll
  Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
  Clang :: CodeGen/linker-diagnostic.ll
  Clang :: CodeGen/memcmp-inline-builtin-to-asm.c
  Clang :: CodeGen/mozilla-ms-inline-asm.c
  Clang :: CodeGen/packed-structure.c
  Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
  Clang :: CodeGen/thinlto-funcattr-prop.ll
  Clang :: CodeGen/thinlto-multi-module.ll
  Clang :: CodeGen/thinlto-opaque-typed-mix.ll
  Clang :: CodeGen/thinlto_backend.ll
  Clang :: CodeGen/thinlto_backend_local_name_conflict.ll
  Clang :: CodeGen/thinlto_embed_bitcode.ll
  Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
  Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
  Clang :: CodeGenCXX/attr-musttail.cpp
  Clang :: CodeGenCXX/ctor-globalopt.cpp
  Clang :: CodeGenCXX/inline-then-fold-variadics.cpp
  Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll
  Clang :: CodeGenCXX/virtual-base-ctor.cpp
  Clang :: CodeGenCoroutines/coro-gro4.cpp
  Clang :: CodeGenCoroutines/pr65054.cpp
  Clang :: CodeGenHIP/offload-pgo-sections.hip
  Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
  Clang :: Modules/pr93497.cppm


Testing Time: 170.66s

Total Discovered Tests: 55926
  Skipped          :    37 (0.07%)
  Unsupported      :  1675 (3.00%)
  Passed           : 50888 (90.99%)
  Expectedly Failed:    29 (0.05%)
  Failed           :  3297 (5.90%)
FAILED: gen/clang/test/run-lit 
python3 bin/llvm-lit -sv ../../clang/test
ninja: build stopped: subcommand failed.
Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.